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21. 发明申请

US20090228981A1 Method For Securely Communicating Information About The Location Of A Compromised Computing Device 有权
标题翻译：用于安全地沟通关于被破坏的计算设备的位置的信息的方法
公开(公告)号：US20090228981A1
公开(公告)日：2009-09-10
申请号：US12208626
申请日：2008-09-11
申请人： Martyn Ryan Shirlen , Richard Gerard Hofmann
发明人： Martyn Ryan Shirlen , Richard Gerard Hofmann
IPC分类号： G06F21/00
CPC分类号： H04L63/1441 , G06F21/55 , G06F21/554 , G06F21/73 , G06F21/88
摘要： A method for securely reporting location information after an attack on a computing device is presented. Such information may be reported to a requesting entity in a manner almost transparent to an attacker. Several exemplary embodiments of systems wherein the method may be used are presented.
摘要翻译：提出了在对计算设备的攻击之后安全地报告位置信息的方法。这样的信息可以以对攻击者几乎透明的方式报告给请求实体。呈现了可以使用该方法的系统的几个示例性实施例。

22. 发明申请

US20080301342A1 Device Directed Memory Barriers 有权
标题翻译：设备定向内存障碍
公开(公告)号：US20080301342A1
公开(公告)日：2008-12-04
申请号：US11756643
申请日：2007-06-01
申请人： Richard Gerard Hofmann , Jaya Prakash Ganasan , Barry Joe Wolford
发明人： Richard Gerard Hofmann , Jaya Prakash Ganasan , Barry Joe Wolford
IPC分类号： G06F13/42 , G06F13/00
CPC分类号： G06F13/1621 , G06F13/4234 , Y02D10/14 , Y02D10/151
摘要： Efficient techniques for controlling synchronization of bus transactions to improve performance and reduce power requirements in a shared memory system are described. Interconnect arrangements in complex processing systems are also described that provide efficient data transfers between bus masters and shared memory devices to improve performance and reduce power use. In one example, a method for controlling synchronization of bus transactions to remote devices is addressed. A device directed memory barrier command is received. The device directed memory barrier command is decoded to determine one or more destination devices. A memory barrier command is selectively routed to the one or more destination devices in response to the decoding. The described techniques combine high speed device directed memory barrier capability, improved bus bandwidth functionality, and power saving features.
摘要翻译：描述了用于控制总线事务的同步以提高性能并降低共享存储器系统中的功率需求的高效技术。还描述了在复杂处理系统中的互连布置，其提供总线主机和共享存储器件之间的有效数据传输，以提高性能并减少功率使用。在一个示例中，解决了用于控制总线事务到远程设备的同步的方法。接收设备定向存储器障碍命令。解码器件定向存储器障碍命令以确定一个或多个目的地设备。响应于解码，存储器屏障命令被选择性地路由到一个或多个目的地设备。所描述的技术结合了高速设备定向存储器屏障能力，改进的总线带宽功能和省电功能。

23. 发明申请

US20070201506A1 Cooperative Writes Over the Address Channel of a Bus 有权
标题翻译：总线地址通道上的合作写入
公开(公告)号：US20070201506A1
公开(公告)日：2007-08-30
申请号：US11468908
申请日：2006-08-31
申请人： Richard Gerard Hofmann , Terence J. Lohman
发明人： Richard Gerard Hofmann , Terence J. Lohman
IPC分类号： H04J15/00
CPC分类号： G06F13/4243 , G06F13/42 , G06F13/4273
摘要： A processing system and method for communicating in a processing system over a bus is disclosed. The processing system includes a receiving device, a bus having first, second and third channels, and a sending device configured to address the receiving device on the first channel, and read a payload from the receiving device on the second channel, the sending device being further configured to write a first portion of a payload to the receiving device on the first channel and a second portion of the payload to the receiving device on the third channel.
摘要翻译：公开了一种用于通过总线在处理系统中通信的处理系统和方法。处理系统包括接收装置，具有第一，第二和第三信道的总线，以及配置成在第一信道上寻址接收装置并从第二信道上的接收装置读取有效载荷的发送装置，发送装置是还被配置为将所述有效负载的第一部分写入所述第一信道上的所述接收设备，并且将所述有效载荷的第二部分写入所述第三信道上的接收设备。

24. 发明授权

US07096297B2 System and method for delaying an interrupt request until corresponding data is provided to a destination device 失效
标题翻译：用于延迟中断请求的系统和方法，直到向目标设备提供相应的数据
公开(公告)号：US07096297B2
公开(公告)日：2006-08-22
申请号：US10804873
申请日：2004-03-19
申请人： Richard Gerard Hofmann , Jason Michael Hopp , Dennis Charles Wilkerson
发明人： Richard Gerard Hofmann , Jason Michael Hopp , Dennis Charles Wilkerson
IPC分类号： G06F13/24 , G06F9/46
CPC分类号： G06F13/24
摘要： A method and system for forwarding interrupt requests from a source device to a destination device. A controller bridge receives data, from a source device, for a destination device and stores the incoming data in a data queue. An interrupt request is received from the source device for the destination device and forwarded to the destination device in response to completing a transfer of the data from the source device to the destination device. If data received from the source device for the destination device are pending in the data queue, the interrupt request is rejected and the source may resubmit the interrupt request at a later time. If additional data are received from the source device for the destination device, the data may be rejected in response to an interrupt pending in the interrupt queue from the source device for the destination device.
摘要翻译：一种用于将来自源设备的中断请求转发到目的地设备的方法和系统。控制器桥接器从源设备接收用于目的地设备的数据，并将输入数据存储在数据队列中。响应于完成从源设备到目的地设备的数据传输，从目的地设备的源设备接收到中断请求并转发到目的地设备。如果数据队列中从目标设备的源设备接收到的数据处于待处理状态，则中断请求被拒绝，并且源可能会在稍后重新提交中断请求。如果从目标设备的源设备接收到附加数据，则响应于来自目的设备的源设备的中断队列中的等待中断，数据可能被拒绝。

25. 发明授权

US06985972B2 Dynamic cache coherency snooper presence with variable snoop latency 有权
标题翻译：动态缓存一致性snooper存在与可变侦听延迟
公开(公告)号：US06985972B2
公开(公告)日：2006-01-10
申请号：US10264163
申请日：2002-10-03
申请人： James Norris Dieffenderfer , Bernard Charles Drerup , Jaya Prakash Subramaniam Ganasan , Richard Gerard Hofmann , Thomas Andrew Sartorius , Thomas Philip Speier , Barry Joe Wolford
发明人： James Norris Dieffenderfer , Bernard Charles Drerup , Jaya Prakash Subramaniam Ganasan , Richard Gerard Hofmann , Thomas Andrew Sartorius , Thomas Philip Speier , Barry Joe Wolford
IPC分类号： G06F13/28 , G06F12/00
CPC分类号： G06F13/366 , G06F12/0831 , G06F2212/1028 , G06F2213/0038 , Y02D10/13 , Y02D10/14
摘要： A data processing system with a snooper that is capable of dynamically enabling and disabling its snooping capabilities (i.e., snoop detect and response). The snooper is connected to a bus controller via a plurality of interconnects, including a snooperPresent signal, a snoop response signal and a snoop detect signal. When the snooperPresent signal is asserted, subsequent snoop requests are sent to the snooper, and the snooper is polled for a snoop response. Each snooper is capable of responding at different times (i.e., each snooper operates with different snoop latencies). The bus controller individually tracks the snoop response received from each snooper with the snooperPresent signal enabled. Whenever the snooper wishes to deactivate its snooping capabilities/operations, the snooper de-asserts the snooperPresent signal. The bus controller recognizes this as an indication that the snooper is unavailable. Thus, when the bus controller broadcasts subsequent snoop requests, the bus controller does not send the snoop request to the snooper.
摘要翻译：具有能够动态地启用和禁用其窥探能力（即，窥探检测和响应）的窥探者的数据处理系统。窥探者通过多个互连连接到总线控制器，包括窥探信号，窥探响应信号和窥探检测信号。当snooperPresent信号被断言时，后续的窥探请求被发送到snooper，并且窥探者被轮询以进行侦听响应。每个窥探者都能够在不同的时间进行响应（即，每个窥探者使用不同的侦听延迟进行操作）。总线控制器单独跟踪snooperPresent信号启用时从每个窥探者接收的窥探响应。只要窥探者希望取消其窥探能力/操作，窥探者将断言snooperPresent信号。总线控制器将此识别为snooper不可用的指示。因此，当总线控制器广播后续的窥探请求时，总线控制器不向窥探者发送窥探请求。

26. 发明授权

US06513089B1 Dual burst latency timers for overlapped read and write data transfers 失效
标题翻译：用于重叠读和写数据传输的双突发等待时间计时器
公开(公告)号：US06513089B1
公开(公告)日：2003-01-28
申请号：US09574101
申请日：2000-05-18
申请人： Richard Gerard Hofmann , Peter Dean LaFauci , Dennis Charles Wilkerson
发明人： Richard Gerard Hofmann , Peter Dean LaFauci , Dennis Charles Wilkerson
IPC分类号： G06F100
CPC分类号： G06F13/28
摘要： The present invention discloses a method and system for managing independent read and write buses by dividing the pending read and write request signals and the read and write request priority level signals. The arbitration for use of the read and write buses are done independently for the read and write operations. A higher priority read, for example, can be concurrent with a corresponding lower priority write. Interruption of in process reads or writes is also done using the split arbitrations of the read and write buses leading the disruption of lower priority operations only if the conflicts are concurrent for the same read or write operation.
摘要翻译：本发明公开了一种通过划分未决读和写请求信号和读和写请求优先级信号来管理独立读和写总线的方法和系统。用于读写总线的仲裁是独立完成的，用于读写操作。例如，较高优先级读取可以与相应的较低优先级写入并发。只有在相同的读取或写入操作的冲突是并发的情况下，进程读取或写入的中断也是使用读取和写入总线的拆分仲裁来引导较低优先级操作的中断。

27. 发明申请

US20130064337A1 Method and Apparatus for Adaptive Hysteresis Timer Adjustments for Clock Gating 审中-公开
标题翻译：用于时钟门控的自适应滞后定时器调整方法和装置
公开(公告)号：US20130064337A1
公开(公告)日：2013-03-14
申请号：US13229943
申请日：2011-09-12
申请人： Richard Gerard Hofmann , Jaya Prakash Subramaniam Ganasan
发明人： Richard Gerard Hofmann , Jaya Prakash Subramaniam Ganasan
IPC分类号： H04L7/00
CPC分类号： G06F1/08 , G06F1/3237 , G06F1/3253 , Y02D10/128 , Y02D10/151
摘要： Apparatus and method for adaptive hysteresis timer adjustments for clock gating are disclosed. An apparatus comprises a transaction circuit configured to perform transactions. The apparatus further comprises a hysteresis timer having a hysteresis value and configured to start counting based on the hysteresis value when a transaction in the transaction circuit has been completed. The apparatus further comprises a hysteresis timer update circuit configured to monitor the hysteresis timer and the transaction circuit, store an adjustment state based on whether a new transaction is received before, coincident with or after the count of the hysteresis timer expires and adjust the hysteresis value based on the adjustment state.
摘要翻译：公开了用于时钟门控的自适应滞后定时器调整的装置和方法。一种装置包括被配置为执行交易的交易电路。该装置还包括具有迟滞值的滞后定时器，并且被配置为当交易电路中的交易已经完成时基于迟滞值开始计数。该装置还包括滞后定时器更新电路，其被配置为监视滞后定时器和事务电路，基于在迟滞计时器的计数到期之前是否接收到新的事务，并且调整滞后值来调整调整状态基于调整状态。

28. 发明授权

US08244947B2 Methods and apparatus for resource sharing in a programmable interrupt controller 失效
标题翻译：可编程中断控制器资源共享的方法和装置
公开(公告)号：US08244947B2
公开(公告)日：2012-08-14
申请号：US12389413
申请日：2009-02-20
申请人： Martyn Ryan Shirlen , Richard Gerard Hofmann , Michael Egnoah Birenbach
发明人： Martyn Ryan Shirlen , Richard Gerard Hofmann , Michael Egnoah Birenbach
IPC分类号： G06F13/26
CPC分类号： G06F13/26 , Y02D10/14
摘要： Efficient techniques are described for identifying active interrupt requests to improve performance and reduce power requirements in a processor system. A method to identify active sampled interrupt requests begins with scanning groups of the sampled interrupt requests one group at a time to identify an active interrupt request in any scanned group. A group of interrupt requests is an M/R priority of N sampled interrupt requests, M is the number of priority levels, and R is a resource sharing factor. A group selection circuit is updated to a new group in response to having identified an active interrupt request to improve the latency in processing high priority interrupt requests. Also, groups having active interrupt requests may be identified by early detection or look ahead circuitry. The scanning of groups of interrupt requests may be stopped until the next interrupt request sample point has been reached to reduce power utilization.
摘要翻译：描述了用于识别活动中断请求以提高性能并降低处理器系统中的功率需求的高效技术。识别有源采样中断请求的方法首先从一组扫描一组采样中断请求，以识别任何扫描组中的活动中断请求。一组中断请求是N个采样中断请求的M / R优先级，M是优先级数，R是资源共享因子。响应于已经识别出用于改善处理高优先级中断请求的等待时间的活动中断请求，组群选择电路被更新为新组。此外，具有活动中断请求的组可以通过早期检测或预期电路来识别。中断请求组的扫描可能会停止，直到达到下一个中断请求采样点以降低功耗。

29. 发明申请

US20120089789A1 Memory Controllers, Systems and Methods for Applying Page Management Policies Based on Stream Transaction Information 有权
标题翻译：基于流交易信息应用页面管理策略的内存控制器，系统和方法
公开(公告)号：US20120089789A1
公开(公告)日：2012-04-12
申请号：US12900857
申请日：2010-10-08
申请人： Martyn Ryan Shirlen , Richard Gerard Hofmann , Mark Michael Schaffer
发明人： Martyn Ryan Shirlen , Richard Gerard Hofmann , Mark Michael Schaffer
IPC分类号： G06F12/00
CPC分类号： G06F13/1689 , G06F12/0215
摘要： Memory controllers, systems, methods, and computer-readable mediums for applying a page management policy(ies) based on stream transaction information are disclosed. In one embodiment, a memory controller is provided and configured to receive memory access requests for stream transactions. The memory controller is configured to perform a memory access to a memory page(s) in memory included in the stream transaction. The controller is further configured to apply a page management policy(ies) to the memory page(s) in memory based on information related to the stream transactions. In this manner, the page management policy(ies) can be configured to utilize page open policies for efficiency that stream transactions may facilitate, but while also recognizing and taking into consideration in the page management policy latency issues that can arise when the memory controller is handling memory access requests from different devices.
摘要翻译：公开了用于基于流交易信息应用页面管理策略的内存控制器，系统，方法和计算机可读介质。在一个实施例中，存储器控制器被提供并被配置为接收流事务的存储器访问请求。存储器控制器被配置为对包含在流事务中的存储器中的存储器页执行存储器访问。控制器还被配置为基于与流事务相关的信息将页面管理策略应用于存储器中的存储器页面。以这种方式，页面管理策略可以被配置为利用页面打开的策略来实现流交易可以促进的效率，但是在存储器控制器是可能出现的页面管理策略延迟问题的同时还识别和考虑处理来自不同设备的存储器访问请求。

30. 发明申请

US20120089759A1 Arbitrating Stream Transactions Based on Information Related to the Stream Transaction(s) 审中-公开
标题翻译：基于与流事务相关的信息仲裁流事务
公开(公告)号：US20120089759A1
公开(公告)日：2012-04-12
申请号：US12900800
申请日：2010-10-08
申请人： Martyn Ryan Shirlen , Richard Gerard Hofmann , Mark Michael Schaffer
发明人： Martyn Ryan Shirlen , Richard Gerard Hofmann , Mark Michael Schaffer
IPC分类号： G06F13/362
CPC分类号： G06F13/362
摘要： Devices, systems, methods, and computer-readable mediums for arbitrating stream transactions based on information related to the stream transactions are disclosed. A stream transaction is a superset of burst access types to facilitate efficient bulk transfers of data. In one embodiment, an arbiter is provided that arbitrates bus transactions between a plurality of devices coupled to a bus competing for resources accessible through the bus. To efficiently arbitrate stream transactions requested on the bus, the arbiter is configured to use information related to the stream transactions to provide a view of future bus traffic on the bus. The arbiter is configured to use this stream transaction information to apply bus arbitration policies for arbitrating stream transactions. In this example, the bus arbitration policy can be adjusted for stream transactions based on the stream transaction information, if necessary, for the arbiter to attempt to meet a parameter(s) for completing the stream transactions.
摘要翻译：公开了用于基于与流事务相关的信息来仲裁流事务的设备，系统，方法和计算机可读介质。流事务是突发访问类型的超集，以便于数据的高效批量传输。在一个实施例中，提供仲裁器，其仲裁耦合到总线的多个设备之间的总线事务，该总线竞争通过总线可访问的资源。为了有效地仲裁在总线上请求的流事务，仲裁器被配置为使用与流事务相关的信息来提供总线上未来总线流量的视图。仲裁器被配置为使用该流事务信息来应用用于仲裁流事务的总线仲裁策略。在该示例中，如果需要，可以基于流交易信息来调整总线仲裁策略，以便仲裁者尝试满足用于完成流事务的参数。

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