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1. 发明授权

US08725488B2 Method and apparatus for adaptive voltage scaling based on instruction usage 失效
标题翻译：基于指令使用的自适应电压缩放的方法和装置
公开(公告)号：US08725488B2
公开(公告)日：2014-05-13
申请号：US11828782
申请日：2007-07-26
申请人： Richard Gerard Hofmann , Jeffrey Todd Bridges
发明人： Richard Gerard Hofmann , Jeffrey Todd Bridges
IPC分类号： G06F9/455 , G06F1/26 , G06F1/32
CPC分类号： G06F1/324 , G06F1/3203 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： Different software applications may use a set of instructions having critical timing paths less than a worst case critical timing path of a processor complex. For such applications, a supply voltage may be reduced while still maintaining the clock frequency necessary to meet the application's performance requirements. In order to reduce the supply voltage, an adaptive voltage scaling method is used. A critical path is selected from a plurality of critical paths for analysis on emulation logic to determine an attribute of the selected critical path during on chip functional operations. The selected critical path is representative of the worst case critical path to be in operation during a program execution. During on-chip functional operations, a voltage is controlled in response to the attribute, wherein the voltage supplies power to a power domain associated with the plurality of critical paths. The reduction in voltage reduces power drain based on instruction set usage allowing battery life to be extended.
摘要翻译：不同的软件应用可以使用具有小于处理器复合体的最坏情况关键定时路径的关键定时路径的指令集。对于这样的应用，可以降低电源电压，同时仍然保持满足应用的性能要求所需的时钟频率。为了降低电源电压，使用自适应电压缩放方法。从多个关键路径中选择关键路径用于分析仿真逻辑以在片上功能操作期间确定所选择的关键路径的属性。所选择的关键路径代表在程序执行期间正在运行的最坏情况的关键路径。在片上功能操作期间，响应于属性来控制电压，其中电压向与多个关键路径相关联的电力域提供电力。降低电压可以根据指令集的使用量减少功耗，从而延长电池寿命。

2. 发明授权

US08521914B2 Auxiliary writes over address channel 有权
标题翻译：辅助写入地址通道
公开(公告)号：US08521914B2
公开(公告)日：2013-08-27
申请号：US13337801
申请日：2011-12-27
申请人： Richard Gerard Hofmann , Terence J. Lohman
发明人： Richard Gerard Hofmann , Terence J. Lohman
IPC分类号： G06F3/00
CPC分类号： G06F13/4282 , G06F13/4265
摘要： A method for communicating via a bus including a first channel, a second channel, and a third channel is disclosed. The method includes addressing a slave device via the first channel, receiving from the slave device via the second channel, and writing to the slave device via the third channel. The method further includes selecting between first and second bus transmission modes. In the first bus transmission mode, payload write data is to be sent to the slave device via the first channel or the third channel. In the second bus transmission mode, during a first clock cycle, second payload write data associated with a second write operation is to be sent to the slave device via the first channel and first payload write data associated with a first write operation is to be concurrently sent to the slave device via the third channel.
摘要翻译：公开了一种经由包括第一通道，第二通道和第三通道的总线进行通信的方法。该方法包括经由第一通道寻址从设备，经由第二通道从从设备接收，以及经由第三通道向从设备写入。该方法还包括在第一和第二总线传输模式之间进行选择。在第一总线传输模式中，有效负载写入数据将经由第一通道或第三通道发送到从设备。在第二总线传输模式中，在第一时钟周期期间，与第二写入操作相关联的第二有效负载写入数据将经由第一通道发送到从设备，并且与第一写入操作相关联的第一有效载荷写入数据将同时通过第三个通道发送到从设备。

3. 发明申请

US20120096202A1 AUXILIARY WRITES OVER ADDRESS CHANNEL 有权
标题翻译：地址通道辅助写
公开(公告)号：US20120096202A1
公开(公告)日：2012-04-19
申请号：US13337801
申请日：2011-12-27
申请人： Richard Gerard Hofmann , Terence J. Lohman
发明人： Richard Gerard Hofmann , Terence J. Lohman
IPC分类号： G06F13/38
CPC分类号： G06F13/4282 , G06F13/4265
摘要： A method for communicating via a bus including a first channel, a second channel, and a third channel is disclosed. The method includes addressing a slave device via the first channel, receiving from the slave device via the second channel, and writing to the slave device via the third channel. The method further includes selecting between first and second bus transmission modes. In the first bus transmission mode, payload write data is to be sent to the slave device via the first channel or the third channel. In the second bus transmission mode, during a first clock cycle, second payload write data associated with a second write operation is to be sent to the slave device via the first channel and first payload write data associated with a first write operation is to be concurrently sent to the slave device via the third channel.
摘要翻译：公开了一种经由包括第一通道，第二通道和第三通道的总线进行通信的方法。该方法包括经由第一通道寻址从设备，经由第二通道从从设备接收，以及经由第三通道向从设备写入。该方法还包括在第一和第二总线传输模式之间进行选择。在第一总线传输模式中，有效负载写入数据将经由第一通道或第三通道发送到从设备。在第二总线传输模式中，在第一时钟周期期间，与第二写入操作相关联的第二有效负载写入数据将经由第一通道发送到从设备，并且与第一写入操作相关联的第一有效载荷写入数据将同时通过第三个通道发送到从设备。

4. 发明授权

US08108838B2 System and method for adaptive run-time reconfiguration for a reconfigurable instruction set co-processor architecture 失效
标题翻译：用于可重构指令集协处理器架构的自适应运行时重新配置的系统和方法
公开(公告)号：US08108838B2
公开(公告)日：2012-01-31
申请号：US12121542
申请日：2008-05-15
申请人： Sameh W. Asaad , Richard Gerard Hofmann
发明人： Sameh W. Asaad , Richard Gerard Hofmann
IPC分类号： G06F9/44 , G06F9/445 , G06F15/00 , G06F3/00
CPC分类号： G06F9/3885 , G06F8/443 , G06F9/30181 , G06F9/3897
摘要： A method for adaptive runtime reconfiguration of a co-processor instruction set, in a computer system with at least a main processor communicatively connected to at least one reconfigurable co-processor, includes the steps of configuring the co-processor to implement an instruction set comprising one or more co-processor instructions, issuing a co-processor instruction to the co-processor, and determining whether the instruction is implemented in the co-processor. For an instruction not implemented in the co-processor instruction set, raising a stall signal to delay the main processor, determining whether there is enough space in the co-processor for the non-implemented instruction, and if there is enough space for said instruction, reconfiguring the instruction set of the co-processor by adding the non-implemented instruction to the co-processor instruction set. The stall signal is cleared and the instruction is executed.
摘要翻译：一种在具有通信地连接到至少一个可重配置协处理器的至少一个主处理器的计算机系统中的协处理器指令集的自适应运行时重新配置的方法包括以下步骤：配置协处理器以实现包括一个或多个协处理器指令，向协处理器发出协处理器指令，以及确定在协处理器中是否实现指令。对于未在协处理器指令集中实现的指令，提高失速信号以延迟主处理器，确定协处理器中对于未实现指令是否有足够的空间，以及如果存在足够的空间用于所述指令通过将未实现的指令添加到协处理器指令集来重新配置协处理器的指令集。停止信号被清除，指令被执行。

5. 发明授权

US07984202B2 Device directed memory barriers 有权
标题翻译：设备定向记忆障碍
公开(公告)号：US07984202B2
公开(公告)日：2011-07-19
申请号：US11756643
申请日：2007-06-01
申请人： Richard Gerard Hofmann , Jaya Prakash Ganasan , Barry Joe Wolford
发明人： Richard Gerard Hofmann , Jaya Prakash Ganasan , Barry Joe Wolford
IPC分类号： G06F13/28 , G06F13/48 , G06F13/00
CPC分类号： G06F13/1621 , G06F13/4234 , Y02D10/14 , Y02D10/151
摘要： Efficient techniques for controlling synchronization of bus transactions to improve performance and reduce power requirements in a shared memory system are described. Interconnect arrangements in complex processing systems are also described that provide efficient data transfers between bus masters and shared memory devices to improve performance and reduce power use. In one example, a method for controlling synchronization of bus transactions to remote devices is addressed. A device directed memory barrier command is received. The device directed memory barrier command is decoded to determine one or more destination devices. A memory barrier command is selectively routed to the one or more destination devices in response to the decoding. The described techniques combine high speed device directed memory barrier capability, improved bus bandwidth functionality, and power saving features.
摘要翻译：描述了用于控制总线事务的同步以提高性能并降低共享存储器系统中的功率需求的高效技术。还描述了在复杂处理系统中的互连布置，其提供总线主机和共享存储器件之间的有效数据传输，以提高性能并减少功率使用。在一个示例中，解决了用于控制总线事务到远程设备的同步的方法。接收设备定向存储器障碍命令。解码器件定向存储器障碍命令以确定一个或多个目的地设备。响应于解码，存储器屏障命令被选择性地路由到一个或多个目的地设备。所描述的技术结合了高速设备定向存储器屏障能力，改进的总线带宽功能和省电功能。

6. 发明授权

US07921249B2 Weakly ordered processing systems and methods 有权
标题翻译：处理系统和方法薄弱
公开(公告)号：US07921249B2
公开(公告)日：2011-04-05
申请号：US12561381
申请日：2009-09-17
申请人： James Edward Sullivan, Jr. , Jaya Prakash Subramaniam Ganasan , Richard Gerard Hofmann
发明人： James Edward Sullivan, Jr. , Jaya Prakash Subramaniam Ganasan , Richard Gerard Hofmann
IPC分类号： G06F13/00
CPC分类号： G06F13/1621 , G06F9/52 , G06F9/522
摘要： The disclosure is directed to a weakly-ordered processing system and method of executing memory barriers in weakly-ordered processing system. The processing system includes memory and a master device configured to issue memory access requests, including memory barriers, to the memory. The processing system also includes a slave device configured to provide the master device access to the memory, the slave device being further configured to produce a signal indicating that an ordering constraint imposed by a memory barrier issued by the master device will be enforced, the signal being produced before the execution of all memory access requests issued by the master device to the memory before the memory barrier.
摘要翻译：本公开涉及一种弱有序处理系统和在弱有序处理系统中执行存储障碍的方法。处理系统包括存储器和被配置为向存储器发出存储器访问请求（包括存储器障碍）的主设备。处理系统还包括被配置为提供主设备对存储器的访问的从设备，从设备还被配置为产生指示由主设备发布的存储器障碍施加的排序约束将被强制的信号，信号在执行由主设备发出的所有存储器访问请求之前在存储器屏障之前被产生到存储器。

7. 发明授权

US07917676B2 Efficient execution of memory barrier bus commands with order constrained memory accesses 有权
标题翻译：具有订单约束的存储器访问的存储器障碍总线命令的高效执行
公开(公告)号：US07917676B2
公开(公告)日：2011-03-29
申请号：US11397287
申请日：2006-04-04
申请人： James Edward Sullivan, Jr. , Jaya Prakash Subramaniam Ganasan , Richard Gerard Hofmann
发明人： James Edward Sullivan, Jr. , Jaya Prakash Subramaniam Ganasan , Richard Gerard Hofmann
IPC分类号： G06F13/00
CPC分类号： G06F13/1621 , G06F9/52 , G06F9/522
摘要： The disclosure is directed to a weakly-ordered processing system and method of executing memory barriers in weakly-ordered processing system. The processing system includes memory and a master device configured to issue memory access requests, including memory barriers, to the memory. The processing system also includes a slave device configured to provide the master device access to the memory, the slave device being further configured to produce a signal indicating that an ordering constraint imposed by a memory barrier issued by the master device will be enforced, the signal being produced before the execution of all memory access requests issued by the master device to the memory before the memory barrier.
摘要翻译：本公开涉及一种弱有序处理系统和在弱有序处理系统中执行存储障碍的方法。处理系统包括存储器和被配置为向存储器发出存储器访问请求（包括存储器障碍）的主设备。处理系统还包括被配置为提供主设备对存储器的访问的从设备，从设备还被配置为产生指示由主设备发布的存储器障碍施加的排序约束将被强制的信号，信号在执行由主设备发出的所有存储器访问请求之前在存储器屏障之前被产生到存储器。

8. 发明授权

US07913021B2 Scalable bus structure 有权
标题翻译：可扩展总线结构
公开(公告)号：US07913021B2
公开(公告)日：2011-03-22
申请号：US11565041
申请日：2006-11-30
申请人： Richard Gerard Hofmann , Mark Michael Schaffer
发明人： Richard Gerard Hofmann , Mark Michael Schaffer
IPC分类号： G06F13/14 , G06F13/00 , G06F13/28
CPC分类号： G06F13/4265
摘要： A processing system is disclosed with a sending component and a receiving component connected by a bus. The bus may be configured with first and second channels. The sending component may be configured to broadcast on the first channel read and write address information, read and write control signals, and write data. The sending component may also be configured to signal the receiving component such that the receiving component can distinguish between the read and write address information, the read and write control signals, and the write data broadcast on the first channel. The receiving component may be configured to store the write data broadcast on the first channel based on the write address information and the write control signals, retrieve read data based on the read address information and the read control signals, and broadcast the retrieved read data on the second channel.
摘要翻译：公开了一种具有通过总线连接的发送部件和接收部件的处理系统。总线可以配置有第一和第二通道。发送组件可以被配置为在第一通道上广播读取和写入地址信息，读取和写入控制信号以及写入数据。发送组件还可以被配置为向接收组件发信号，使得接收组件可以区分读取和写入地址信息，读取和写入控制信号以及在第一通道上广播的写入数据。接收部件可以被配置为基于写入地址信息和写入控制信号在第一信道上存储写入数据，基于读取的地址信息和读取的控制信号来检索读取的数据，并将检索到的读取数据广播到第二个渠道。

9. 发明申请

US20090228981A1 Method For Securely Communicating Information About The Location Of A Compromised Computing Device 有权
标题翻译：用于安全地沟通关于被破坏的计算设备的位置的信息的方法
公开(公告)号：US20090228981A1
公开(公告)日：2009-09-10
申请号：US12208626
申请日：2008-09-11
申请人： Martyn Ryan Shirlen , Richard Gerard Hofmann
发明人： Martyn Ryan Shirlen , Richard Gerard Hofmann
IPC分类号： G06F21/00
CPC分类号： H04L63/1441 , G06F21/55 , G06F21/554 , G06F21/73 , G06F21/88
摘要： A method for securely reporting location information after an attack on a computing device is presented. Such information may be reported to a requesting entity in a manner almost transparent to an attacker. Several exemplary embodiments of systems wherein the method may be used are presented.
摘要翻译：提出了在对计算设备的攻击之后安全地报告位置信息的方法。这样的信息可以以对攻击者几乎透明的方式报告给请求实体。呈现了可以使用该方法的系统的几个示例性实施例。

10. 发明申请

US20090089515A1 Memory Controller for Performing Memory Block Initialization and Copy 审中-公开
标题翻译：用于执行存储器块初始化和复制的存储器控制器
公开(公告)号：US20090089515A1
公开(公告)日：2009-04-02
申请号：US11865970
申请日：2007-10-02
申请人： Gerald Paul Michalak , Richard Gerard Hofmann , Perry Willmann Remaklus, JR.
发明人： Gerald Paul Michalak , Richard Gerard Hofmann , Perry Willmann Remaklus, JR.
IPC分类号： G06F12/00
CPC分类号： G06F13/1668
摘要： A memory controller and methods for performing memory block initialization and copy functions with reduced bus traffic are disclosed. The memory controller can perform the memory initialization by receiving a start address of a memory, an end address of the memory and a fill value. The fill value is then written from the memory controller to the memory in a fill range of arbitrary length defined by the start address and end address.
摘要翻译：公开了一种用于执行具有减少的总线流量的存储器块初始化和复制功能的存储器控制器和方法。存储器控制器可以通过接收存储器的起始地址，存储器的结束地址和填充值来执行存储器初始化。然后将填充值从存储器控制器写入到由起始地址和结束地址定义的任意长度的填充范围内的存储器中。

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