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1. 发明授权

US07984202B2 Device directed memory barriers 有权
标题翻译：设备定向记忆障碍
公开(公告)号：US07984202B2
公开(公告)日：2011-07-19
申请号：US11756643
申请日：2007-06-01
申请人： Richard Gerard Hofmann , Jaya Prakash Ganasan , Barry Joe Wolford
发明人： Richard Gerard Hofmann , Jaya Prakash Ganasan , Barry Joe Wolford
IPC分类号： G06F13/28 , G06F13/48 , G06F13/00
CPC分类号： G06F13/1621 , G06F13/4234 , Y02D10/14 , Y02D10/151
摘要： Efficient techniques for controlling synchronization of bus transactions to improve performance and reduce power requirements in a shared memory system are described. Interconnect arrangements in complex processing systems are also described that provide efficient data transfers between bus masters and shared memory devices to improve performance and reduce power use. In one example, a method for controlling synchronization of bus transactions to remote devices is addressed. A device directed memory barrier command is received. The device directed memory barrier command is decoded to determine one or more destination devices. A memory barrier command is selectively routed to the one or more destination devices in response to the decoding. The described techniques combine high speed device directed memory barrier capability, improved bus bandwidth functionality, and power saving features.
摘要翻译：描述了用于控制总线事务的同步以提高性能并降低共享存储器系统中的功率需求的高效技术。还描述了在复杂处理系统中的互连布置，其提供总线主机和共享存储器件之间的有效数据传输，以提高性能并减少功率使用。在一个示例中，解决了用于控制总线事务到远程设备的同步的方法。接收设备定向存储器障碍命令。解码器件定向存储器障碍命令以确定一个或多个目的地设备。响应于解码，存储器屏障命令被选择性地路由到一个或多个目的地设备。所描述的技术结合了高速设备定向存储器屏障能力，改进的总线带宽功能和省电功能。

2. 发明申请

US20080301342A1 Device Directed Memory Barriers 有权
标题翻译：设备定向内存障碍
公开(公告)号：US20080301342A1
公开(公告)日：2008-12-04
申请号：US11756643
申请日：2007-06-01
申请人： Richard Gerard Hofmann , Jaya Prakash Ganasan , Barry Joe Wolford
发明人： Richard Gerard Hofmann , Jaya Prakash Ganasan , Barry Joe Wolford
IPC分类号： G06F13/42 , G06F13/00
CPC分类号： G06F13/1621 , G06F13/4234 , Y02D10/14 , Y02D10/151
摘要： Efficient techniques for controlling synchronization of bus transactions to improve performance and reduce power requirements in a shared memory system are described. Interconnect arrangements in complex processing systems are also described that provide efficient data transfers between bus masters and shared memory devices to improve performance and reduce power use. In one example, a method for controlling synchronization of bus transactions to remote devices is addressed. A device directed memory barrier command is received. The device directed memory barrier command is decoded to determine one or more destination devices. A memory barrier command is selectively routed to the one or more destination devices in response to the decoding. The described techniques combine high speed device directed memory barrier capability, improved bus bandwidth functionality, and power saving features.
摘要翻译：描述了用于控制总线事务的同步以提高性能并降低共享存储器系统中的功率需求的高效技术。还描述了在复杂处理系统中的互连布置，其提供总线主机和共享存储器件之间的有效数据传输，以提高性能并减少功率使用。在一个示例中，解决了用于控制总线事务到远程设备的同步的方法。接收设备定向存储器障碍命令。解码器件定向存储器障碍命令以确定一个或多个目的地设备。响应于解码，存储器屏障命令被选择性地路由到一个或多个目的地设备。所描述的技术结合了高速设备定向存储器屏障能力，改进的总线带宽功能和省电功能。

3. 发明授权

US07127562B2 Ensuring orderly forward progress in granting snoop castout requests 失效
标题翻译：确保在发出侦听请求时有序地推进进度
公开(公告)号：US07127562B2
公开(公告)日：2006-10-24
申请号：US10458998
申请日：2003-06-11
申请人： James Norris Dieffenderfer , Bernard Charles Drerup , Jaya Prakash Ganasan , Richard Gerard Hofmann , Thomas Andrew Sartorius , Thomas Philip Speier , Barry Joe Wolford
发明人： James Norris Dieffenderfer , Bernard Charles Drerup , Jaya Prakash Ganasan , Richard Gerard Hofmann , Thomas Andrew Sartorius , Thomas Philip Speier , Barry Joe Wolford
IPC分类号： G06F12/00
CPC分类号： G06F12/0831
摘要： A method and system for ensuring orderly forward progress in granting snoop castout requests. Masters may include a tag (“request tag”) in their transfer requests to a bus macro. The request tag indicates the order of the request issued by the master. If the bus macro determines that the transfer request is snoopable, then the bus macro broadcasts a snoop request that includes the request tag. If a snoop controller determines that the address in the snoop request is a hit to a modified coherency granule in an associated cache, then the master associated with that snoop controller transmits a castout request to the bus macro that includes the request tag associated with the snoop request. The bus macro uses the request tag to determine whether the castout request is a response to the oldest in a series of pipelined snoop requests to be serviced.
摘要翻译：一种方法和系统，用于确保在发出侦听请求时有序地前进进度。主机可以在其传送请求中包括一个标签（“请求标签”）到总线宏。请求标签指示主机发出的请求的顺序。如果总线宏确定传输请求是可窥探的，则总线宏广播包含请求标签的窥探请求。如果窥探控制器确定窥探请求中的地址是对相关高速缓存中修改的相关性粒度的命中，则与该监听控制器相关联的主机向总线宏发送包含与窥探相关联的请求标签的总线宏的抛出请求请求。总线宏使用请求标签来确定castout请求是否是对一系列待管理的流水线侦听请求中的最早的响应。

4. 发明授权

US06973520B2 System and method for providing improved bus utilization via target directed completion 失效
标题翻译：通过目标定向完成提供改进的总线利用率的系统和方法
公开(公告)号：US06973520B2
公开(公告)日：2005-12-06
申请号：US10195172
申请日：2002-07-11
申请人： Bernard Charles Drerup , Jaya Prakash Subramaniam Ganasan , Richard Gerard Hofmann , Richard Nicholas Iachetta, Jr. , Barry Joe Wolford
发明人： Bernard Charles Drerup , Jaya Prakash Subramaniam Ganasan , Richard Gerard Hofmann , Richard Nicholas Iachetta, Jr. , Barry Joe Wolford
IPC分类号： G06F13/00 , G06F13/14 , G06F13/364
CPC分类号： G06F13/364
摘要： An electronic system is disclosed, including multiple initiators and one or more targets coupled to a bus, and a request mask control unit (RMCU). The initiators are configured to initiate requests (e.g., read requests and write requests) via the bus, and the targets are configured to receive requests from the initiators via the bus. The targets are also configured to produce multiple MaskEnable signals, wherein each of the MaskEnable signals is generated following an initial request received via the bus, and dependent on a corresponding “masking situation” within the target. The RMCU receives the MaskEnable signals and produces multiple RequestMask signals dependent upon the MaskEnable signals. One or more of the initiators are permitted to repeat requests via the bus dependent upon one or more of the RequestMask signals. This mechanism provides additional bus bandwidth for carrying out successful data transfers.
摘要翻译：公开了一种电子系统，包括多个启动器和耦合到总线的一个或多个目标，以及请求掩码控制单元（RMCU）。启动器被配置为经由总线发起请求（例如，读请求和写请求），并且目标被配置为经由总线接收来自发起者的请求。目标还被配置为产生多个MaskEnable信号，其中每个MaskEnable信号是在经由总线接收到的初始请求之后生成的，并且取决于目标内相应的“屏蔽情况”。 RMCU接收MaskEnable信号，并根据MaskEnable信号产生多个RequestMask信号。一个或多个启动器被允许经由总线重复请求，取决于一个或多个请求掩码信号。该机制为进行成功的数据传输提供了额外的总线带宽。

5. 发明授权

US06834378B2 System on a chip bus with automatic pipeline stage insertion for timing closure 有权
标题翻译：系统具有自动流水线插入的片上总线，用于定时关闭
公开(公告)号：US06834378B2
公开(公告)日：2004-12-21
申请号：US10264162
申请日：2002-10-03
申请人： Victor Roberts Augsburg , James Norris Dieffenderfer , Bernard Charles Drerup , Richard Gerard Hofmann , Thomas Andrew Sartorius , Barry Joe Wolford
发明人： Victor Roberts Augsburg , James Norris Dieffenderfer , Bernard Charles Drerup , Richard Gerard Hofmann , Thomas Andrew Sartorius , Barry Joe Wolford
IPC分类号： G06F945
CPC分类号： G06F17/5045
摘要： A method of designing a system on a chip (SoC) to operate with varying latencies and frequencies. A layout of the chip is designed with specific placement of devices, including a bus controller, initiator, and target devices. The time for a signal to propagate from a source device to a destination device is determined relative to a default propagation time. A pipeline stage is then inserted into a bus path between said source device and destination device for each additional time the signal takes to propagate. Each device (i.e., initiators, targets, and bus controller) is designed with logic to control a protocol that functions with a variety of response latencies. With the additional logic, the devices do not need to be changed when pipeline stages are inserted in the various paths. Registers are utilized as the pipeline stages that are inserted within the paths.
摘要翻译：一种设计芯片上的系统（SoC）以在不同的延迟和频率下工作的方法。芯片的布局设计具有特定的器件布局，包括总线控制器，启动器和目标器件。相对于默认传播时间确定信号从源设备传播到目的地设备的时间。然后，在信号需要传播的每个附加时间，将流水线级插入到所述源设备和目的设备之间的总线路径中。每个设备（即，启动器，目标和总线控制器）被设计为具有控制以各种响应延迟起作用的协议的逻辑。使用附加逻辑，当管道级插入各种路径时，不需要更改设备。寄存器被用作插入到路径内的流水线级。

6. 发明授权

US06826656B2 Reducing power in a snooping cache based multiprocessor environment 失效
标题翻译：在基于多播处理器环境的基于高速缓存的基础上降低功耗
公开(公告)号：US06826656B2
公开(公告)日：2004-11-30
申请号：US10059537
申请日：2002-01-28
申请人： Victor Roberts Augsburg , James Norris Dieffenderfer , Bernard Charles Drerup , Richard Gerard Hofmann , Thomas Andrew Sartorius , Barry Joe Wolford
发明人： Victor Roberts Augsburg , James Norris Dieffenderfer , Bernard Charles Drerup , Richard Gerard Hofmann , Thomas Andrew Sartorius , Barry Joe Wolford
IPC分类号： G06F1208
CPC分类号： G06F1/3203 , G06F1/3275 , G06F12/0831 , Y02D10/14
摘要： A method and system for reducing power in a snooping cache based environment. A memory may be coupled to a plurality of processing units via a bus. Each processing unit may comprise a cache controller coupled to a cache associated with the processing unit. The cache controller may comprise a segment register comprising N bits where each bit in the segment register may be associated with a segment of memory divided into N segments. The cache controller may be configured to snoop a requested address on the bus. Upon determining which bit in the segment register is associated with the snooped requested address, the segment register may determine if the bit associated with the snooped requested address is set. If the bit is not set, then a cache search may not be performed thereby mitigating the power consumption associated with a snooped request cache search.
摘要翻译：一种用于在基于窥探缓存的环境中降低功耗的方法和系统。存储器可以经由总线耦合到多个处理单元。每个处理单元可以包括耦合到与处理单元相关联的高速缓存器的高速缓存控制器。高速缓存控制器可以包括包括N个比特的分段寄存器，其中分段寄存器中的每个比特可以与划分成N个分段的一段存储器相关联。高速缓存控制器可以被配置为窥探总线上的所请求的地址。一旦确定段寄存器中的哪个位与被窥探的请求地址相关联，则段寄存器可以确定是否设置与被窥探的请求地址相关联的位。如果该位未设置，则可能不执行高速缓存搜索，从而减轻与窥探请求高速缓存搜索相关联的功耗。

7. 发明申请

US20070176742A1 Method of Associating Groups of Classified Source Addresses with Vibration Patterns 有权
标题翻译：将分类源地址组与振动模式相关联的方法
公开(公告)号：US20070176742A1
公开(公告)日：2007-08-02
申请号：US11553600
申请日：2006-10-27
申请人： Richard Gerard Hofmann , Gerald Paul Michalak , Barry Joe Wolford
发明人： Richard Gerard Hofmann , Gerald Paul Michalak , Barry Joe Wolford
IPC分类号： G08B5/22 , H04Q7/14
CPC分类号： H04M19/04 , H04M1/57 , H04M1/72547 , H04M19/044 , H04M19/047
摘要： In a meeting or group event, people having a portable device, such as a cell phone or pager, may wish to be discretely notified when an important message is received, an urgent call comes in from a selected person or a selected group of people, or to be alerted to an upcoming important event without any audible alert to disturb the meeting or group event. To convey such a notification, a tactile alert is provided by vibrating the portable device according to a unique vibration pattern associated with the received communication. When a communication is received, a group identification (ID) is assigned based on the communication being a member of a classified group of source addresses. The portable device associates the group ID with a unique vibration pattern. To provide the alert, the portable device is vibrated according to the unique vibration pattern.
摘要翻译：在会议或小组活动中，具有诸如蜂窝电话或寻呼机的便携式设备的人可能希望在收到重要消息时离散地通知来自所选择的人或所选人群的紧急呼叫，或者提醒未来的重要事件而没有任何可听见的警报来打扰会议或团体活动。为了传达这种通知，通过根据与接收的通信相关联的唯一振动模式振动便携式设备来提供触觉警报。当接收到通信时，基于作为分类的源地址组的成员的通信来分配组标识（ID）。便携式设备将组ID与唯一的振动模式相关联。为了提供警报，便携式设备根据独特的振动模式而振动。

8. 发明授权

US07035958B2 Re-ordering a first request within a FIFO request queue to a different queue position when the first request receives a retry response from the target 失效
标题翻译：当第一个请求从目标接收到重试响应时，将FIFO请求队列内的第一请求重新排序到不同的队列位置
公开(公告)号：US07035958B2
公开(公告)日：2006-04-25
申请号：US10264170
申请日：2002-10-03
申请人： Victor Roberts Augsburg , James Norris Dieffenderfer , Bernard Charles Drerup , Richard Gerard Hofmann , Thomas Andrew Sartorius , Barry Joe Wolford
发明人： Victor Roberts Augsburg , James Norris Dieffenderfer , Bernard Charles Drerup , Richard Gerard Hofmann , Thomas Andrew Sartorius , Barry Joe Wolford
IPC分类号： G06F13/36
CPC分类号： G06F13/362 , G06F13/4022 , G06F2213/0038
摘要： A method of operating a request FIFO of a system on a chip (SoC) in which a requests in a first position that has been granted and which subsequently receives a retry from the intended target is automatically re-ordered with respect to the other requests below it in the request FIFO. Each issued requests is tagged to either enable or disable a re-order feature. When a request that is tagged as re-order enabled is granted, the FIFO logic monitors the response provided for the request. If the response is a retry, the request is removed from the first position of the request FIFO and the next sequential request is moved into the first position. The removed requests may be re-ordered within the request FIFO or sent back to the initiator. In the former implementation, controller logic reorders the first request within the request FIFO. In the latter implementation, the controller logic of the bus controller messages the initiator when a request has been retried and subsequently removed from the first position of the request FIFO. The initiator then determines whether or not to re-issue the request.
摘要翻译：一种操作芯片上系统（SoC）的请求FIFO的方法，其中已经被许可的第一个位置的请求和随后从预期目标接收到重试的请求自动地按照下面的其他请求重新排序它在请求FIFO中。每个发出的请求被标记为启用或禁用重新排序功能。当被标记为启用重新排序的请求被授予时，FIFO逻辑监视为请求提供的响应。如果响应是重试，则请求从请求FIFO的第一位置移除，并且下一个顺序请求被移动到第一位置。删除的请求可以在请求FIFO内重新排序或发送回发起者。在前面的实现中，控制器逻辑重新排序请求FIFO中的第一个请求。在后一实现中，总线控制器的控制器逻辑在请求已被重试并随后从请求FIFO的第一位置移除时消息发起者。然后，启动器确定是否重新发出请求。

9. 发明授权

US06907502B2 Method for moving snoop pushes to the front of a request queue 失效
标题翻译：将snoop移动到请求队列前端的方法
公开(公告)号：US06907502B2
公开(公告)日：2005-06-14
申请号：US10264169
申请日：2002-10-03
申请人： Victor Roberts Augsburg , James Norris Dieffenderfer , Bernard Charles Drerup , Jaya Prakash Subramaniam Ganasan , Richard Gerard Hofmann , Thomas Andrew Sartorius , Thomas Philip Speier , Barry Joe Wolford
发明人： Victor Roberts Augsburg , James Norris Dieffenderfer , Bernard Charles Drerup , Jaya Prakash Subramaniam Ganasan , Richard Gerard Hofmann , Thomas Andrew Sartorius , Thomas Philip Speier , Barry Joe Wolford
IPC分类号： G06F12/00 , G06F12/08
CPC分类号： G06F12/0831
摘要： A method for prioritizing snoop pushes in a data processing system that schedules requests within a request FIFO. Each new request that is received is placed in the last position of the request FIFO and the request FIFO typically grants request based solely on the order within the request FIFO. As prior requests are sequentially granted the subsequent requests move closer to a first position of the request FIFO. However, when a snoop push is received at the request FIFO, the snoop push is automatically inserted at the first position of the request FIFO ahead of all yet to be granted requests within the request FIFO.
摘要翻译：一种用于将窥探优先级的方法推送到在请求FIFO内调度请求的数据处理系统中。接收到的每个新请求被置于请求FIFO的最后位置，并且请求FIFO通常仅基于请求FIFO内的顺序授予请求。由于先前请求被顺序授权，所以随后的请求更接近请求FIFO的第一位置。然而，当在请求FIFO处接收到窥探推送时，窥探推送将自动插入请求FIFO的第一个位置，而在请求FIFO之前尚未被授予请求。

10. 发明授权

US06807608B2 Multiprocessor environment supporting variable-sized coherency transactions 失效
标题翻译：多处理器环境支持可变大小的一致性事务
公开(公告)号：US06807608B2
公开(公告)日：2004-10-19
申请号：US10077560
申请日：2002-02-15
申请人： Victor Roberts Augsburg , James Norris Dieffenderfer , Bernard Charles Drerup , Richard Gerard Hofmann , Thomas Andrew Sartorius , Barry Joe Wolford
发明人： Victor Roberts Augsburg , James Norris Dieffenderfer , Bernard Charles Drerup , Richard Gerard Hofmann , Thomas Andrew Sartorius , Barry Joe Wolford
IPC分类号： G06F1200
CPC分类号： G06F12/0831 , Y02D10/13
摘要： A method and system for performing variable-sized memory coherency transactions. A bus interface unit coupled between a slave and a master may be configured to receive a request (master request) comprising a plurality of coherency granules from the master. Each snooping unit in the system may be configured to snoop a different number of coherency granules in the master request at a time. Once the bus interface unit has received a collection of sets of indications from each snooping logic unit indicating that the associated collection of coherency granules in the master request have been snooped by each snooping unit and that the data at the addresses for the collection of coherency granules snooped has not been updated, the bus interface unit may allow the data at the addresses of those coherency granules not updated to be transferred between the requesting master and the slave.
摘要翻译：用于执行可变大小的存储器一致性事务的方法和系统。耦合在从机和主机之间的总线接口单元可以被配置为从主机接收包括多个相干性颗粒的请求（主请求）。系统中的每个窥探单元可以被配置为一次窥探主请求中的不同数量的一致性粒子。一旦总线接口单元已经从每个窥探逻辑单元接收到指示集合的指示集合，指示主请求中的相关性集合的集合已被每个监听单元窥探，并且用于收集相关性颗粒的地址上的数据被侦听未被更新，总线接口单元可以允许未更新的那些一致性粒度的地址上的数据在请求主机和从机之间传送。

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