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1. 发明授权

US06684277B2 Bus transaction verification method 失效
标题翻译：总线交易验证方法
公开(公告)号：US06684277B2
公开(公告)日：2004-01-27
申请号：US09770584
申请日：2001-01-26
申请人： Peter Dean LaFauci , Bryan Heath Stypmann , Paul David Bryan
发明人： Peter Dean LaFauci , Bryan Heath Stypmann , Paul David Bryan
IPC分类号： G06F1300
CPC分类号： G06F13/423
摘要： The present invention provides a method and computer readable medium with program instructions for automatically verifying bus transactions. The method includes: parsing a parameter code for the bus transactions, wherein the parameter code comprises a plurality of expected parameter values for the bus transactions; automatically integrating the parsed parameter code into a checking program; and automatically executing the checking program, wherein the checking program compares the plurality of expected parameter values with a plurality of actual parameter values for the bus transactions. The bus transaction verification method in accordance with the present invention automates the coding of expected parameter values for each test case into a checking program and automates the execution of the checking program, where the checking program compares the expected parameter values with the actual parameter values. By automating the bus transaction verification in this manner, the process is more efficient and reduces the chances of human error and inaccurate observation.
摘要翻译：本发明提供一种具有用于自动验证总线事务的程序指令的方法和计算机可读介质。该方法包括：解析总线事务的参数代码，其中参数代码包括用于总线事务的多个预期参数值; 自动将解析的参数代码集成到检查程序中; 并且自动执行所述检查程序，其中所述检查程序将所述多个预期参数值与所述总线事务的多个实际参数值进行比较。根据本发明的总线事务验证方法将每个测试用例的期望参数值的编码自动化到检查程序中，并自动执行检查程序，其中检查程序将预期参数值与实际参数值进行比较。通过以这种方式自动化总线事务验证，该过程更有效，并且减少人为错误和不准确的观察的机会。

2. 发明授权

US06513089B1 Dual burst latency timers for overlapped read and write data transfers 失效
标题翻译：用于重叠读和写数据传输的双突发等待时间计时器
公开(公告)号：US06513089B1
公开(公告)日：2003-01-28
申请号：US09574101
申请日：2000-05-18
申请人： Richard Gerard Hofmann , Peter Dean LaFauci , Dennis Charles Wilkerson
发明人： Richard Gerard Hofmann , Peter Dean LaFauci , Dennis Charles Wilkerson
IPC分类号： G06F100
CPC分类号： G06F13/28
摘要： The present invention discloses a method and system for managing independent read and write buses by dividing the pending read and write request signals and the read and write request priority level signals. The arbitration for use of the read and write buses are done independently for the read and write operations. A higher priority read, for example, can be concurrent with a corresponding lower priority write. Interruption of in process reads or writes is also done using the split arbitrations of the read and write buses leading the disruption of lower priority operations only if the conflicts are concurrent for the same read or write operation.
摘要翻译：本发明公开了一种通过划分未决读和写请求信号和读和写请求优先级信号来管理独立读和写总线的方法和系统。用于读写总线的仲裁是独立完成的，用于读写操作。例如，较高优先级读取可以与相应的较低优先级写入并发。只有在相同的读取或写入操作的冲突是并发的情况下，进程读取或写入的中断也是使用读取和写入总线的拆分仲裁来引导较低优先级操作的中断。

3. 发明授权

US06970816B1 Method and system for efficiently generating parameterized bus transactions 失效
标题翻译：有效产生参数化总线事务的方法和系统
公开(公告)号：US06970816B1
公开(公告)日：2005-11-29
申请号：US09638268
申请日：2000-08-14
申请人： Paul David Bryan , Richard Gerard Hofmann , Peter Dean LaFauci , William Robert Lee , Rhonda Gurganious Mitchell , Timothy Patrick Oke
发明人： Paul David Bryan , Richard Gerard Hofmann , Peter Dean LaFauci , William Robert Lee , Rhonda Gurganious Mitchell , Timothy Patrick Oke
IPC分类号： G06F17/50
CPC分类号： G06F17/5022
摘要： A method and system for efficiently generating parameterized bus transactions for verification of a design-under-test (DUT) comprises providing a configuration file for the DUT to a generator program. The configuration file defines possible parameter combinations for bus transactions executable by the DUT, and the generator program systematically enumerates all the possible combinations to produce a test case for verifying the DUT. Rules specified within the configuration file can include or exclude selected parameter combinations to tailor the test case to a specific DUT-to-bus interface.
摘要翻译：用于有效地产生用于验证被测设计（DUT）的参数化总线事务的方法和系统包括向发生器程序提供DUT的配置文件。配置文件定义可由DUT执行的总线事务的可能参数组合，并且生成器程序系统地枚举所有可能的组合以产生用于验证DUT的测试用例。在配置文件中指定的规则可以包括或排除选定的参数组合，以将测试用例定制到特定的DUT到总线接口。

4. 发明授权

US06718521B1 Method and system for measuring and reporting test coverage of logic designs 有权
标题翻译：测量和报告逻辑设计测试覆盖的方法和系统
公开(公告)号：US06718521B1
公开(公告)日：2004-04-06
申请号：US09638528
申请日：2000-08-14
申请人： David Gary Bentlage , Paul David Bryan , Peter Dean LaFauci , Randall Rogers Pratt
发明人： David Gary Bentlage , Paul David Bryan , Peter Dean LaFauci , Randall Rogers Pratt
IPC分类号： G06F1750
CPC分类号： G06F17/5022
摘要： A method and system for easily and automatically determining the extent of test coverage for a design-under-test (DUT). Incremental test coverage information is gathered from the application of test cases to the DUT, and cumulative test coverage information is maintained. The incremental test coverage and cumulative test coverage information are fed into a correlation process, which correlates valid bus transactions automatically generated from a configuration file describing the DUT with the incremental and cumulative test coverage information. The correlation process determines which valid bus transactions have or have not been applied in testing the DUT.
摘要翻译：一种用于轻松自动确定被测设计（DUT）测试覆盖范围的方法和系统。增量测试覆盖信息从应用测试用例收集到DUT，并保持累积测试覆盖信息。增量测试覆盖率和累积测试覆盖率信息被馈送到相关过程，其将从描述DUT的配置文件自动生成的有效总线事务与增量和累积测试覆盖信息相关联。相关过程确定哪些有效总线事务已经或未被应用于测试DUT。

5. 发明授权

US06772254B2 Multi-master computer system with overlapped read and write operations and scalable address pipelining 失效
标题翻译：具有重叠读写操作和可扩展地址流水线的多主计算机系统
公开(公告)号：US06772254B2
公开(公告)日：2004-08-03
申请号：US09855831
申请日：2001-05-15
申请人： Richard Gerard Hofmann , Jason Michael Hopp , Peter Dean LaFauci , Dennis Charles Wilkerson
发明人： Richard Gerard Hofmann , Jason Michael Hopp , Peter Dean LaFauci , Dennis Charles Wilkerson
IPC分类号： G06F1314
CPC分类号： G06F13/364
摘要： A multi-master computer system having overlapped read and write signal with scalable address pipelining programmable increases the depth of address pipelining independently on two overlapped read and write data busses up to “N” deep requests. The system includes a local bus having an address bus, a read bus, and a write bus. Master devices are coupled to separate address, read data and write data buses. Slave devices are attached to the data busses through shared, but decoupled address, read and write data buses. An arbiter is coupled to the data bus and allows masters to compete for bus ownership. The arbiter includes read and write pipeline logic for processing and priortizing master and slave read and write data transfers across the data bus. Programming apparatus alters the read and write pipeline logic for address pipelining
摘要翻译：具有重叠的读和写信号与可扩展地址流水线可编程的多主计算机系统在两个重叠的读和写数据总线上独立地增加地址流水线的深度，直到“N”个深度请求。该系统包括具有地址总线，读总线和写总线的本地总线。主器件耦合到单独的地址，读取数据和写入数据总线。从设备通过共享但解耦的地址，读写数据总线连接到数据总线。仲裁器耦合到数据总线，并允许主机竞争总线所有权。仲裁器包括读写流水线逻辑，用于处理和优化主数据和从属读写数据总线上的数据传输。编程设备改变了用于地址流水线化的读写流水线逻辑

6. 发明授权

US06507808B1 Hardware logic verification data transfer checking apparatus and method therefor 失效
标题翻译：硬件逻辑验证数据传输检查装置及其方法
公开(公告)号：US06507808B1
公开(公告)日：2003-01-14
申请号：US09338084
申请日：1999-06-23
申请人： Peter Dean LaFauci
发明人： Peter Dean LaFauci
IPC分类号： G06F1750
CPC分类号： G06F17/5022
摘要： An apparatus and method for hardware logic verification data transfer checking are implemented. Data for transfer is generated in response to a decoded bus transaction instruction using a pseudorandom number generator. The seed for the generator includes a predetermined portion provided to each bus device. The predetermined portion is combined with the address of the target device, obtained from the decoded instruction, to form the seed input to the random number generator. For write transactions, the bus master generates the data to be transferred using the seed, and sends the data to the target. The target independently generates the data by a call to the random number generator and compares the value received via the data transfer with the independently generated value. Similarly, for read transactions, the slave device generates the data to be transferred in response to the read request. The bus master initiating the read independently generates the data value by a call to the pseudorandom number generator, and effects the comparison between the received and independently generated values. If a miscompare occurs, for a bus transaction, a data transfer error has occurred, and is reported.
摘要翻译：实现了用于硬件逻辑验证数据传输检查的装置和方法。用于传送的数据是响应于使用伪随机数发生器的解码总线事务指令产生的。用于发电机的种子包括提供给每个总线装置的预定部分。预定部分与从解码指令获得的目标装置的地址组合，以形成对随机数发生器的种子输入。对于写事务，总线主机使用种子生成要传输的数据，并将数据发送到目标。目标通过对随机数发生器的呼叫独立地生成数据，并将经由数据传送接收的值与独立生成的值进行比较。类似地，对于读取事务，从设备响应于读取请求生成要传送的数据。启动读取的总线主机通过对伪随机数发生器的调用独立地生成数据值，并且实现接收到和独立生成的值之间的比较。如果发生错误比较，对于总线事务，发生了数据传输错误，并被报告。

7. 发明授权

US06829731B1 Method and system for generating a design-specific test case from a generalized set of bus transactions 失效
标题翻译：用于从一般化的总线事务集合生成设计特定测试用例的方法和系统
公开(公告)号：US06829731B1
公开(公告)日：2004-12-07
申请号：US09638757
申请日：2000-08-14
申请人： Peter Dean LaFauci , Rhonda Gurganious Mitchell , Jeffrey Richard Summers
发明人： Peter Dean LaFauci , Rhonda Gurganious Mitchell , Jeffrey Richard Summers
IPC分类号： G05F1100
CPC分类号： G06F11/3696 , G06F11/3684
摘要： A method and system for automating the creation of test cases for logic designs. A comprehensive set of bus transactions characterizing a bus architecture is provided to a test case designer in a user interface. The designer may enter inputs corresponding to a particular design-under-test (DUT) via the interface. The interface processes the inputs to automatically generate a configuration file corresponding to the particular DUT. The configuration file may be processed by a generator program to automatically generate a test case comprising one or more bus transactions customized to the particular DUT.
摘要翻译：一种用于自动创建逻辑设计测试用例的方法和系统。在用户界面中向测试用例设计者提供表征总线架构的综合总线事务。设计者可以通过接口输入与特定待测设计（DUT）相对应的输入。接口处理输入以自动生成与特定DUT相对应的配置文件。配置文件可以由生成器程序来处理，以自动生成包括针对特定DUT定制的一个或多个总线事务的测试用例。

8. 发明授权

US06587905B1 Dynamic data bus allocation 失效
标题翻译：动态数据总线分配
公开(公告)号：US06587905B1
公开(公告)日：2003-07-01
申请号：US09606463
申请日：2000-06-29
申请人： Anthony Correale, Jr. , Richard Gerard Hofmann , Peter Dean LaFauci , Dennis Charles Wilkerson
发明人： Anthony Correale, Jr. , Richard Gerard Hofmann , Peter Dean LaFauci , Dennis Charles Wilkerson
IPC分类号： G06F1300
CPC分类号： G06F13/364
摘要： A high performance integrated circuit (IC) with independent read and write data busses enables full simultaneous read and write data transfers between devices coupled to the buses. Multiple master and multiple slave devices communicate using the resources of a bus controller and a bus arbiter. Having separate read and write data busses with separate and independent arbitration allows reads and writes from different devices to occur simultaneously. Many high performance IC, like systems on a chip (SOC), have many different functional units communicating with a central processing unit (CPU). Many such CPUs have architectures that may cause in certain applications an unbalance between read and write traffic on the independent busses. Master and slave devices contain auxiliary internal read and write data buses multiplexed such that read or write data may be interchanged. A corresponding Auxiliary_(read or write) command is routed to the slave units to notify the units when to route normal read or write data to an idle bus. The bus controller may use this added feature to optimize the available bandwidth of independent read and write data busses up to the limit where a read or write bandwidth may be two times that available if the read and write data buses were used only for their normal traffic.
摘要翻译：具有独立读写数据总线的高性能集成电路（IC）使得能够在耦合到总线的器件之间实现全面同时的读和写数据传输。多个主设备和多个从设备使用总线控制器和总线仲裁器的资源进行通信。具有独立且独立仲裁的单独的读写数据总线允许来自不同设备的读取和写入同时发生。许多高性能IC，如片上系统（SOC），具有与中央处理单元（CPU）通信的许多不同功能单元。许多这样的CPU具有在某些应用中可能导致独立总线上的读取和写入流量之间的不平衡的架构。主设备和从设备包含辅助内部读和写数据总线进行复用，使得读或写数据可以互换。相应的辅助（读或写）命令被路由到从单元，以通知单元何时将正常读或写数据传送到空闲总线。总线控制器可以使用这个附加功能来优化独立的读和写数据总线的可用带宽，直到只有在读写数据总线仅用于其正常业务时，读或写带宽可能是可用的两倍。

9. 发明授权

US06430641B1 Methods, arbiters, and computer program products that can improve the performance of a pipelined dual bus data processing system 有权
标题翻译：可以提高流水线双总线数据处理系统性能的方法，仲裁器和计算机程序产品
公开(公告)号：US06430641B1
公开(公告)日：2002-08-06
申请号：US09304939
申请日：1999-05-04
申请人： Richard Gerard Hofmann , Peter Dean LaFauci , Dennis Charles Wilkerson
发明人： Richard Gerard Hofmann , Peter Dean LaFauci , Dennis Charles Wilkerson
IPC分类号： G06F1338
CPC分类号： G06F13/364
摘要： Methods, arbiters, and computer program products determine if a request for an idle bus in a dual bus data processing system is being blocked by one or more pending requests for the other bus. In this circumstance, any such pending request for the other bus is masked by the arbiter so that the request for the idle bus can be granted. Consequently, a more efficient utilization of the dual bus architecture is achieved. In an illustrative embodiment, a bus request is received for a first one of the dual busses. If the address and control busses are unavailable to allow the request to be granted, then an inquiry is made regarding the status of a pending request for the second one of the dual busses that has gained control of the address and control busses. In particular, it is determined whether a primary request has been granted and a secondary request has been pipelined for the second one of the dual busses. If a primary request has been granted and a secondary request has been pipelined, then the priority of the pending requests for the second one of the dual busses are examined. If the priority of the pending requests for the second one of the dual busses are at least as high as the currently pending request for the first one of the dual busses, then these requests are masked so that they no longer appears to be pending, which allows the request for the first one of the dual busses to be granted.
摘要翻译：方法，仲裁器和计算机程序产品确定对双总线数据处理系统中的空闲总线的请求是否被另一总线的一个或多个未决请求阻止。在这种情况下，任何这样的对另一总线的等待请求被仲裁器屏蔽，以便可以授予空闲总线的请求。因此，实现了双总线架构的更有效的利用。在说明性实施例中，为双总线中的第一个接收总线请求。如果地址和控制总线不可用于允许请求被授予，则询问已经获得对地址和控制总线的控制的双总线中的第二个的待决请求的状态。特别地，确定是否已经授权了主要请求，并且为双重总线中的第二个请求已经被流水线化。如果已经批准了主要请求并且已经流水线地执行了次要请求，则检查双总线中第二个请求的优先级。如果对于双总线中的第二个双总线的未决请求的优先级至少等于对于双总线中的第一个双总线的当前未决请求，则这些请求被屏蔽，使得它们不再似乎在等待，其中允许授予第一个双总线的请求。

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