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1. 发明授权

US06772254B2 Multi-master computer system with overlapped read and write operations and scalable address pipelining 失效
标题翻译：具有重叠读写操作和可扩展地址流水线的多主计算机系统
公开(公告)号：US06772254B2
公开(公告)日：2004-08-03
申请号：US09855831
申请日：2001-05-15
申请人： Richard Gerard Hofmann , Jason Michael Hopp , Peter Dean LaFauci , Dennis Charles Wilkerson
发明人： Richard Gerard Hofmann , Jason Michael Hopp , Peter Dean LaFauci , Dennis Charles Wilkerson
IPC分类号： G06F1314
CPC分类号： G06F13/364
摘要： A multi-master computer system having overlapped read and write signal with scalable address pipelining programmable increases the depth of address pipelining independently on two overlapped read and write data busses up to “N” deep requests. The system includes a local bus having an address bus, a read bus, and a write bus. Master devices are coupled to separate address, read data and write data buses. Slave devices are attached to the data busses through shared, but decoupled address, read and write data buses. An arbiter is coupled to the data bus and allows masters to compete for bus ownership. The arbiter includes read and write pipeline logic for processing and priortizing master and slave read and write data transfers across the data bus. Programming apparatus alters the read and write pipeline logic for address pipelining
摘要翻译：具有重叠的读和写信号与可扩展地址流水线可编程的多主计算机系统在两个重叠的读和写数据总线上独立地增加地址流水线的深度，直到“N”个深度请求。该系统包括具有地址总线，读总线和写总线的本地总线。主器件耦合到单独的地址，读取数据和写入数据总线。从设备通过共享但解耦的地址，读写数据总线连接到数据总线。仲裁器耦合到数据总线，并允许主机竞争总线所有权。仲裁器包括读写流水线逻辑，用于处理和优化主数据和从属读写数据总线上的数据传输。编程设备改变了用于地址流水线化的读写流水线逻辑

2. 发明授权

US06055584A Processor local bus posted DMA FlyBy burst transfers 失效
标题翻译：处理器本地总线发送DMA FlyBy突发传输
公开(公告)号：US06055584A
公开(公告)日：2000-04-25
申请号：US975540
申请日：1997-11-20
申请人： Jeffrey Todd Bridges , Edward Hammond Green, III , Richard Gerard Hofmann , David Otero , Mark Michael Schaffer , Dennis Charles Wilkerson
发明人： Jeffrey Todd Bridges , Edward Hammond Green, III , Richard Gerard Hofmann , David Otero , Mark Michael Schaffer , Dennis Charles Wilkerson
IPC分类号： G06F13/28 , G06F12/00
CPC分类号： G06F13/28
摘要： A method and implementing system are provided which includes a DMA controller coupled to a slave bus controller through a processor local bus. The slave bus controller is also coupled to a memory unit. The memory unit is connected directly to a peripheral device. The DMA controller is arranged to receive a data transfer request from the peripheral unit and initiate a transfer cycle with the slave bus controller. The slave bus controller is selectively operable to assert a transfer signal to the memory unit which enables data movement directly between memory and the peripheral device in accordance with the request from the peripheral device. Upon completion of the address transfer and prior to the completion of the data transfer, the slave bus controller generates a transfer complete signal back to the peripheral device. This technique allows for a DMA FlyBy transfer to be overlapped with a subsequent processor local bus transfer.
摘要翻译：提供了一种方法和实现系统，其包括通过处理器局部总线耦合到从总线控制器的DMA控制器。从总线控制器还耦合到存储器单元。存储器单元直接连接到外围设备。 DMA控制器被布置成从外围单元接收数据传输请求，并且与从总线控制器发起传输周期。从总线控制器可选择性地操作以将传送信号断言到存储器单元，该存储器单元能够根据来自外围设备的请求直接在存储器和外围设备之间进行数据移动。在地址传送完成之后，在完成数据传输之前，从总线控制器产生传输完成信号回外围设备。这种技术允许DMA FlyBy传输与随后的处理器局部总线传输重叠。

3. 发明授权

US6032238A Overlapped DMA line transfers 失效
标题翻译：重叠的DMA线路传输
公开(公告)号：US6032238A
公开(公告)日：2000-02-29
申请号：US20123
申请日：1998-02-06
申请人： Edward Hammond Green, III , Richard Gerard Hofmann , Mark Michael Schaffer , Dennis Charles Wilkerson
发明人： Edward Hammond Green, III , Richard Gerard Hofmann , Mark Michael Schaffer , Dennis Charles Wilkerson
IPC分类号： G06F13/28 , G06F12/00
CPC分类号： G06F13/28
摘要： A method and apparatus is provided which allows overlapping of DMA line read and line write cycles. In an exemplary embodiment, the PLB Line Read Word Address bus is used with a DMA controller sideband signal to detect the conditions required to allow the DMA controller to start the line write one cycle prior to the completion of the line read cycle. A reference bit is set when the first word of a multi-word line transfer has been read. A sideband timing signal is generated one cycle prior to the completion of the read cycle indicating that there is only one read data phase remaining of the line read. If the first word to be written out to memory has been read or is available when the timing signal is generated, the write operation is begun prior to the final phase of the memory read transfer, and the read and write operations are overlapped thereby accomplishing an overlapped read/write transfer in fewer cycles than the sum of read and write transfer cycles if done sequentially.
摘要翻译：提供了允许DMA线读取和行写入周期重叠的方法和装置。在示例性实施例中，PLB线读取字地址总线与DMA控制器边带信号一起使用，以检测在线读取周期完成之前允许DMA控制器开始行写入一个周期所需的条件。当读取多字行传输的第一个字时，设置一个参考位。边缘定时信号在读周期完成之前一个周期产生，表示只读一行读取数据相位。如果要在存储器中写入的第一个字已经被读取或在生成定时信号时可用，则在存储器读取传送的最后阶段之前开始写入操作，并且读取和写入操作重叠，从而完成如果顺序完成，则读取/写入传输的循环次数比读取和写入传输周期的总和少。

4. 发明授权

US07096297B2 System and method for delaying an interrupt request until corresponding data is provided to a destination device 失效
标题翻译：用于延迟中断请求的系统和方法，直到向目标设备提供相应的数据
公开(公告)号：US07096297B2
公开(公告)日：2006-08-22
申请号：US10804873
申请日：2004-03-19
申请人： Richard Gerard Hofmann , Jason Michael Hopp , Dennis Charles Wilkerson
发明人： Richard Gerard Hofmann , Jason Michael Hopp , Dennis Charles Wilkerson
IPC分类号： G06F13/24 , G06F9/46
CPC分类号： G06F13/24
摘要： A method and system for forwarding interrupt requests from a source device to a destination device. A controller bridge receives data, from a source device, for a destination device and stores the incoming data in a data queue. An interrupt request is received from the source device for the destination device and forwarded to the destination device in response to completing a transfer of the data from the source device to the destination device. If data received from the source device for the destination device are pending in the data queue, the interrupt request is rejected and the source may resubmit the interrupt request at a later time. If additional data are received from the source device for the destination device, the data may be rejected in response to an interrupt pending in the interrupt queue from the source device for the destination device.
摘要翻译：一种用于将来自源设备的中断请求转发到目的地设备的方法和系统。控制器桥接器从源设备接收用于目的地设备的数据，并将输入数据存储在数据队列中。响应于完成从源设备到目的地设备的数据传输，从目的地设备的源设备接收到中断请求并转发到目的地设备。如果数据队列中从目标设备的源设备接收到的数据处于待处理状态，则中断请求被拒绝，并且源可能会在稍后重新提交中断请求。如果从目标设备的源设备接收到附加数据，则响应于来自目的设备的源设备的中断队列中的等待中断，数据可能被拒绝。

5. 发明授权

US06513089B1 Dual burst latency timers for overlapped read and write data transfers 失效
标题翻译：用于重叠读和写数据传输的双突发等待时间计时器
公开(公告)号：US06513089B1
公开(公告)日：2003-01-28
申请号：US09574101
申请日：2000-05-18
申请人： Richard Gerard Hofmann , Peter Dean LaFauci , Dennis Charles Wilkerson
发明人： Richard Gerard Hofmann , Peter Dean LaFauci , Dennis Charles Wilkerson
IPC分类号： G06F100
CPC分类号： G06F13/28
摘要： The present invention discloses a method and system for managing independent read and write buses by dividing the pending read and write request signals and the read and write request priority level signals. The arbitration for use of the read and write buses are done independently for the read and write operations. A higher priority read, for example, can be concurrent with a corresponding lower priority write. Interruption of in process reads or writes is also done using the split arbitrations of the read and write buses leading the disruption of lower priority operations only if the conflicts are concurrent for the same read or write operation.
摘要翻译：本发明公开了一种通过划分未决读和写请求信号和读和写请求优先级信号来管理独立读和写总线的方法和系统。用于读写总线的仲裁是独立完成的，用于读写操作。例如，较高优先级读取可以与相应的较低优先级写入并发。只有在相同的读取或写入操作的冲突是并发的情况下，进程读取或写入的中断也是使用读取和写入总线的拆分仲裁来引导较低优先级操作的中断。

6. 发明授权

US6047336A Speculative direct memory access transfer between slave devices and memory 失效
标题翻译：从设备和存储器之间的直接存储器访问传输
公开(公告)号：US6047336A
公开(公告)日：2000-04-04
申请号：US39645
申请日：1998-03-16
申请人： Edward Hammond Green, III , Richard Gerard Hofmann , Mark Michael Schaffer , Dennis Charles Wilkerson
发明人： Edward Hammond Green, III , Richard Gerard Hofmann , Mark Michael Schaffer , Dennis Charles Wilkerson
IPC分类号： G06F13/28
CPC分类号： G06F13/28
摘要： A DMA Controller, in response to a data transfer request from a slave device, initiates a memory transfer cycle and informs the slave device when the data transfer has completed. In order to avoid dead clock cycles on internal bus(es), the DMA Controller initiates a speculative data transfer cycle after the notification. The DMA Controller aborts the speculative data transfer cycle if the slave device does not request another data transfer within a predetermined time.
摘要翻译： DMA控制器响应来自从设备的数据传输请求，启动存储器传送周期并在数据传输完成时通知从设备。为了避免内部总线上的死时钟周期，DMA控制器在通知后启动推测数据传输周期。如果从设备在预定时间内没有请求另一个数据传输，则DMA控制器中止推测数据传输周期。

7. 发明授权

US06633994B1 Method and system for optimizing data transfers between devices interconnected by buses operating at different clocking speeds 失效
标题翻译：用于优化通过以不同时钟速度运行的总线互连的设备之间的数据传输的方法和系统
公开(公告)号：US06633994B1
公开(公告)日：2003-10-14
申请号：US09510178
申请日：2000-02-22
申请人： Richard Gerard Hofmann , Jason Michael Hopp , Rhonda Gurganious Mitchell , Dennis Charles Wilkerson
发明人： Richard Gerard Hofmann , Jason Michael Hopp , Rhonda Gurganious Mitchell , Dennis Charles Wilkerson
IPC分类号： G06F506
CPC分类号： G06F1/12 , G06F13/405 , Y02D10/14 , Y02D10/151
摘要： Disclosed is a method and apparatus for optimizing communication between buses operating at different frequencies. A high speed bus provides communication between high speed devices as well as provides communication to a lower speed bus which provides communications between low speed devices and between low speed devices and high speed devices. During transaction reset a bridge device that controls communication between the high and low speed buses determines the ratio of the respective bus clocks. The bridge device sets a logic state machine based on this data and selects from the higher frequency clock selected cycles on which transfers to the lower speed bus take place. The unused cycles of the high speed clock may then be used on the high speed bus for additional transfers. The clock ratios may be determined on each transaction reset and new data on clock ratios stored in the bridge device for subsequent operation.
摘要翻译：公开了一种用于优化在不同频率下工作的总线之间的通信的方法和装置。高速总线提供高速设备之间的通信，并且提供与提供低速设备之间以及低速设备和高速设备之间的通信的低速总线的通信。在事务重置期间，控制高速和低速总线之间的通信的桥接器件确定各个总线时钟的比率。桥接器件基于该数据设置逻辑状态机，并从选择的较高频率时钟周期中选择发送到低速总线的传输。然后可以在高速总线上使用高速时钟的未使用的周期进行额外的传输。可以在每个事务重置上确定时钟比率，并且存储在桥接器件中的时钟比率的新数据用于后续操作。

8. 发明授权

US06587905B1 Dynamic data bus allocation 失效
标题翻译：动态数据总线分配
公开(公告)号：US06587905B1
公开(公告)日：2003-07-01
申请号：US09606463
申请日：2000-06-29
申请人： Anthony Correale, Jr. , Richard Gerard Hofmann , Peter Dean LaFauci , Dennis Charles Wilkerson
发明人： Anthony Correale, Jr. , Richard Gerard Hofmann , Peter Dean LaFauci , Dennis Charles Wilkerson
IPC分类号： G06F1300
CPC分类号： G06F13/364
摘要： A high performance integrated circuit (IC) with independent read and write data busses enables full simultaneous read and write data transfers between devices coupled to the buses. Multiple master and multiple slave devices communicate using the resources of a bus controller and a bus arbiter. Having separate read and write data busses with separate and independent arbitration allows reads and writes from different devices to occur simultaneously. Many high performance IC, like systems on a chip (SOC), have many different functional units communicating with a central processing unit (CPU). Many such CPUs have architectures that may cause in certain applications an unbalance between read and write traffic on the independent busses. Master and slave devices contain auxiliary internal read and write data buses multiplexed such that read or write data may be interchanged. A corresponding Auxiliary_(read or write) command is routed to the slave units to notify the units when to route normal read or write data to an idle bus. The bus controller may use this added feature to optimize the available bandwidth of independent read and write data busses up to the limit where a read or write bandwidth may be two times that available if the read and write data buses were used only for their normal traffic.
摘要翻译：具有独立读写数据总线的高性能集成电路（IC）使得能够在耦合到总线的器件之间实现全面同时的读和写数据传输。多个主设备和多个从设备使用总线控制器和总线仲裁器的资源进行通信。具有独立且独立仲裁的单独的读写数据总线允许来自不同设备的读取和写入同时发生。许多高性能IC，如片上系统（SOC），具有与中央处理单元（CPU）通信的许多不同功能单元。许多这样的CPU具有在某些应用中可能导致独立总线上的读取和写入流量之间的不平衡的架构。主设备和从设备包含辅助内部读和写数据总线进行复用，使得读或写数据可以互换。相应的辅助（读或写）命令被路由到从单元，以通知单元何时将正常读或写数据传送到空闲总线。总线控制器可以使用这个附加功能来优化独立的读和写数据总线的可用带宽，直到只有在读写数据总线仅用于其正常业务时，读或写带宽可能是可用的两倍。

9. 发明授权

US06430641B1 Methods, arbiters, and computer program products that can improve the performance of a pipelined dual bus data processing system 有权
标题翻译：可以提高流水线双总线数据处理系统性能的方法，仲裁器和计算机程序产品
公开(公告)号：US06430641B1
公开(公告)日：2002-08-06
申请号：US09304939
申请日：1999-05-04
申请人： Richard Gerard Hofmann , Peter Dean LaFauci , Dennis Charles Wilkerson
发明人： Richard Gerard Hofmann , Peter Dean LaFauci , Dennis Charles Wilkerson
IPC分类号： G06F1338
CPC分类号： G06F13/364
摘要： Methods, arbiters, and computer program products determine if a request for an idle bus in a dual bus data processing system is being blocked by one or more pending requests for the other bus. In this circumstance, any such pending request for the other bus is masked by the arbiter so that the request for the idle bus can be granted. Consequently, a more efficient utilization of the dual bus architecture is achieved. In an illustrative embodiment, a bus request is received for a first one of the dual busses. If the address and control busses are unavailable to allow the request to be granted, then an inquiry is made regarding the status of a pending request for the second one of the dual busses that has gained control of the address and control busses. In particular, it is determined whether a primary request has been granted and a secondary request has been pipelined for the second one of the dual busses. If a primary request has been granted and a secondary request has been pipelined, then the priority of the pending requests for the second one of the dual busses are examined. If the priority of the pending requests for the second one of the dual busses are at least as high as the currently pending request for the first one of the dual busses, then these requests are masked so that they no longer appears to be pending, which allows the request for the first one of the dual busses to be granted.
摘要翻译：方法，仲裁器和计算机程序产品确定对双总线数据处理系统中的空闲总线的请求是否被另一总线的一个或多个未决请求阻止。在这种情况下，任何这样的对另一总线的等待请求被仲裁器屏蔽，以便可以授予空闲总线的请求。因此，实现了双总线架构的更有效的利用。在说明性实施例中，为双总线中的第一个接收总线请求。如果地址和控制总线不可用于允许请求被授予，则询问已经获得对地址和控制总线的控制的双总线中的第二个的待决请求的状态。特别地，确定是否已经授权了主要请求，并且为双重总线中的第二个请求已经被流水线化。如果已经批准了主要请求并且已经流水线地执行了次要请求，则检查双总线中第二个请求的优先级。如果对于双总线中的第二个双总线的未决请求的优先级至少等于对于双总线中的第一个双总线的当前未决请求，则这些请求被屏蔽，使得它们不再似乎在等待，其中允许授予第一个双总线的请求。

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