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21. 发明授权

US06735690B1 Specifying different type generalized event and action pair in a processor 有权
标题翻译：在处理器中指定不同类型的广义事件和动作对
公开(公告)号：US06735690B1
公开(公告)日：2004-05-11
申请号：US09598566
申请日：2000-06-21
申请人： Edwin F. Barry , Patrick R. Marchand , Gerald G. Pechanek , Charles W. Kurak, Jr.
发明人： Edwin F. Barry , Patrick R. Marchand , Gerald G. Pechanek , Charles W. Kurak, Jr.
IPC分类号： G06F1500
CPC分类号： G06F9/30054 , G06F9/30101 , G06F9/30112 , G06F9/325
摘要： A processor with a generalized eventpoint architecture, which is scalable for use in a very long instruction word (VLIW) array processor, such as the manifold array (ManArray) processor is described. In one aspect, generalized processor event (p-event) detection facilities are provided by use of compares to check if an instruction address, a data memory address, an instruction, a data value, arithmetic-condition flags, or other processor change of state eventpoint has occurred. In another aspect, generalized processor action (p-action) facilities are provided to cause a change in the program flow by loading the program counter with a new instruction address, generate an interrupt, signal a semaphore, log or count the p-event, time stamp the event, initiate a background operation, or to cause other p-actions to occur. The generalized facilities are defined in the eventpoint architecture as consisting of a control register and three eventpoint parameters, namely at least one register to compare against, a register containing a second compare register, a vector address, or parameter to be passed, and a count or mask register. Based upon this generalized eventpoint architecture, new capabilities are enabled. For example, auto-looping with capabilities to branch out of a nested auto-loop upon detection of a specified condition, background DMA facilities, the ability to link a chain of p-events together for debug purposes, and others are all important capabilities which are readily obtained.
摘要翻译：描述了具有广泛事件点架构的处理器，其可扩展以用于非常长的指令字（VLIW）阵列处理器，例如歧管阵列（ManArray）处理器。在一个方面，通过使用比较来提供广义处理器事件（p事件）检测设施，以检查指令地址，数据存储器地址，指令，数据值，算术条件标志或其他处理器状态变化事件点已发生。在另一方面，提供通用处理器动作（p-action）功能以通过用新的指令地址加载程序计数器来产生程序流程的改变，生成中断，信号信号，记录或计数p事件，事件时间戳，启动后台操作，或导致其他动作发生。广义设施在事件点架构中被定义为由控制寄存器和三个事件点参数组成，即至少要有一个要比较的寄存器，一个包含第二个比较寄存器的寄存器，一个向量地址或要传递的参数，以及一个计数或屏蔽寄存器。基于这种广义的事件点架构，启用了新的功能。例如，在检测到指定的条件时，自动循环具有分支出嵌套自动循环的功能，后台DMA设施，将p个事件链链接在一起用于调试目的的能力等等都是重要的功能容易获得。

22. 发明授权

US06343356B1 Methods and apparatus for dynamic instruction controlled reconfiguration register file with extended precision 有权
标题翻译：动态指令控制重配置寄存器文件的扩展精度的方法和装置
公开(公告)号：US06343356B1
公开(公告)日：2002-01-29
申请号：US09169255
申请日：1998-10-09
申请人： Gerald G. Pechanek , Edwin F. Barry
发明人： Gerald G. Pechanek , Edwin F. Barry
IPC分类号： G06F930
CPC分类号： G06F9/30036 , G06F9/30105 , G06F9/30112 , G06F9/3012 , G06F9/3016
摘要： A reconfigurable register file integrated in an instruction set architecture capable of extended precision operations, and also capable of parallel operation on lower precision data is described. A register file is composed of two separate files with each half containing half as many registers as the original. The halves are designated even or odd by virtue of the register addresses which they contain. Single width and double width operands are optimally supported without increasing the register file size and without increasing the number of register file ports. Separate extended registers are also employed to provide extended precision for operations such as multiply-accumulate operations.
摘要翻译：描述集成在能够进行扩展精度操作并且还能够对较低精度数据进行并行操作的指令集架构中的可重配置寄存器文件。注册文件由两个单独的文件组成，每个文件的每个文件包含与原始文件一样多的寄存器。这两半由于它们包含的寄存器地址而被指定为偶数或奇数。单个宽度和双宽度操作数得到最佳支持，而不增加寄存器文件大小，而不增加寄存器文件端口数量。还使用单独的扩展寄存器来为诸如乘法累加操作的操作提供扩展精度。

23. 发明授权

US6167502A Method and apparatus for manifold array processing 失效
标题翻译：用于歧管阵列处理的方法和装置
公开(公告)号：US6167502A
公开(公告)日：2000-12-26
申请号：US949122
申请日：1997-10-10
申请人： Gerald G. Pechanek , Nikos P. Pitsianis , Edwin F. Barry , Thomas L. Drabenstott
发明人： Gerald G. Pechanek , Nikos P. Pitsianis , Edwin F. Barry , Thomas L. Drabenstott
IPC分类号： G06F15/80 , G06F15/00
CPC分类号： G06F15/8023
摘要： A manifold array topology includes processing elements, nodes, memories or the like arranged in clusters. Clusters are connected by cluster switch arrangements which advantageously allow changes of organization without physical rearrangement of processing elements. A significant reduction in the typical number of interconnections for preexisting arrays is also achieved. Fast, efficient and cost effective processing and communication result with the added benefit of ready scalability.
摘要翻译：歧管阵列拓扑包括以簇排列的处理元件，节点，存储器等。集群通过集群交换机布置连接，其有利地允许组织的改变而不需要处理元件的物理重排。也实现了预先存在的阵列的典型互连数量的显着减少。快速，高效和经济高效的处理和通信带来了可扩展性的附加优势。

24. 发明授权

US06101592A Methods and apparatus for scalable instruction set architecture with dynamic compact instructions 有权
公开(公告)号：US06101592A
公开(公告)日：2000-08-08
申请号：US215081
申请日：1998-12-18
申请人： Gerald G. Pechanek , Edwin F. Barry , Juan Guillermo Revilla , Larry D. Larsen
发明人： Gerald G. Pechanek , Edwin F. Barry , Juan Guillermo Revilla , Larry D. Larsen
IPC分类号： G06F9/30 , G06F9/318 , G06F9/38 , G06F15/80
CPC分类号： G06F9/3822 , G06F9/30145 , G06F9/30149 , G06F9/30178 , G06F9/30181 , G06F9/382 , G06F9/3885
摘要： A hierarchical instruction set architecture (ISA) provides pluggable instruction set capability and support of array processors. The term pluggable is from the programmer's viewpoint and relates to groups of instructions that can easily be added to a processor architecture for code density and performance enhancements. One specific aspect addressed herein is the unique compacted instruction set which allows the programmer the ability to dynamically create a set of compacted instructions on a task by task basis for the primary purpose of improving control and parallel code density. These compacted instructions are parallelizable in that they are not specifically restricted to control code application but can be executed in the processing elements (PEs) in an array processor. The ManArray family of processors is designed for this dynamic compacted instruction set capability and also supports a scalable array of from one to N PEs. In addition, the ManArray ISA is defined as a hierarchy of ISAs which allows for future growth in instruction capability and supports the packing of multiple instructions within a hierarchy of instructions.

25. 发明申请

US20130019082A1 Manifold Array Processor 审中-公开
标题翻译：歧管阵列处理器
公开(公告)号：US20130019082A1
公开(公告)日：2013-01-17
申请号：US13616942
申请日：2012-09-14
申请人： Gerald G. Pechanek , Charles W. Kurak, JR.
发明人： Gerald G. Pechanek , Charles W. Kurak, JR.
IPC分类号： G06F15/80
CPC分类号： G06F15/17381 , G06F9/30076 , G06F15/17337 , G06F15/8023
摘要： An array processor includes processing elements arranged in to form a rectangular array. Inter-cluster communication paths are mutually exclusive. Due to the mutual exclusivity of the data paths, communications between the processing elements of each cluster may be combined in a single inter-cluster path, thus eliminating half the wiring required for the path. The length of the longest communication path is not directly determined by the overall dimension of the array, as in conventional torus arrays. Rather, the longest communications path is limited by the inter-cluster spacing. Transpose elements of an N×N torus may be combined in clusters and communicate with one another through intra-cluster communications paths. Transpose operation latency is eliminated in this approach. Each PE may have a single transmit port and a single receive port. Thus, the individual PEs are decoupled from the array topology.
摘要翻译：阵列处理器包括布置成形成矩形阵列的处理元件。群集间通信路径是互斥的。由于数据路径的相互独占性，每个集群的处理元件之间的通信可以组合在单个集群间路径中，从而消除路径所需的一半接线。最长通信路径的长度不直接取决于阵列的整体尺寸，如在常规环形阵列中。相反，最长的通信路径受群间间隔的限制。 N×N环面的移位元素可以组合在一起，并通过群内通信路径相互通信。这种方法消除了转置操作延迟。每个PE可以具有单个发送端口和单个接收端口。因此，各个PE与阵列拓扑分离。

26. 发明申请

US20130007421A1 Methods and Apparatus for Efficient Complex Long Multiplication and Covariance Matrix Implementation 审中-公开
标题翻译：高效复合长乘法和协方差矩阵实现方法与装置
公开(公告)号：US20130007421A1
公开(公告)日：2013-01-03
申请号：US13613769
申请日：2012-09-13
申请人： Gerald G. Pechanek , Ricardo Rodriguez , Matthew Plonski , David Strube , Kevin Coopman
发明人： Gerald G. Pechanek , Ricardo Rodriguez , Matthew Plonski , David Strube , Kevin Coopman
IPC分类号： G06F9/302
CPC分类号： G06F7/4812 , G06F9/30014 , G06F9/325 , G06F9/3885 , G06F17/15 , G06F17/16 , G06F2207/3896
摘要： Efficient computation of complex long multiplication results and an efficient calculation of a covariance matrix are described. A parallel array VLIW digital signal processor is employed along with specialized complex long multiplication instructions and communication operations between the processing elements which are overlapped with computation to provide very high performance operation. Successive iterations of a loop of tightly packed VLIWs may be used allowing the complex multiplication pipeline hardware to be efficiently used.
摘要翻译：描述了复数长乘法结果的有效计算和协方差矩阵的有效计算。采用并行阵列VLIW数字信号处理器以及与计算重叠的处理元件之间的专门的复数长乘法指令和通信操作，以提供非常高的性能操作。可以使用紧密压缩的VLIW的循环的连续迭代，允许有效地使用复数乘法管线硬件。

27. 发明申请

US20080222333A1 Methods and Apparatus for Scalable Array Processor Interrupt Detection and Response 有权
标题翻译：用于可扩展阵列处理器中断检测和响应的方法和装置
公开(公告)号：US20080222333A1
公开(公告)日：2008-09-11
申请号：US12120543
申请日：2008-05-14
申请人： Edwin Frank Barry , Patrick R. Marchand , Gerald G. Pechanek , Larry D. Larsen
发明人： Edwin Frank Barry , Patrick R. Marchand , Gerald G. Pechanek , Larry D. Larsen
IPC分类号： G06F13/24 , G06F9/30 , G06F9/312
CPC分类号： G06F9/3865 , G06F9/30058 , G06F9/3861 , G06F9/4812 , G06F11/27 , G06F13/26 , Y02D10/14 , Y02D10/24
摘要： Hardware and software techniques for interrupt detection and response in a scalable pipelined array processor environment are described. Utilizing these techniques, a sequential program execution model with interrupts can be maintained in a highly parallel scalable pipelined array processing containing multiple processing elements and distributed memories and register files. When an interrupt occurs, interface signals are provided to all PEs to support independent interrupt operations in each PE dependent upon the local PE instruction sequence prior to the interrupt. Processing/element exception interrupts are supported and low latency interrupt processing is also provided for embedded systems where real time signal processing is required. Further, a hierarchical interrupt structure is used allowing a generalized debug approach using debut interrupts and a dynamic debut monitor mechanism.
摘要翻译：描述了可扩展流水线阵列处理器环境中的中断检测和响应的硬件和软件技术。利用这些技术，可以在包含多个处理元件和分布式存储器和寄存器文件的高度并行的可扩展流水线阵列处理中维持具有中断的顺序程序执行模型。当发生中断时，接口信号提供给所有PE，以支持每个PE中的独立中断操作，取决于中断前的本地PE指令序列。支持处理/元件异常中断，并为需要实时信号处理的嵌入式系统提供低延迟中断处理。此外，使用分层中断结构，允许使用初次中断的通用调试方法和动态登场监视机制。

28. 发明授权

US06842811B2 Methods and apparatus for scalable array processor interrupt detection and response 失效
标题翻译：用于可扩展阵列处理器中断检测和响应的方法和装置
公开(公告)号：US06842811B2
公开(公告)日：2005-01-11
申请号：US09791256
申请日：2001-02-23
申请人： Edwin Frank Barry , Patrick R. Marchand , Gerald G. Pechanek , Larry D. Larsen
发明人： Edwin Frank Barry , Patrick R. Marchand , Gerald G. Pechanek , Larry D. Larsen
IPC分类号： G06F9/00 , G06F9/38 , G06F9/48 , G06F13/24 , G06F13/26
CPC分类号： G06F9/3865 , G06F9/30058 , G06F9/3861 , G06F9/4812 , G06F11/27 , G06F13/26 , Y02D10/14 , Y02D10/24
摘要： Hardware and software techniques for interrupt detection and response in a scalable pipelined array processor environment are described. Utilizing these techniques, a sequential program execution model with interrupts can be maintained in a highly parallel scalable pipelined array processing containing multiple processing elements (PEs) and distributed memories and register files. When an interrupt occurs, interface signals are provided to all PEs to support independent interrupt operations in each PE dependent upon the local PE instruction sequence prior to the interrupt. Processing/element exception interrupts are supported and low latency interrupt processing is also provided for embedded systems where real time signal processing is required. Further, a hierarchical interrupt structure is used allowing a generalized debug approach using debug interrupts and a dynamic debuts monitor mechanism.
摘要翻译：描述了可扩展流水线阵列处理器环境中的中断检测和响应的硬件和软件技术。利用这些技术，可以在包含多个处理元件（PE）和分布式存储器和寄存器文件的高度并行的可扩展流水线阵列处理中维持具有中断的顺序程序执行模型。当发生中断时，接口信号提供给所有PE，以支持每个PE中的独立中断操作，取决于中断前的本地PE指令序列。支持处理/元件异常中断，并为需要实时信号处理的嵌入式系统提供低延迟中断处理。此外，使用分层中断结构，允许使用调试中断的通用调试方法和动态初始化监视机制。

29. 发明授权

US06704857B2 Methods and apparatus for loading a very long instruction word memory 有权
标题翻译：用于加载非常长的指令字存储器的方法和装置
公开(公告)号：US06704857B2
公开(公告)日：2004-03-09
申请号：US09747056
申请日：2000-12-22
申请人： Edwin Frank Barry , Gerald G. Pechanek
发明人： Edwin Frank Barry , Gerald G. Pechanek
IPC分类号： G06F1500
CPC分类号： G06F9/382 , G06F9/30149 , G06F9/3017 , G06F9/3802 , G06F9/3853 , G06F13/28 , G06F2213/2808
摘要： The ManArray processor is a scalable indirect VLIW array processor that defines two preferred architectures for indirect VLIW memories. One approach treats the VIM as one composite block of memory using one common address interface to access any VLIW stored in the VIM. The second approach treats the VIM as made up of multiple smaller VIMs each individually associated with the functional units and each individually addressable for loading and reading during XV execution. The VIM memories, contained in each processing element (PE), are accessible by the same type of LV and XV Short Instruction Words (SIWs) as in a single processor instantiation of the indirect VLIW architecture. In the ManArray architecture, the control processor, also called a sequence processor (SP), fetches the instructions from the SIW memory and dispatches them to itself and the PEs. By using the LV instruction, VLIWs can be loaded into VIMs in the SP and the PEs. Since the LV instruction is supplied by the SP through the instruction stream, when VLIWs are being loaded into any VIM no other processing takes place. In addition, as defined in the ManArray architecture, when the SP is processing SIWs, such as control and other sequential code, the PE array is not executing any instructions. Techniques are provided herein to independently load the VIMs concurrent with SIW or iVLIW execution on the SP or on the PEs thereby allowing the load latency to be hidden by the computation.
摘要翻译： ManArray处理器是可扩展的间接VLIW阵列处理器，它定义了间接VLIW存储器的两种优选架构。一种方法将VIM视为一个复合的存储器块，使用一个公共地址接口访问存储在VIM中的任何VLIW。第二种方法将VIM视为由功能单元单独关联的多个较小的VIM组成，并且每个VIM单独可寻址以在XV执行期间进行加载和读取。包含在每个处理元件（PE）中的VIM存储器可以通过与间接VLIW架构的单处理器实例化中相同类型的LV和XV短指令字（SIW）来访问。在ManArray架构中，控制处理器（也称为序列处理器（SP））从SIW存储器中获取指令，并将它们分派给自身和PE。通过使用LV指令，VLIW可以加载到SP和PE中的VIM中。由于LV指令由SP通过指令流提供，当VLIW被加载到任何VIM中时，不会发生其他处理。另外，如ManArray架构所定义的，当SP正在处理SIW（例如控制和其他顺序代码）时，PE阵列不执行任何指令。本文提供了技术来独立地在SP或PE上独立地加载与SIW或iVLIW执行的VIM，从而允许通过计算隐藏负载等待时间。

30. 发明授权

US5659785A Array processor communication architecture with broadcast processor instructions 失效
标题翻译：具有广播处理器指令的阵列处理器通信架构
公开(公告)号：US5659785A
公开(公告)日：1997-08-19
申请号：US386384
申请日：1995-02-10
申请人： Gerald G. Pechanek , Larry D. Larsen , Clair John Glossner , Stamatis Vassiliaadis
发明人： Gerald G. Pechanek , Larry D. Larsen , Clair John Glossner , Stamatis Vassiliaadis
IPC分类号： G06F15/16 , G06F15/173 , G06F15/177 , G06F15/80
CPC分类号： G06F15/17381
摘要： A plurality of processor elements (PEs) are connected in a duster by a common instruction bus to a sequencing control unit with its associated instruction memory. Each PE has data buses connected to at least its four nearest PE neighbors, referred to as its North, South, East and West PE neighbors. Each PE also has a general purpose register file containing several operand registers. A common instruction is fetched from the instruction memory by the sequencing control unit and broadcast over the instruction bus to each PE in the cluster. The instruction includes an upcode value that controls the arithmetic or logical operation performed by an execution unit in the PE on one or more operands in the register file. A switch is included in each PE to interconnect it with a first PE neighbor as the destination to which the result from the execution unit is sent. The broadcast instruction includes a destination field that controls the switch in the PE, to dynamically select the destination neighbor PE to which the result is sent. Further, the broadcast instruction includes a target field that controls the switch in the PE, to dynamically select the operand register in the register file of the PE, to which another result received from another neighbor PE in the cluster is stored. In this manner, the instruction broadcast to all the PEs in the cluster, dynamically controls the communication of operands and results between the PEs in the cluster, in a single instruction, multiple data processor array.
摘要翻译：多个处理器元件（PE）通过公共指令总线连接到除尘器中，其具有与其相关联的指令存储器的排序控制单元。每个PE都有数据总线连接到至少其四个最近的PE邻居，称为其北，南，东和西PE邻居。每个PE还有一个包含多个操作数寄存器的通用寄存器文件。通过排序控制单元从指令存储器取出通用指令，并通过指令总线广播到集群中的每个PE。该指令包括一个上限值，其控制由PE中的执行单元在寄存器文件中的一个或多个操作数上执行的算术或逻辑操作。每个PE中包括一个交换机，将其与第一个PE邻居进行互连，作为发送执行单元的结果的目的地。广播指令包括控制PE中的交换机的目的地字段，动态地选择发送结果的目的地邻居PE。此外，广播指令包括控制PE中的交换机的目标字段，动态地选择PE的寄存器文件中的操作数寄存器，存储从群集中的另一个邻居PE接收到的另一结果。以这种方式，向集群中的所有PE广播的指令在单个指令，多数据处理器阵列中动态地控制集群中的PE之间的操作数和结果的通信。

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