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21. 发明授权

US08286114B2 3-dimensional device design layout 有权
标题翻译：三维设备设计布局
公开(公告)号：US08286114B2
公开(公告)日：2012-10-09
申请号：US11833119
申请日：2007-08-02
申请人： Harry Chuang , Kong-Beng Thei , Mong Song Liang , Sheng-Chen Chung , Chih-Tsung Yao , Jung-Hui Kao , Chung Long Cheng , Gary Shen , Gwan Sin Chang
发明人： Harry Chuang , Kong-Beng Thei , Mong Song Liang , Sheng-Chen Chung , Chih-Tsung Yao , Jung-Hui Kao , Chung Long Cheng , Gary Shen , Gwan Sin Chang
IPC分类号： G06F17/50
CPC分类号： H01L29/785 , H01L21/76807 , H01L21/76895 , H01L21/76897 , H01L21/823431 , H01L21/823437 , H01L21/823475 , H01L29/41791 , H01L29/66795 , H01L2029/7858
摘要： A method for defining a layout of 3-D devices, such as a finFET, is provided. The method includes determining an area required by a desired 3-D device and designing a circuit using planar devices having an equivalent area. The planar device corresponding to the desired 3-D device is used to layout a circuit design, thereby allowing circuit and layout designers to work at a higher level without the need to specify each individual fin or 3-D structure. Thereafter, the planar design may be converted to a 3-D design by replacing planar active areas with 3-D devices occupying an equivalent area.
摘要翻译：提供了一种用于定义诸如finFET的3-D器件的布局的方法。该方法包括确定期望的3-D设备所需的区域和使用具有等效面积的平面设备来设计电路。对应于期望的3-D器件的平面器件用于布局电路设计，从而允许电路和布局设计者在更高级别工作，而不需要指定每个单独的鳍或3-D结构。此后，平面设计可以通过用占据等同面积的3-D器件代替平面有源区域而被转换成3维设计。

22. 发明申请

US20110260251A1 Semiconductor Device and Method of Fabricating Same 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20110260251A1
公开(公告)日：2011-10-27
申请号：US13178755
申请日：2011-07-08
申请人： Chung Long Cheng , Sheng-Chen Chung , Kong-Beng Thei , Harry Chuang , Mong-Song Liang
发明人： Chung Long Cheng , Sheng-Chen Chung , Kong-Beng Thei , Harry Chuang , Mong-Song Liang
IPC分类号： H01L27/12
CPC分类号： H01L29/66477 , H01L21/823412 , H01L21/823418 , H01L21/823462 , H01L27/0629 , H01L27/088 , H01L27/0922 , H01L29/7848
摘要： A semiconductor device having a core device with a high-k gate dielectric and an I/O device with a silicon dioxide or other non-high-k gate dielectric, and a method of fabricating such a device. A core well and an I/O well are created in a semiconductor substrate and separated by an isolation structure. An I/O device is formed over the I/O well and has a silicon dioxide or a low-k gate dielectric. A resistor may be formed on an isolation structure adjacent to the core well. A core-well device such as a transistor is formed over the core well, and has a high-k gate dielectric. In some embodiments, a p-type I/O well and an n-type I/O well are created. In a preferred embodiment, the I/O device or devices are formed prior to forming the core device and protected with a sacrificial layer until the core device is fabricated.
摘要翻译：具有具有高k栅极电介质的核心器件和具有二氧化硅或其它非高k栅极电介质的I / O器件的半导体器件及其制造方法。核心阱和I / O阱在半导体衬底中产生并被隔离结构隔开。 I / O器件形成在I / O阱上，并具有二氧化硅或低k栅极电介质。可以在与芯井相邻的隔离结构上形成电阻器。在核心阱上形成诸如晶体管的核心阱器件，并且具有高k栅极电介质。在一些实施例中，产生p型I / O阱和n型I / O阱。在优选实施例中，在形成核心器件之前形成I / O器件或器件，并用牺牲层进行保护，直到制造核心器件。

23. 发明申请

US20110076813A1 Semiconductor Device with both I/O and Core Components and Method of Fabricating Same 有权
标题翻译：具有I / O和核心组件的半导体器件及其制造方法
公开(公告)号：US20110076813A1
公开(公告)日：2011-03-31
申请号：US12961167
申请日：2010-12-06
申请人： Chung Long Cheng , Sheng-Chen Chung , Kong-Beng Thei , Harry Chuang , Mong Song Liang
发明人： Chung Long Cheng , Sheng-Chen Chung , Kong-Beng Thei , Harry Chuang , Mong Song Liang
IPC分类号： H01L21/8238
CPC分类号： H01L29/66477 , H01L21/823412 , H01L21/823418 , H01L21/823462 , H01L27/0629 , H01L27/088 , H01L27/0922 , H01L29/7848
摘要： A semiconductor device having a core device with a high-k gate dielectric and an I/O device with a silicon dioxide or other non-high-k gate dielectric, and a method of fabricating such a device. A core well and an I/O well are created in a semiconductor substrate and separated by an isolation structure. An I/O device is formed over the I/O well and has a silicon dioxide or a low-k gate dielectric. A resistor may be formed on an isolation structure adjacent to the core well. A core-well device such as a transistor is formed over the core well, and has a high-k gate dielectric. In some embodiments, a p-type I/O well and an n-type I/O well are created. In a preferred embodiment, the I/O device or devices are formed prior to forming the core device and protected with a sacrificial layer until the core device is fabricated.
摘要翻译：具有具有高k栅极电介质的核心器件和具有二氧化硅或其它非高k栅极电介质的I / O器件的半导体器件及其制造方法。核心阱和I / O阱在半导体衬底中产生并被隔离结构隔开。 I / O器件形成在I / O阱上，并具有二氧化硅或低k栅极电介质。可以在与芯井相邻的隔离结构上形成电阻器。在核心阱上形成诸如晶体管的核心阱器件，并且具有高k栅极电介质。在一些实施例中，产生p型I / O阱和n型I / O阱。在优选实施例中，在形成核心器件之前形成I / O器件或器件，并用牺牲层进行保护，直到制造核心器件。

24. 发明申请

US20090273055A1 Fuse Structure 有权
标题翻译：保险丝结构
公开(公告)号：US20090273055A1
公开(公告)日：2009-11-05
申请号：US12503641
申请日：2009-07-15
申请人： Kong-Beng Thei , Chung Long Cheng , Chung-Shi Liu , Harry Chuang , Shien-Yang Wu , Shi-Bai Chen
发明人： Kong-Beng Thei , Chung Long Cheng , Chung-Shi Liu , Harry Chuang , Shien-Yang Wu , Shi-Bai Chen
IPC分类号： H01L23/525
CPC分类号： H01L23/5256 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： An electrical fuse and a method of forming the same are presented. A first-layer conductive line is formed over a base material. A via is formed over the first-layer conductive line. The via preferably comprises a barrier layer and a conductive material. A second-layer conductive line is formed over the via. A first external pad is formed coupling to the first-layer conductive line. A second external pad is formed coupling to the second-layer conductive line. The via, the first conductive line and the second conductive line are adapted to be an electrical fuse. The electrical fuse can be burned out by applying a current. The vertical structure of the preferred embodiment is suitable to be formed in any layer.
摘要翻译：提出了电熔丝及其形成方法。在基材上形成第一层导电线。在第一层导电线上形成通孔。通孔优选包括阻挡层和导电材料。在通孔上形成第二层导电线。第一外部焊盘形成为耦合到第一层导电线。第二外部焊盘形成为耦合到第二层导电线。通孔，第一导线和第二导线适于作为电熔丝。电熔丝可以通过施加电流而烧坏。优选实施例的垂直结构适合于形成任何层。

25. 发明申请

US20080179688A1 Method and Apparatus for Semiconductor Device with Improved Source/Drain Junctions 有权
标题翻译：具有改进的源极/漏极结的半导体器件的方法和装置
公开(公告)号：US20080179688A1
公开(公告)日：2008-07-31
申请号：US12058997
申请日：2008-03-31
申请人： Kong Beng Thei , Chung Long Cheng , Harry Chuang
发明人： Kong Beng Thei , Chung Long Cheng , Harry Chuang
IPC分类号： H01L29/78
CPC分类号： H01L21/26586 , H01L21/26506 , H01L21/26513 , H01L29/105 , H01L29/1083 , H01L29/41766 , H01L29/665 , H01L29/6659 , H01L29/7843
摘要： A semiconductor device with improved source/drain junctions and methods for fabricating the device are disclosed. A preferred embodiment comprises a MOS transistor with a gate structure overlying a substrate, lightly doped source/drain regions formed in the substrate aligned to the gate structure, sidewall spacers formed on the sidewalls of the gate structure and overlying the lightly doped source/drain regions, deeper source/drain diffusions formed into the substrate aligned to the sidewall spacers and additional pocket implants of source/drain dopants formed at the boundary of the deeper source/drain diffusions and the substrate. In a preferred method, the additional pocket implants are formed using an angled ion implant with the angle being between 4 and 45 degrees from vertical. Additional embodiments include recesses formed in the source/drain regions and methods for forming the recesses.
摘要翻译：公开了一种具有改善的源极/漏极结的半导体器件和用于制造该器件的方法。优选实施例包括具有覆盖在衬底上的栅极结构的MOS晶体管，形成在衬底中的与栅极结构对准的轻掺杂源极/漏极区域，形成在栅极结构的侧壁上并叠置在轻掺杂源极/漏极区域形成在衬底中的更深的源极/漏极扩散与侧壁间隔物对准，并且在较深的源极/漏极扩散和衬底的边界处形成的源极/漏极掺杂剂的另外的凹穴注入。在优选的方法中，使用角度离子植入物形成额外的袋状植入物，该角度离垂直方向在4度与45度之间。另外的实施例包括在源极/漏极区域中形成的凹部和用于形成凹部的方法。

26. 发明授权

US07298011B2 Semiconductor device with recessed L-shaped spacer and method of fabricating the same 有权
标题翻译：具有凹形L形间隔件的半导体器件及其制造方法
公开(公告)号：US07298011B2
公开(公告)日：2007-11-20
申请号：US11215103
申请日：2005-08-30
申请人： Kong-Beng Thei , Chung-Long Cheng , Harry Chuang
发明人： Kong-Beng Thei , Chung-Long Cheng , Harry Chuang
IPC分类号： H01L29/94
CPC分类号： H01L29/6656 , H01L21/28052 , H01L21/76897 , H01L29/66507 , H01L29/6653
摘要： A semiconductor device with a recessed L-shaped spacer and a method for fabricating the same. A recessed L-shaped spacer includes a vertical portion and a horizontal portion. The vertical portion is disposed on lower sidewalls of a conductor pattern, exposing upper sidewalls thereof. A top spacer is on the L-shaped spacer, wherein a width ratio of the vertical portion of the L-shaped spacer to the top spacer is at least about 2:1.
摘要翻译：具有凹入的L形间隔物的半导体器件及其制造方法。凹进的L形间隔件包括垂直部分和水平部分。垂直部分设置在导体图案的下侧壁上，露出其上侧壁。顶部间隔物在L形间隔件上，其中L形间隔件的垂直部分与顶部间隔物的宽度比为至少约2:1。

27. 发明申请

US20120286368A1 Layout Methods of Integrated Circuits Having Unit MOS Devices 有权
标题翻译：具有单位MOS器件的集成电路布局方法
公开(公告)号：US20120286368A1
公开(公告)日：2012-11-15
申请号：US13558109
申请日：2012-07-25
申请人： Harry Chuang , Kong-Beng Thei , Jen-Bin Hsu , Chung Long Cheng , Mong Song Liang
发明人： Harry Chuang , Kong-Beng Thei , Jen-Bin Hsu , Chung Long Cheng , Mong Song Liang
IPC分类号： H01L27/088
CPC分类号： H01L27/0207 , H01L27/11 , H01L27/1104
摘要： A semiconductor structure includes an array of unit metal-oxide-semiconductor (MOS) devices arranged in a plurality of rows and a plurality of columns is provided. Each of the unit MOS devices includes an active region laid out in a row direction and a gate electrode laid out in a column direction. The semiconductor structure further includes a first unit MOS device in the array and a second unit MOS device in the array, wherein active regions of the first and the second unit MOS devices have different conductivity types.
摘要翻译：半导体结构包括以多行排列的单位金属氧化物半导体（MOS）器件的阵列，并且提供多个列。每个单位MOS器件包括布置在行方向上的有源区和沿列方向布置的栅电极。半导体结构还包括阵列中的第一单元MOS器件和阵列中的第二单元MOS器件，其中第一和第二单位MOS器件的有源区具有不同的导电类型。

28. 发明申请

US20090298243A1 SOI DEVICES AND METHODS FOR FABRICATING THE SAME 有权
标题翻译： SOI器件及其制造方法
公开(公告)号：US20090298243A1
公开(公告)日：2009-12-03
申请号：US12468131
申请日：2009-05-19
申请人： Chung-Long Cheng , Kong-Beng Thei , Sheng-Chen Chung , Tzung-Chi Lee , Harry Chuang
发明人： Chung-Long Cheng , Kong-Beng Thei , Sheng-Chen Chung , Tzung-Chi Lee , Harry Chuang
IPC分类号： H01L21/336
CPC分类号： H01L21/84 , H01L27/1203 , H01L29/4238 , H01L29/78636
摘要： Silicon on insulator (SOI) devices and methods for fabricating the same are provided. An exemplary embodiment of a SOI device comprises a substrate. A first insulating layer is formed over the substrate. A plurality of semiconductor islands is formed over the first insulating layer, wherein the semiconductor islands are isolated from each other. A second insulating layer is formed over the first insulating layer, protruding over the semiconductor islands and surrounding thereof. At least one recess is formed in a portion of the second insulating layer adjacent to a pair of the semiconductor islands. A first dielectric layer is formed on a portion of each of the semiconductor islands. A conductive layer is formed over the first dielectric layer and over the second insulating layer exposed by the recess. A pair of source/drain regions is oppositely formed in portions of each of the semiconductor islands not covered by the first dielectric layer and the conductive layer.
摘要翻译：提供绝缘体上硅（SOI）器件及其制造方法。 SOI器件的示例性实施例包括衬底。在衬底上形成第一绝缘层。在第一绝缘层上形成多个半导体岛，其中半导体岛彼此隔离。在第一绝缘层上形成第二绝缘层，突出在半岛上并围绕它们。在与一对半导体岛相邻的第二绝缘层的一部分中形成至少一个凹部。第一电介质层形成在每个半导体岛的一部分上。导电层形成在第一电介质层之上，并在由凹部露出的第二绝缘层之上。一对源极/漏极区域相对地形成在未被第一介电层和导电层覆盖的半导体岛的每一个的部分中。

29. 发明申请

US20080076215A1 Method for semiconductor device performance enhancement 有权
标题翻译：半导体器件性能提高的方法
公开(公告)号：US20080076215A1
公开(公告)日：2008-03-27
申请号：US11527616
申请日：2006-09-27
申请人： Harry Chuang , Kong-Beng Thei , Chung-Long Cheng , Sheng-Chen Chung , Wen-Huei Guo , Jung-Hui Kao , Ryan Chia-Jen Chen , Mong-Song Liang
发明人： Harry Chuang , Kong-Beng Thei , Chung-Long Cheng , Sheng-Chen Chung , Wen-Huei Guo , Jung-Hui Kao , Ryan Chia-Jen Chen , Mong-Song Liang
IPC分类号： H01L21/8238
CPC分类号： H01L21/823807 , H01L21/823814 , H01L21/823842 , H01L29/7843
摘要： A method of manufacturing a semiconductor device is disclosed. The method provides a semiconductor substrate with at least a PMOS device and at least an NMOS device thereon. A first insulating layer is formed overlying the NMOS and PMOS devices. A second insulating layer is formed overlying the first insulating layer. The second insulating layer overlying the PMOS device is thinned to leave portion of the second insulating layer. A first thermal treatment is performed on the NMOS and PMOS devices. The second insulating layer overlying the NMOS device and the remaining portion of the second insulating layer overlying the PMOS device are removed and the first insulating layer overlying the NMOS and PMOS devices is thinned to leave a remaining portion thereof.
摘要翻译：公开了制造半导体器件的方法。该方法提供具有至少PMOS器件和至少NMOS器件的半导体衬底。在NMOS和PMOS器件上形成第一绝缘层。在第一绝缘层上形成第二绝缘层。覆盖PMOS器件的第二绝缘层变薄以留下第二绝缘层的部分。在NMOS和PMOS器件上进行第一次热处理。去除覆盖NMOS器件的第二绝缘层和覆盖PMOS器件的第二绝缘层的剩余部分，并且覆盖NMOS和PMOS器件的第一绝缘层变薄以留下其余部分。

30. 发明申请

US20060163734A1 Fuse structure and method for making the same 审中-公开
标题翻译：保险丝结构及制作方法
公开(公告)号：US20060163734A1
公开(公告)日：2006-07-27
申请号：US11041585
申请日：2005-01-24
申请人： Kong-Beng Thei , Chung-Long Cheng , Chung-Shi Liu , Harry Chuang
发明人： Kong-Beng Thei , Chung-Long Cheng , Chung-Shi Liu , Harry Chuang
IPC分类号： H01L23/48
CPC分类号： H01L23/5258 , H01L23/5222 , H01L2924/0002 , H01L2924/00
摘要： Provided are a fuse structure and a method for manufacturing the fuse structure. In one example, the method includes providing a multilayer interconnect structure (MLI) over a semiconductor substrate. The MLI includes multiple fuse connection and bonding connection features. A passivation layer is formed over the MLI and patterned to form openings, with each opening being aligned with one of the fuse connection or bonding connection features. A conductive layer is formed on the passivation layer and in the openings. The conductive layer is patterned to form bonding features and fuse structures. Each bonding feature is in contact with one of the bonding connection features, and each fuse structure is in contact with two of the fuse connection features. A cap dielectric layer is formed over the fuse structures and patterned to expose at least one of the bonding features while leaving the fuse structures covered.
摘要翻译：提供了一种熔丝结构和用于制造熔丝结构的方法。在一个示例中，该方法包括在半导体衬底上提供多层互连结构（MLI）。 MLI包括多个保险丝连接和接合连接功能。钝化层形成在MLI上方并被图案化以形成开口，其中每个开口与保险丝连接或接合连接特征中的一个对准。在钝化层和开口中形成导电层。将导电层图案化以形成结合特征和熔丝结构。每个接合特征与接合连接特征之一接触，并且每个熔断器结构与两个熔断器连接特征接触。在熔丝结构之上形成盖电介质层，并将其图案化以暴露粘合特征中的至少一个，同时保留熔丝结构。

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