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1. 发明申请

US20080237885A1 Method for Improving Design Window 审中-公开
标题翻译：改进设计窗口的方法
公开(公告)号：US20080237885A1
公开(公告)日：2008-10-02
申请号：US12134381
申请日：2008-06-06
申请人： Harry Chuang , Kong-Beng Thei , Chih-Tsung Yao , Heng-Kai Liu , Ming-Jer Chiu , Chien-Wen Chen
发明人： Harry Chuang , Kong-Beng Thei , Chih-Tsung Yao , Heng-Kai Liu , Ming-Jer Chiu , Chien-Wen Chen
IPC分类号： H01L23/48
CPC分类号： H01L23/481 , G03F1/144 , G03F1/36 , H01L21/31144 , H01L21/76807 , H01L21/76816 , H01L2924/0002 , H01L2924/00
摘要： A method of forming photo masks having rectangular patterns and a method for forming a semiconductor structure using the photo masks is provided. The method for forming the photo masks includes determining a minimum spacing and identifying vertical conductive feature patterns having a spacing less than the minimum spacing value. The method further includes determining a first direction to expand and a second direction to shrink, and checking against design rules to see if the design rules are violated for each of the vertical conductive feature patterns identified. If designed rules are not violated, the identified vertical conductive feature pattern is replaced with a revised vertical conductive feature pattern having a rectangular shape. The photo masks are then formed. The semiconductor structure can be formed using the photo masks.
摘要翻译：提供一种形成具有矩形图案的光掩模的方法和使用该光掩模形成半导体结构的方法。用于形成光掩模的方法包括确定最小间距并识别具有小于最小间隔值的间隔的垂直导电特征图案。该方法还包括确定第一扩展方向和缩小第二方向，并且检查设计规则，以查看所标识的垂直导电特征图案中的每一个是否违反了设计规则。如果没有违反设计的规则，则所确定的垂直导电特征图案被替换为具有矩形形状的经修改的垂直导电特征图案。然后形成照相掩模。可以使用光掩膜形成半导体结构。

2. 发明授权

US07404167B2 Method for improving design window 有权
标题翻译：改善设计窗口的方法
公开(公告)号：US07404167B2
公开(公告)日：2008-07-22
申请号：US11320513
申请日：2005-12-27
申请人： Harry Chuang , Kong-Beng Thei , Chih-Tsung Yao , Heng-Kai Liu , Ming-Jer Chiu , Chien-Wen Chen
发明人： Harry Chuang , Kong-Beng Thei , Chih-Tsung Yao , Heng-Kai Liu , Ming-Jer Chiu , Chien-Wen Chen
IPC分类号： G06F17/50 , G06F19/00 , G03F1/00 , G21K5/00
CPC分类号： H01L23/481 , G03F1/144 , G03F1/36 , H01L21/31144 , H01L21/76807 , H01L21/76816 , H01L2924/0002 , H01L2924/00
摘要： A method of forming photo masks having rectangular patterns and a method for forming a semiconductor structure using the photo masks is provided. The method for forming the photo masks includes determining a minimum spacing and identifying vertical conductive feature patterns having a spacing less than the minimum spacing value. The method further includes determining a first direction to expand and a second direction to shrink, and checking against design rules to see if the design rules are violated for each of the vertical conductive feature patterns identified. If designed rules are not violated, the identified vertical conductive feature pattern is replaced with a revised vertical conductive feature pattern having a rectangular shape. The photo masks are then formed. The semiconductor structure can be formed using the photo masks.
摘要翻译：提供一种形成具有矩形图案的光掩模的方法和使用该光掩模形成半导体结构的方法。用于形成光掩模的方法包括确定最小间距并识别具有小于最小间隔值的间隔的垂直导电特征图案。该方法还包括确定第一扩展方向和缩小第二方向，并且检查设计规则，以查看所标识的每个垂直导电特征图案是否违反了设计规则。如果没有违反设计的规则，则所确定的垂直导电特征图案被替换为具有矩形形状的经修改的垂直导电特征图案。然后形成照相掩模。可以使用光掩膜形成半导体结构。

3. 发明授权

US08826207B2 Method of generating technology file for integrated circuit design tools 有权
标题翻译：集成电路设计工具生成技术文件的方法
公开(公告)号：US08826207B2
公开(公告)日：2014-09-02
申请号：US11966570
申请日：2007-12-28
申请人： Cliff Hou , Gwan Sin Chang , Cheng-Hung Yeh , Chih-Tsung Yao
发明人： Cliff Hou , Gwan Sin Chang , Cheng-Hung Yeh , Chih-Tsung Yao
IPC分类号： G06F9/455 , G06F17/50
CPC分类号： G06F17/5036
摘要： A method and system for extracting the parasitic capacitance in an IC and generating a technology file for at least one or more IC design tools are provided. Parasitic extraction using the preferred method can significantly reduce field solver computational intensity and save technology file preparation cycle time. The network-based technology file generation system enables circuit designers to obtain a desired technology file in a timely manner. The common feature of the various embodiments includes identifying common conductive feature patterns for a given technology generation. Capacitance models created from the identified patterns are used to assemble the required technology files for IC design projects using different technology node and different process flows.
摘要翻译：提供了一种用于提取IC中的寄生电容并为至少一个或多个IC设计工具生成技术文件的方法和系统。使用优选方法的寄生提取可以显着降低场求解器的计算强度，节省技术文件准备周期时间。基于网络的技术文件生成系统使得电路设计人员能够及时获得所需的技术文件。各种实施例的共同特征包括识别给定技术生成的共同导电特征图案。使用识别的模式创建的电容模型用于使用不同的技术节点和不同的工艺流程，为IC设计项目组装所需的技术文件。

4. 发明申请

US20060188824A1 Method for improving design window 有权
标题翻译：改善设计窗口的方法
公开(公告)号：US20060188824A1
公开(公告)日：2006-08-24
申请号：US11320513
申请日：2005-12-27
申请人： Harry Chuang , Kong-Beng Thei , Chih-Tsung Yao , Heng-Kai Liu , Ming-Jer Chiu , Chien-Wen Chen
发明人： Harry Chuang , Kong-Beng Thei , Chih-Tsung Yao , Heng-Kai Liu , Ming-Jer Chiu , Chien-Wen Chen
IPC分类号： G03F7/00
CPC分类号： H01L23/481 , G03F1/144 , G03F1/36 , H01L21/31144 , H01L21/76807 , H01L21/76816 , H01L2924/0002 , H01L2924/00
摘要： A method of forming photo masks having rectangular patterns and a method for forming a semiconductor structure using the photo masks is provided. The method for forming the photo masks includes determining a minimum spacing and identifying vertical conductive feature patterns having a spacing less than the minimum spacing value. The method further includes determining a first direction to expand and a second direction to shrink, and checking against design rules to see if the design rules are violated for each of the vertical conductive feature patterns identified. If designed rules are not violated, the identified vertical conductive feature pattern is replaced with a revised vertical conductive feature pattern having a rectangular shape. The photo masks are then formed. The semiconductor structure can be formed using the photo masks.
摘要翻译：提供一种形成具有矩形图案的光掩模的方法和使用该光掩模形成半导体结构的方法。用于形成光掩模的方法包括确定最小间距并识别具有小于最小间隔值的间隔的垂直导电特征图案。该方法还包括确定第一扩展方向和缩小第二方向，并且检查设计规则，以查看所标识的每个垂直导电特征图案是否违反了设计规则。如果没有违反设计的规则，则所确定的垂直导电特征图案被替换为具有矩形形状的经修改的垂直导电特征图案。然后形成照相掩模。可以使用光掩膜形成半导体结构。

5. 发明申请

US20080263492A1 3-Dimensional Device Design Layout 有权
标题翻译：三维设备设计布局
公开(公告)号：US20080263492A1
公开(公告)日：2008-10-23
申请号：US11833119
申请日：2007-08-02
申请人： Harry Chuang , Kong-Beng Thei , Mong Song Liang , Sheng-Chen Chung , Chih-Tsung Yao , Jung-Hui Kao , Chung Long Cheng , Gary Shen , Gwan Sin Chang
发明人： Harry Chuang , Kong-Beng Thei , Mong Song Liang , Sheng-Chen Chung , Chih-Tsung Yao , Jung-Hui Kao , Chung Long Cheng , Gary Shen , Gwan Sin Chang
IPC分类号： G06F17/50
CPC分类号： H01L29/785 , H01L21/76807 , H01L21/76895 , H01L21/76897 , H01L21/823431 , H01L21/823437 , H01L21/823475 , H01L29/41791 , H01L29/66795 , H01L2029/7858
摘要： A method for defining a layout of 3-D devices, such as a finFET, is provided. The method includes determining an area required by a desired 3-D device and designing a circuit using planar devices having an equivalent area. The planar device corresponding to the desired 3-D device is used to layout a circuit design, thereby allowing circuit and layout designers to work at a higher level without the need to specify each individual fin or 3-D structure. Thereafter, the planar design may be converted to a 3-D design by replacing planar active areas with 3-D devices occupying an equivalent area.
摘要翻译：提供了一种用于定义诸如finFET的3-D器件的布局的方法。该方法包括确定期望的3-D设备所需的区域和使用具有等效面积的平面设备来设计电路。对应于期望的3-D器件的平面器件用于布局电路设计，从而允许电路和布局设计者在更高级别工作，而不需要指定每个单独的鳍或3-D结构。此后，平面设计可以通过用占据等同面积的3-D器件代替平面有源区域而被转换成3维设计。

6. 发明授权

US08981562B2 Wiring layout having differently shaped vias 有权
标题翻译：接线布局具有不同形状的通孔
公开(公告)号：US08981562B2
公开(公告)日：2015-03-17
申请号：US12134381
申请日：2008-06-06
申请人： Harry Chuang , Kong-Beng Thei , Chih-Tsung Yao , Heng-Kai Liu , Ming-Jer Chiu , Chien-Wen Chen
发明人： Harry Chuang , Kong-Beng Thei , Chih-Tsung Yao , Heng-Kai Liu , Ming-Jer Chiu , Chien-Wen Chen
IPC分类号： H01L21/00 , G03F1/00 , G03F1/36 , H01L21/768 , H01L21/311
CPC分类号： H01L23/481 , G03F1/144 , G03F1/36 , H01L21/31144 , H01L21/76807 , H01L21/76816 , H01L2924/0002 , H01L2924/00
摘要： A method of forming photo masks having rectangular patterns and a method for forming a semiconductor structure using the photo masks is provided. The method for forming the photo masks includes determining a minimum spacing and identifying vertical conductive feature patterns having a spacing less than the minimum spacing value. The method further includes determining a first direction to expand and a second direction to shrink, and checking against design rules to see if the design rules are violated for each of the vertical conductive feature patterns identified. If designed rules are not violated, the identified vertical conductive feature pattern is replaced with a revised vertical conductive feature pattern having a rectangular shape. The photo masks are then formed. The semiconductor structure can be formed using the photo masks.
摘要翻译：提供一种形成具有矩形图案的光掩模的方法和使用该光掩模形成半导体结构的方法。用于形成光掩模的方法包括确定最小间距并识别具有小于最小间隔值的间隔的垂直导电特征图案。该方法还包括确定第一扩展方向和缩小第二方向，并且检查设计规则，以查看所标识的每个垂直导电特征图案是否违反了设计规则。如果没有违反设计的规则，则所确定的垂直导电特征图案被替换为具有矩形形状的经修改的垂直导电特征图案。然后形成照相掩模。可以使用光掩膜形成半导体结构。

7. 发明申请

US20090077507A1 Method of Generating Technology File for Integrated Circuit Design Tools 有权
标题翻译：集成电路设计工具生成技术文件的方法
公开(公告)号：US20090077507A1
公开(公告)日：2009-03-19
申请号：US11966570
申请日：2007-12-28
申请人： Cliff Hou , Gwan Sin Chang , Cheng-Hung Yeh , Chih-Tsung Yao
发明人： Cliff Hou , Gwan Sin Chang , Cheng-Hung Yeh , Chih-Tsung Yao
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： A method and system for extracting the parasitic capacitance in an IC and generating a technology file for at least one or more IC design tools are provided. Parasitic extraction using the preferred method can significantly reduce field solver computational intensity and save technology file preparation cycle time. The network-based technology file generation system enables circuit designers to obtain a desired technology file in a timely manner. The common feature of the various embodiments includes identifying common conductive feature patterns for a given technology generation. Capacitance models created from the identified patterns are used to assemble the required technology files for IC design projects using different technology node and different process flows.
摘要翻译：提供了一种用于提取IC中的寄生电容并为至少一个或多个IC设计工具生成技术文件的方法和系统。使用优选方法的寄生提取可以显着降低场求解器的计算强度，节省技术文件准备周期时间。基于网络的技术文件生成系统使得电路设计人员能够及时获得所需的技术文件。各种实施例的共同特征包括识别给定技术生成的共同导电特征图案。使用识别的模式创建的电容模型用于使用不同的技术节点和不同的工艺流程，为IC设计项目组装所需的技术文件。

8. 发明授权

US08286114B2 3-dimensional device design layout 有权
标题翻译：三维设备设计布局
公开(公告)号：US08286114B2
公开(公告)日：2012-10-09
申请号：US11833119
申请日：2007-08-02
申请人： Harry Chuang , Kong-Beng Thei , Mong Song Liang , Sheng-Chen Chung , Chih-Tsung Yao , Jung-Hui Kao , Chung Long Cheng , Gary Shen , Gwan Sin Chang
发明人： Harry Chuang , Kong-Beng Thei , Mong Song Liang , Sheng-Chen Chung , Chih-Tsung Yao , Jung-Hui Kao , Chung Long Cheng , Gary Shen , Gwan Sin Chang
IPC分类号： G06F17/50
CPC分类号： H01L29/785 , H01L21/76807 , H01L21/76895 , H01L21/76897 , H01L21/823431 , H01L21/823437 , H01L21/823475 , H01L29/41791 , H01L29/66795 , H01L2029/7858
摘要： A method for defining a layout of 3-D devices, such as a finFET, is provided. The method includes determining an area required by a desired 3-D device and designing a circuit using planar devices having an equivalent area. The planar device corresponding to the desired 3-D device is used to layout a circuit design, thereby allowing circuit and layout designers to work at a higher level without the need to specify each individual fin or 3-D structure. Thereafter, the planar design may be converted to a 3-D design by replacing planar active areas with 3-D devices occupying an equivalent area.
摘要翻译：提供了一种用于定义诸如finFET的3-D器件的布局的方法。该方法包括确定期望的3-D设备所需的区域和使用具有等效面积的平面设备来设计电路。对应于期望的3-D器件的平面器件用于布局电路设计，从而允许电路和布局设计者在更高级别工作，而不需要指定每个单独的鳍或3-D结构。此后，平面设计可以通过用占据等同面积的3-D器件代替平面有源区域而被转换成3维设计。

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