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21. 发明申请

US20100230762A1 INTEGRATED CIRCUIT USING FINFETS AND HAVING A STATIC RANDOM ACCESS MEMORY (SRAM) 有权
标题翻译：使用FINFET并具有静态随机存取存储器（SRAM）的集成电路
公开(公告)号：US20100230762A1
公开(公告)日：2010-09-16
申请号：US12785829
申请日：2010-05-24
申请人： James D. Burnett , Leo Mathew , Byoung W. Min
发明人： James D. Burnett , Leo Mathew , Byoung W. Min
IPC分类号： H01L29/78 , H01L21/8244
CPC分类号： H01L27/1108 , H01L27/1203 , H01L27/1207 , H01L27/1211 , H01L29/045 , H01L29/66795 , H01L29/785
摘要： An integrated circuit includes a logic circuit and a memory cell. The logic circuit includes a P-channel transistor, and the memory cell includes a P-channel transistor. The P-channel transistor of the logic circuit includes a channel region. The channel region has a portion located along a sidewall of a semiconductor structure having a surface orientation of (110). The portion of the channel region located along the sidewall has a first vertical dimension that is greater than a vertical dimension of any portion of the channel region of the P-channel transistor of the memory cell located along a sidewall of a semiconductor structure having a surface orientation of (110).
摘要翻译：集成电路包括逻辑电路和存储单元。逻辑电路包括P沟道晶体管，并且存储单元包括P沟道晶体管。逻辑电路的P沟道晶体管包括沟道区。沟道区具有位于具有（110）表面取向的半导体结构的侧壁的部分。位于沿着侧壁的通道区域的部分具有第一垂直尺寸，其大于沿着具有表面的半导体结构的侧壁的存储单元的P沟道晶体管的沟道区的任何部分的垂直尺寸（110）的方向。

22. 发明授权

US07648884B2 Semiconductor device with integrated resistive element and method of making 失效
标题翻译：具有集成电阻元件的半导体器件及其制造方法
公开(公告)号：US07648884B2
公开(公告)日：2010-01-19
申请号：US11680199
申请日：2007-02-28
申请人： Byoung W. Min , James K. Schaeffer , David C. Sing
发明人： Byoung W. Min , James K. Schaeffer , David C. Sing
IPC分类号： H01L21/20
CPC分类号： H01L27/0629 , H01L28/20
摘要： A resistive device (44) and a transistor (42) are formed. Each uses a portion of a metal layer (18) that is formed at the same time and thus additional process steps are avoided to remove the metal from the resistive device. The metal used in the resistive device is selectively treated to increase the resistance in the resistive device. A polycrystalline semiconductor material layer (34) overlies the metal layer in the resistive device. The combination of these layers provides the resistive device. In one form the metal is treated after formation of the polycrystalline semiconductor material layer. In one form the metal treatment involves an implant of a species, such as oxygen, to increase the resistivity of the metal. Various transistor structures are formed using the untreated portion of the metal layer as a control electrode.
摘要翻译：形成电阻器件（44）和晶体管（42）。每个都使用同时形成的金属层（18）的一部分，因此避免了额外的工艺步骤以从电阻器件去除金属。选择性地处理在电阻器件中使用的金属以增加电阻器件中的电阻。多晶半导体材料层（34）覆盖电阻器件中的金属层。这些层的组合提供了电阻装置。在一种形式中，在形成多晶半导体材料层之后处理金属。在一种形式中，金属处理包括物质（例如氧）的植入物以增加金属的电阻率。使用金属层的未处理部分作为控制电极形成各种晶体管结构。

23. 发明申请

US20090039418A1 MULTIPLE DEVICE TYPES INCLUDING AN INVERTED-T CHANNEL TRANSISTOR AND METHOD THEREFOR 有权
标题翻译：多种器件类型，包括反相通道晶体管及其方法
公开(公告)号：US20090039418A1
公开(公告)日：2009-02-12
申请号：US12251746
申请日：2008-10-15
申请人： Byoung W. Min , James D. Burnett , Leo Mathew
发明人： Byoung W. Min , James D. Burnett , Leo Mathew
IPC分类号： H01L29/78
CPC分类号： H01L27/1104 , H01L21/823431 , H01L27/11 , H01L29/66795 , H01L29/785
摘要： A method for making a semiconductor device is provided. The method includes forming a first transistor with a vertical active region and a horizontal active region extending on both sides of the vertical active region. The method further includes forming a second transistor with a vertical active region. The method further includes forming a third transistor with a vertical active region and a horizontal active region extending on only one side of the vertical active region.
摘要翻译：提供一种制造半导体器件的方法。该方法包括形成具有在垂直有源区两侧延伸的垂直有源区和水平有源区的第一晶体管。该方法还包括形成具有垂直有源区的第二晶体管。该方法还包括形成具有垂直有源区和仅在垂直有源区的一侧上延伸的水平有源区的第三晶体管。

24. 发明授权

US07452768B2 Multiple device types including an inverted-T channel transistor and method therefor 有权
标题翻译：多种器件类型，包括反向T沟道晶体管及其方法
公开(公告)号：US07452768B2
公开(公告)日：2008-11-18
申请号：US11257972
申请日：2005-10-25
申请人： Byoung W. Min , James D. Burnett , Leo Mathew
发明人： Byoung W. Min , James D. Burnett , Leo Mathew
IPC分类号： H01L21/8234
CPC分类号： H01L27/1104 , H01L21/823431 , H01L27/11 , H01L29/66795 , H01L29/785
摘要： A method for making a semiconductor device is provided. The method includes forming a first transistor with a vertical active region and a horizontal active region extending on both sides of the vertical active region. The method further includes forming a second transistor with a vertical active region. The method further includes forming a third transistor with a vertical active region and a horizontal active region extending on only one side of the vertical active region.
摘要翻译：提供一种制造半导体器件的方法。该方法包括形成具有在垂直有源区两侧延伸的垂直有源区和水平有源区的第一晶体管。该方法还包括形成具有垂直有源区的第二晶体管。该方法还包括形成具有垂直有源区和仅在垂直有源区的一侧上延伸的水平有源区的第三晶体管。

25. 发明授权

US07186596B2 Vertical diode formation in SOI application 有权
标题翻译： SOI应用中的垂直二极管形成
公开(公告)号：US07186596B2
公开(公告)日：2007-03-06
申请号：US11158022
申请日：2005-06-21
申请人： Byoung W. Min , Laegu Kang , Michael Khazhinsky
发明人： Byoung W. Min , Laegu Kang , Michael Khazhinsky
IPC分类号： H01L29/72
CPC分类号： H01L29/8611 , H01L27/0255 , H01L29/66136 , H01L29/868
摘要： A method for making a semiconductor device is provided. The method comprises (a) providing a semiconductor stack comprising a semiconductor substrate (203), a first semiconductor layer (205), and a first dielectric layer (207) disposed between the substrate and the first semiconductor layer; (b) forming a first trench in the first dielectric layer which exposes a portion of the substrate; (c) forming a first doped region (209) in the exposed portion of the substrate; and (d) forming anode (211) and cathode (213) regions in the first implant region.
摘要翻译：提供一种制造半导体器件的方法。该方法包括（a）提供包括半导体衬底（203），第一半导体层（205）和设置在衬底和第一半导体层之间的第一电介质层（207）的半导体堆叠; （b）在所述第一电介质层中形成暴露所述衬底的一部分的第一沟槽; （c）在所述衬底的暴露部分中形成第一掺杂区域（209）; 和（d）在第一注入区域中形成阳极（211）和阴极（213）区域。

26. 发明授权

US07122421B2 Semiconductor device including a transistor and a capacitor having an aligned transistor and capacitive element 有权
标题翻译：包括具有对准的晶体管和电容元件的晶体管和电容器的半导体器件
公开(公告)号：US07122421B2
公开(公告)日：2006-10-17
申请号：US11098070
申请日：2005-04-04
申请人： Hector Sanchez , Michael A. Mendicino , Byoung W. Min , Kathleen C. Yu
发明人： Hector Sanchez , Michael A. Mendicino , Byoung W. Min , Kathleen C. Yu
IPC分类号： H01L21/8242 , H01L21/20 , H01L21/44 , H01L21/4763
CPC分类号： H01L27/0688 , H01L21/76838 , H01L21/76898 , H01L21/84 , H01L23/481 , H01L23/5223 , H01L27/1203 , H01L28/40 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor (10) has an active device, such as a transistor, with a directly underlying passive device, such as a capacitor (75, 77, 79), that are connected by a via or conductive region (52) and interconnect (68, 99). The via or conductive region (52) contacts a bottom surface of a diffusion or source region (22) of the transistor and contacts a first (75) of the capacitor electrodes. A laterally positioned vertical via (32, 54, 68) and interconnect (99) contacts a second (79) of the capacitor electrodes. A metal interconnect or conductive material (68) may be used as a power plane that saves circuit area by implementing the power plane underneath the transistor rather than adjacent the transistor.
摘要翻译：半导体（10）具有诸如晶体管的有源器件，其具有通过通孔或导电区域（52）和互连（68）连接的直接下伏的无源器件，例如电容器（75,77,79），99）。通孔或导电区域（52）接触晶体管的扩散或源极区域（22）的底表面并与第一（75）电容器电极接触。横向定位的垂直通孔（32,54,68）和互连件（99）接触电容器电极的第二（79）。金属互连或导电材料（68）可以用作通过在晶体管下面实现功率平面而不是与晶体管相邻来节省电路面积的功率面。

27. 发明授权

US07041576B2 Separately strained N-channel and P-channel transistors 失效
标题翻译：单独应变的N沟道和P沟道晶体管
公开(公告)号：US07041576B2
公开(公告)日：2006-05-09
申请号：US10856581
申请日：2004-05-28
申请人： Scott K. Pozder , Salih M. Celik , Byoung W. Min , Vance H. Adams
发明人： Scott K. Pozder , Salih M. Celik , Byoung W. Min , Vance H. Adams
IPC分类号： H01L21/30
CPC分类号： H01L27/0688 , H01L21/8221 , H01L24/29 , H01L24/83 , H01L27/1203 , H01L29/7842 , H01L2224/83191 , H01L2224/8385 , H01L2924/01005 , H01L2924/01015 , H01L2924/01032 , H01L2924/01033 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/04941 , H01L2924/07802 , H01L2924/14 , H01L2924/19043
摘要： An integrated circuit with a first plurality of transistors formed on a first wafer and second plurality of transistors formed on a second wafer. At least a substantial majority of the transistor of the first transistor are of a first conductivity type and at least a substantial majority of the transistors of the second plurality are of a second conductivity type. After wafers are bonded together, a portion of the second wafer is removed wherein the strain of the channels of the second plurality of transistors is more compressive than the strain of the channels of the first plurality of transistors.
摘要翻译：一种集成电路，其具有形成在第一晶片上的第一多个晶体管和形成在第二晶片上的第二多个晶体管。第一晶体管的至少绝大部分晶体管是第一导电类型，并且第二多晶体管的至少绝大部分晶体管是第二导电类型。在将晶片接合在一起之后，去除第二晶片的一部分，其中第二多个晶体管的通道的应变比第一多个晶体管的通道的应变更为压缩。

28. 发明授权

US09082650B2 Integrated split gate non-volatile memory cell and logic structure 有权
标题翻译：集成分离门非易失性存储单元和逻辑结构
公开(公告)号：US09082650B2
公开(公告)日：2015-07-14
申请号：US13971987
申请日：2013-08-21
申请人： Asanga H. Perera , Cheong Min Hong , Sung-Taeg Kang , Byoung W. Min , Jane A. Yater
发明人： Asanga H. Perera , Cheong Min Hong , Sung-Taeg Kang , Byoung W. Min , Jane A. Yater
IPC分类号： H01L21/336 , H01L27/115 , H01L29/66 , H01L21/28 , H01L29/423
CPC分类号： H01L27/11517 , H01L21/28273 , H01L27/11534 , H01L29/42332 , H01L29/66545 , H01L29/66825
摘要： A method of making a semiconductor structure includes forming a select gate and a charge storage layer in an NVM region. A spacer select gate is formed by depositing a conformal layer followed by an etch back. A patterned etch results in leaving a portion of the charge storage layer over the select gate. A dummy gate structure formed in a logic region has a dummy gate surrounded by an insulating layer. Performing chemical polishing results in the top surface of the charge storage layer being coplanar with top surface of the dummy gate structure. Replacing a portion of the dummy gate structure with a metal logic gate which includes a further chemical mechanical polishing results in the top surface of the charge storage layer being coplanar with the metal logic gate.
摘要翻译：制造半导体结构的方法包括在NVM区域中形成选择栅极和电荷存储层。间隔选择栅极通过沉积保形层，随后进行回蚀而形成。图案化蚀刻导致将电荷存储层的一部分留在选择栅上。形成在逻辑区域中的虚拟栅极结构具有由绝缘层包围的虚拟栅极。执行化学抛光导致电荷存储层的顶表面与虚拟栅极结构的顶表面共面。用包括另外的化学机械抛光的金属逻辑门来替代虚拟栅极结构的一部分导致电荷存储层的顶表面与金属逻辑门共面。

29. 发明授权

US09059006B2 Replacement-gate-compatible programmable electrical antifuse 有权
标题翻译：替换门兼容可编程电气反熔丝
公开(公告)号：US09059006B2
公开(公告)日：2015-06-16
申请号：US13523120
申请日：2012-06-14
申请人： Satya N. Chakravarti , Dechao Guo , Chuck T. Le , Byoung W. Min , Thekkemadathil V. Rajeevakumar , Keith Kwong Hon Wong
发明人： Satya N. Chakravarti , Dechao Guo , Chuck T. Le , Byoung W. Min , Thekkemadathil V. Rajeevakumar , Keith Kwong Hon Wong
IPC分类号： G01R27/08 , H01L23/52 , H01L29/10 , H01L27/06 , H01L23/525 , H01L27/112 , H01L29/66 , H01L29/49 , H01L29/78
CPC分类号： H01L27/0617 , H01L23/5252 , H01L27/112 , H01L27/11206 , H01L29/4966 , H01L29/66545 , H01L29/7833 , H01L2924/0002 , H01L2924/00
摘要： After planarization of a gate level dielectric layer, a dummy structure is removed to form a recess. A first conductive material layer and an amorphous metal oxide are deposited into the recess area. A second conduct material layer fills the recess. After planarization, an electrical antifuse is formed within the filled recess area, which includes a first conductive material portion, an amorphous metal oxide portion, and a second conductive material portion. To program the electrical antifuse, current is passed between the two terminals in the pair of the conductive contacts to transform the amorphous metal oxide portion into a crystallized metal oxide portion, which has a lower resistance. A sensing circuit determines whether the metal oxide portion is in an amorphous state (high resistance state) or in a crystalline state (low resistance state).
摘要翻译：在栅极级介电层平坦化之后，去除虚拟结构以形成凹陷。第一导电材料层和无定形金属氧化物沉积到凹陷区域中。第二导电材料层填充凹部。在平坦化之后，在填充的凹陷区域内形成电反熔丝，其包括第一导电材料部分，非晶金属氧化物部分和第二导电材料部分。为了编程电反熔丝，电流在一对导电触点中的两个端子之间通过，以将非晶金属氧化物部分转变成具有较低电阻的结晶化金属氧化物部分。感测电路确定金属氧化物部分是非晶态（高电阻状态）还是结晶态（低电阻状态）。

30. 发明授权

US08237457B2 Replacement-gate-compatible programmable electrical antifuse 有权
标题翻译：替换门兼容可编程电气反熔丝
公开(公告)号：US08237457B2
公开(公告)日：2012-08-07
申请号：US12503116
申请日：2009-07-15
申请人： Satya N. Chakravarti , Dechao Guo , Chuck T. Le , Byoung W. Min , Thekkemadathil V. Rajeevakumar , Keith Kwong Hon Wong
发明人： Satya N. Chakravarti , Dechao Guo , Chuck T. Le , Byoung W. Min , Thekkemadathil V. Rajeevakumar , Keith Kwong Hon Wong
IPC分类号： G01R27/08 , H01L23/52 , H01L29/10
CPC分类号： H01L27/0617 , H01L23/5252 , H01L27/112 , H01L27/11206 , H01L29/4966 , H01L29/66545 , H01L29/7833 , H01L2924/0002 , H01L2924/00
摘要： After planarization of a gate level dielectric layer, a dummy structure is removed to form a recess. A first conductive material layer and an amorphous metal oxide are deposited into the recess area. A second conduct material layer fills the recess. After planarization, an electrical antifuse is formed within the filled recess area, which includes a first conductive material portion, an amorphous metal oxide portion, and a second conductive material portion. To program the electrical antifuse, current is passed between the two terminals in the pair of the conductive contacts to transform the amorphous metal oxide portion into a crystallized metal oxide portion, which has a lower resistance. A sensing circuit determines whether the metal oxide portion is in an amorphous state (high resistance state) or in a crystalline state (low resistance state).
摘要翻译：在栅极级介电层平坦化之后，去除虚拟结构以形成凹陷。第一导电材料层和无定形金属氧化物沉积到凹陷区域中。第二导电材料层填充凹部。在平坦化之后，在填充的凹陷区域内形成电反熔丝，其包括第一导电材料部分，非晶金属氧化物部分和第二导电材料部分。为了编程电反熔丝，电流在一对导电触头中的两个端子之间通过，以将非晶金属氧化物部分转变成具有较低电阻的结晶化金属氧化物部分。感测电路确定金属氧化物部分是非晶态（高电阻状态）还是结晶态（低电阻状态）。

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