专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

21. 发明授权

US07598596B2 Methods and apparatus for a dual-metal magnetic shield structure 有权
标题翻译：双金属磁屏蔽结构的方法和装置
公开(公告)号：US07598596B2
公开(公告)日：2009-10-06
申请号：US11602639
申请日：2006-11-21
申请人： Jaynal A. Molla , Gregory W. Grynkewich , Eric J. Salter
发明人： Jaynal A. Molla , Gregory W. Grynkewich , Eric J. Salter
IPC分类号： H01L23/552 , H01L21/00 , H01L21/8246
CPC分类号： H01L23/552 , G11C11/16 , H01L43/08 , H01L2924/0002 , H01L2924/12044 , H01L2924/00
摘要： A shield structure for shielding an electromagnetic-field-susceptible region of a semiconductor component (e.g., a magnetoresistive random access memory, or “MRAM”) includes a stress-relief layer (e.g., electroplated Ni) formed over the semiconductor device in a shield region substantially corresponding to the electromagnetic-field-susceptible region, and a magnetic shield layer (e.g., an electroplated PERMALLOY or MUMETAL layer) mechanically coupled to the stress-relief layer within the shield region, wherein the magnetic shield layer has a stress condition that is substantially opposite of that of the stress-relief layer.
摘要翻译：用于屏蔽半导体部件（例如，磁阻随机存取存储器或“MRAM”）的电磁场敏感区域的屏蔽结构包括形成在屏蔽层上的半导体器件上的应力消除层（例如，电镀Ni）基本上对应于电磁场敏感区域的磁屏蔽层（例如，电镀的PERMALLOY或MUMETAL层），其机械耦合到屏蔽区域内的应力消除层，其中磁屏蔽层具有应力条件，与应力消除层的基本相反。

22. 发明授权

US07444738B2 Method for tunnel junction sensor with magnetic cladding 失效
标题翻译：具有磁性包层的隧道结传感器的方法
公开(公告)号：US07444738B2
公开(公告)日：2008-11-04
申请号：US11192517
申请日：2005-07-29
申请人： Young Sir Chung , Robert W. Baird , Gregory W. Grynkewich
发明人： Young Sir Chung , Robert W. Baird , Gregory W. Grynkewich
IPC分类号： G11B5/127 , G11B5/33
CPC分类号： G01R33/06 , H01L43/12 , Y10T29/49032 , Y10T29/49034 , Y10T29/49036 , Y10T29/49039 , Y10T29/49041 , Y10T29/49043 , Y10T29/49044
摘要： Methods and apparatus are provided for sensing physical parameters. The apparatus comprises a magnetic tunnel junction (MTJ) and a magnetic field source whose magnetic field overlaps the MTJ and whose proximity to the MTJ varies in response to an input to the sensor. A magnetic shield is provided at least on a face of the MFS away from the MTJ. The MTJ comprises first and second magnetic electrodes separated by a dielectric configured to permit significant tunneling conduction therebetween. The first magnetic region has its spin axis pinned and the second magnetic electrode has its spin axis free. The magnetic field source is oriented closer to the second magnetic electrode than the first magnetic electrode. The overall sensor dynamic range is extended by providing multiple electrically coupled sensors receiving the same input but with different individual response curves and desirably but not essentially formed on the same substrate.
摘要翻译：提供了用于感测物理参数的方法和装置。该装置包括磁隧道结（MTJ）和磁场源，其磁场与MTJ重叠，并且其与MTJ的接近度响应于对传感器的输入而变化。至少在远离MTJ的MFS的面上设有磁屏蔽。 MTJ包括由电介质隔开的第一和第二磁极，其被配置为允许它们之间的显着的隧穿传导。第一磁性区域的自旋轴被固定，第二磁极的自由轴自由。磁场源比第一磁极更靠近第二磁极。通过提供多个电耦合传感器来接收相同的输入但是具有不同的单个响应曲线并且期望地但不是基本上形成在相同的基板上来扩展总传感器动态范围。

23. 发明授权

US07324369B2 MRAM embedded smart power integrated circuits 有权
标题翻译： MRAM嵌入式智能电源集成电路
公开(公告)号：US07324369B2
公开(公告)日：2008-01-29
申请号：US11170874
申请日：2005-06-30
申请人： Young Sir Chung , Robert W. Baird , Mark A. Durlam , Gregory W. Grynkewich , Eric J. Salter
发明人： Young Sir Chung , Robert W. Baird , Mark A. Durlam , Gregory W. Grynkewich , Eric J. Salter
IPC分类号： G11C11/00
CPC分类号： G11C11/1659 , H01F10/3254
摘要： An integrated circuit device includes a magnetic random access memory (“MRAM”) architecture and a smart power integrated circuit architecture formed on the same substrate using the same fabrication process technology. The fabrication process technology is a modular process having a front end process and a back end process. In the example embodiment, the smart power architecture includes a power circuit component, a digital logic component, and an analog control component formed by the front end process, and a sensor architecture formed by the back end process. The MRAM architecture includes an MRAM circuit component formed by the front end process and an MRAM cell array formed by the back end process. In one practical embodiment, the sensor architecture includes a sensor component that is formed from the same magnetic tunnel junction core material utilized by the MRAM cell array. The concurrent fabrication of the MRAM architecture and the smart power architecture facilitates an efficient and cost effective use of the physical space available over active circuit blocks of the substrate, resulting in three-dimensional integration.
摘要翻译：集成电路装置包括使用相同的制造工艺技术在同一衬底上形成的磁性随机存取存储器（“MRAM”）架构和智能电力集成电路架构。制造工艺技术是具有前端工艺和后端工艺的模块化工艺。在该示例性实施例中，智能功率架构包括由前端处理形成的电源电路部件，数字逻辑部件和模拟控制部件以及由后端处理形成的传感器架构。 MRAM架构包括由前端处理形成的MRAM电路部件和由后端处理形成的MRAM单元阵列。在一个实际实施例中，传感器架构包括由MRAM单元阵列使用的相同的磁性隧道结芯体材料形成的传感器部件。 MRAM架构和智能电源架构的并行制造有助于在衬底的有源电路块上可用的物理空间的有效和成本有效的使用，导致三维集成。

24. 发明授权

US06927072B2 Method of applying cladding material on conductive lines of MRAM devices 失效
公开(公告)号：US06927072B2
公开(公告)日：2005-08-09
申请号：US10093909
申请日：2002-03-08
申请人： Jaynal A. Molla , John D'Urso , Kelly Kyler , Bradley N. Engel , Gregory W. Grynkewich , Nicholas D. Rizzo
发明人： Jaynal A. Molla , John D'Urso , Kelly Kyler , Bradley N. Engel , Gregory W. Grynkewich , Nicholas D. Rizzo
IPC分类号： H01L27/105 , C25D5/12 , G11C11/15 , G11C11/16 , H01L21/00 , H01L21/4763 , H01L21/8246 , H01L27/22
CPC分类号： G11C11/16 , H01L27/222
摘要： A method of fabricating a cladding region for use in MRAM devices includes the formation of a conductive bit line proximate to a magnetoresistive memory device. The conductive bit line is immersed in a first bath containing dissolved ions of a first conductive material for a time sufficient to displacement plate a first barrier layer on the conductive line. The first barrier layer is then immersed in an electroless plating bath to form a flux concentrating layer on the first barrier layer. The flux concentrating layer is immersed in a second bath containing dissolved ions of a second conductive material for a time sufficient to displacement plate a second barrier layer on the flux concentrating layer.

25. 发明授权

US06812040B2 Method of fabricating a self-aligned via contact for a magnetic memory element 失效
标题翻译：制造用于磁存储元件的自对准通孔接点的方法
公开(公告)号：US06812040B2
公开(公告)日：2004-11-02
申请号：US10095816
申请日：2002-03-12
申请人： Kelly Kyler , Saied N. Tehrani , John J. D'urso , Gregory W. Grynkewich , Mark A. Durlam , Brian Butcher
发明人： Kelly Kyler , Saied N. Tehrani , John J. D'urso , Gregory W. Grynkewich , Mark A. Durlam , Brian Butcher
IPC分类号： H01L2100
CPC分类号： H01L43/12 , B82Y10/00
摘要： A method of fabricating a magnetoresistive random access memory device comprising the steps of providing a substrate, forming a conductive layer positioned on the substrate, forming a magnetoresistive random access memory device positioned on conductive layer, forming a metal cap on the magnetoresistive random access memory device, and electroless plating a bump metal layer on the metal cap. The bump metal layer acts as a self-aligned via for a bit line subsequently formed thereon.
摘要翻译：一种制造磁阻随机存取存储器件的方法，包括以下步骤：提供衬底，形成位于衬底上的导电层，形成位于导电层上的磁阻随机存取存储器件，在磁阻随机存取存储器件上形成金属帽并且在金属盖上化学镀覆凸块金属层。凸块金属层用作随后在其上形成的位线的自对准通孔。

26. 发明授权

US06784510B1 Magnetoresistive random access memory device structures 有权
标题翻译：磁阻随机存取存储器件结构
公开(公告)号：US06784510B1
公开(公告)日：2004-08-31
申请号：US10417851
申请日：2003-04-16
申请人： Gregory W. Grynkewich , Mark Deherrera , Mark A. Durlam , Clarence J. Tracy
发明人： Gregory W. Grynkewich , Mark Deherrera , Mark A. Durlam , Clarence J. Tracy
IPC分类号： H01L2900
CPC分类号： H01L27/228 , B82Y10/00
摘要： A method for fabricating an MRAM device structure includes providing a substrate on which is formed a first transistor and a second transistor. An operative memory element device is formed in electrical contact with the first transistor. At least a portion of a false memory element device is formed in electrical contact with the second transistor. A first dielectric layer is deposited overlying the at least a portion of a false memory element device and the operative memory element device. The first dielectric layer is etched to simultaneously form a first via to the at least a portion of a false memory element device and a second via to the operative memory element device. An electrically conductive interconnect layer is deposited so the electrically conductive interconnect layer extends from the at least a portion of a false memory element device to the operative memory element device.
摘要翻译：一种用于制造MRAM器件结构的方法包括提供其上形成有第一晶体管和第二晶体管的衬底。操作存储元件装置形成为与第一晶体管电接触。假存储元件器件的至少一部分形成为与第二晶体管电接触。第一介电层沉积在伪存储元件器件和操作存储元件器件的至少一部分上。蚀刻第一电介质层以同时形成第一通孔到伪存储元件器件的至少一部分，并将第二通孔形成到操作存储元件器件。沉积导电互连层，使得导电互连层从假存储元件器件的至少一部分延伸到可操作存储元件器件。

27. 发明授权

US07402529B2 Method of applying cladding material on conductive lines of MRAM devices 失效
标题翻译：在MRAM器件的导线上施加覆层材料的方法
公开(公告)号：US07402529B2
公开(公告)日：2008-07-22
申请号：US11139143
申请日：2005-05-26
申请人： Jaynal A. Molla , John D'Urso , Kelly Kyler , Bradley N. Engel , Gregory W. Grynkewich , Nicholas D. Rizzo
发明人： Jaynal A. Molla , John D'Urso , Kelly Kyler , Bradley N. Engel , Gregory W. Grynkewich , Nicholas D. Rizzo
IPC分类号： H01L21/302
CPC分类号： G11C11/16 , H01L27/222
摘要： A method of fabricating a cladding region for use in MRAM devices includes the formation of a conductive bit line proximate to a magnetoresistive memory device. The conductive bit line is immersed in a first bath containing dissolved ions of a first conductive material for a time sufficient to displacement plate a first barrier layer on the conductive line. The first barrier layer is then immersed in an electroless plating bath to form a flux concentrating layer on the first barrier layer. The flux concentrating layer is immersed in a second bath containing dissolved ions of a second conductive material for a time sufficient to displacement plate a second barrier layer on the flux concentrating layer.
摘要翻译：制造用于MRAM器件的包层区域的方法包括形成靠近磁阻存储器件的导电位线。将导电位线浸入包含第一导电材料的溶解离子的第一槽中足以使导电线上的第一阻挡层移位的时间。然后将第一阻挡层浸入无电镀浴中以在第一阻挡层上形成通量聚集层。将集流层浸入含有第二导电材料的溶解离子的第二槽中，持续足够的时间使得在集流层上移动第二阻挡层。

28. 发明申请

US20080116535A1 Methods and apparatus for a dual-metal magnetic shield structure 有权
标题翻译：双金属磁屏蔽结构的方法和装置
公开(公告)号：US20080116535A1
公开(公告)日：2008-05-22
申请号：US11602639
申请日：2006-11-21
申请人： Jaynal A. Molla , Gregory W. Grynkewich , Eric J. Salter
发明人： Jaynal A. Molla , Gregory W. Grynkewich , Eric J. Salter
IPC分类号： H01L29/82 , H01L23/544 , H01L21/60
CPC分类号： H01L23/552 , G11C11/16 , H01L43/08 , H01L2924/0002 , H01L2924/12044 , H01L2924/00
摘要： A shield structure for shielding an electromagnetic-field-susceptible region of a semiconductor component (e.g., a magnetoresistive random access memory, or “MRAM”) includes a stress-relief layer (e.g., electroplated Ni) formed over the semiconductor device in a shield region substantially corresponding to the electromagnetic-field-susceptible region, and a magnetic shield layer (e.g., an electroplated PERMALLOY or MUMETAL layer) mechanically coupled to the stress-relief layer within the shield region, wherein the magnetic shield layer has a stress condition that is substantially opposite of that of the stress-relief layer.
摘要翻译：用于屏蔽半导体部件（例如，磁阻随机存取存储器或“MRAM”）的电磁场敏感区域的屏蔽结构包括形成在屏蔽层上的半导体器件上的应力消除层（例如，电镀Ni）基本上对应于电磁场敏感区域的磁屏蔽层（例如，电镀的PERMALLOY或MUMETAL层），其机械耦合到屏蔽区域内的应力消除层，其中磁屏蔽层具有应力条件，与应力消除层的基本相反。

29. 发明授权

US06890770B2 Magnetoresistive random access memory device structures and methods for fabricating the same 有权
标题翻译：磁阻随机存取存储器件结构及其制造方法
公开(公告)号：US06890770B2
公开(公告)日：2005-05-10
申请号：US10885869
申请日：2004-07-06
申请人： Gregory W. Grynkewich , Mark Deherrera , Mark A. Durlam , Clarence J. Tracy
发明人： Gregory W. Grynkewich , Mark Deherrera , Mark A. Durlam , Clarence J. Tracy
IPC分类号： G11C20060101 , G11C8/02 , H01L21/00 , H01L21/8246 , H01L27/22 , H01L29/00 , H01L29/82
CPC分类号： H01L27/228 , B82Y10/00
摘要： A method for fabricating an MRAM device structure includes providing a substrate on which is formed a first transistor and a second transistor. An operative memory element device is formed in electrical contact with the first transistor. At least a portion of a false memory element device is formed in electrical contact with the second transistor. A first dielectric layer is deposited overlying the at least a portion of a false memory element device and the operative memory element device. The first dielectric layer is etched to simultaneously form a first via to the at least a portion of a false memory element device and a second via to the operative memory element device. An electrically conductive interconnect layer is deposited so the electrically conductive interconnect layer extends from the at least a portion of a false memory element device to the operative memory element device.
摘要翻译：一种用于制造MRAM器件结构的方法包括提供其上形成有第一晶体管和第二晶体管的衬底。操作存储元件装置形成为与第一晶体管电接触。假存储元件器件的至少一部分形成为与第二晶体管电接触。第一介电层沉积在伪存储元件器件和操作存储元件器件的至少一部分上。蚀刻第一电介质层以同时形成第一通孔到伪存储元件器件的至少一部分，并将第二通孔形成到操作存储元件器件。沉积导电互连层，使得导电互连层从假存储元件器件的至少一部分延伸到可操作存储元件器件。

30. 发明授权

US5814545A Semiconductor device having a phosphorus doped PECVD film and a method of manufacture 失效
标题翻译：具有磷掺杂PECVD膜的半导体器件及其制造方法
公开(公告)号：US5814545A
公开(公告)日：1998-09-29
申请号：US810037
申请日：1997-03-04
申请人： Kenneth M. Seddon , Gregory W. Grynkewich , Vida Ilderem , Heidi L. Denton , Jeffrey Pearse
发明人： Kenneth M. Seddon , Gregory W. Grynkewich , Vida Ilderem , Heidi L. Denton , Jeffrey Pearse
IPC分类号： H01L21/225 , H01L21/336 , H01L21/768
CPC分类号： H01L29/6659 , H01L21/2255 , H01L21/76801 , H01L29/665
摘要： Portions of a semiconductor device (10,30) are formed from a dielectric layer (16,38,46) which is deposited using a plasma enhanced chemical vapor deposition (PECVD) process which adds trimethylphosphite as a dopant source during the deposition. A first embodiment forms sidewall spacers (17) adjacent to a gate structure (14) and forms doped regions (19) under the sidewall spacers (17) by annealing the dielectric layer (16) and driving phosphorus into a substrate (11). A second embodiment uses the trimethylphosphite doped film as an interlevel dielectric layer (38) which can be planarized to provide a flat surface for the formation of metal interconnect lines. A third embodiment of the present invention uses the trimethylphosphite doped film as a passivation layer (46) which is deposited in a single step process and has a phosphorus concentration to getter mobile ions.
摘要翻译：半导体器件（10,30）的部分由介电层（16,38,46）形成，其使用等离子体增强化学气相沉积（PECVD）工艺沉积，其在沉积期间添加三甲基亚磷酸酯作为掺杂剂源。第一实施例形成与栅极结构（14）相邻的侧壁间隔物（17），并且通过退火介电层（16）并将磷驱动到衬底（11）中，在侧壁间隔物（17）下形成掺杂区域（19）。第二实施例使用掺杂了磷酸三甲酯的膜作为层间电介质层（38），其可被平坦化以提供用于形成金属互连线的平坦表面。本发明的第三个实施方案使用磷酸三亚甲酯作为钝化层（46），其被沉积在单步骤中并具有磷浓度以吸收移动离子。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式