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1. 发明授权

US07264985B2 Passive elements in MRAM embedded integrated circuits 有权
标题翻译： MRAM嵌入式集成电路中的被动元件
公开(公告)号：US07264985B2
公开(公告)日：2007-09-04
申请号：US11217146
申请日：2005-08-31
申请人： Young Sir Chung , Robert W. Baird , Mark A. Durlam , Gregory W. Grynkewich , Eric J. Salter
发明人： Young Sir Chung , Robert W. Baird , Mark A. Durlam , Gregory W. Grynkewich , Eric J. Salter
IPC分类号： H01L21/00
CPC分类号： H01L27/228
摘要： An integrated circuit device (300) comprises a substrate (301) and MRAM architecture (314) formed on the substrate (308). The MRAM architecture (314) includes a MRAM circuit (318) formed on the substrate (301); and a MRAM cell (316) coupled to and formed above the MRAM circuit (318). Additionally a passive device (320) is formed in conjunction with the MRAM cell (316). The passive device (320) can be one or more resistors and one or more capacitor. The concurrent fabrication of the MRAM architecture (314) and the passive device (320) facilitates an efficient and cost effective use of the physical space available over active circuit blocks of the substrate (404, 504), resulting in three-dimensional integration.
摘要翻译：集成电路器件（300）包括形成在衬底（308）上的衬底（301）和MRAM架构（314）。 MRAM架构（314）包括形成在基板（301）上的MRAM电路（318）。和耦合到并形成在MRAM电路（318）上方的MRAM单元（316）。另外，与MRAM单元（316）结合形成无源器件（320）。无源器件（320）可以是一个或多个电阻器和一个或多个电容器。 MRAM架构（314）和无源器件（320）的并发制造有助于在衬底（404,504）的有源电路块上可用的物理空间的有效和成本有效的使用，导致三维集成。

2. 发明授权

US07239543B2 Magnetic tunnel junction current sensors 有权
标题翻译：磁隧道结电流传感器
公开(公告)号：US07239543B2
公开(公告)日：2007-07-03
申请号：US11262053
申请日：2005-10-28
申请人： Young Sir Chung , Robert W. Baird , Mark A. Durlam , Gregory W. Grynkewich , Eric J. Salter , Jiang-Kai Zuo
发明人： Young Sir Chung , Robert W. Baird , Mark A. Durlam , Gregory W. Grynkewich , Eric J. Salter , Jiang-Kai Zuo
IPC分类号： G11C11/00
CPC分类号： G11C11/1675 , G11C11/1659 , G11C11/1673
摘要： An integrated circuit device includes an active circuit component and a current sensor. The active circuit component may be coupled between a first conductive layer and a second conductive layer, and is configured to produce a first current. The current sensor is disposed over the active circuit component. The current sensor may includes a Magnetic Tunnel Junction (“MTJ”) core disposed between the first conductive layer and the second conductive layer. The MTJ core is configured to sense the first current and produce a second current based on the first current sensed at the MTJ core.
摘要翻译：集成电路装置包括有源电路部件和电流传感器。有源电路组件可以耦合在第一导电层和第二导电层之间，并且被配置为产生第一电流。电流传感器设置在有源电路部件上。电流传感器可以包括设置在第一导电层和第二导电层之间的磁隧道结（“MTJ”）芯。 MTJ内核被配置为基于在MTJ核心处感测到的第一电流来感测第一电流并产生第二电流。

3. 发明授权

US07444738B2 Method for tunnel junction sensor with magnetic cladding 失效
标题翻译：具有磁性包层的隧道结传感器的方法
公开(公告)号：US07444738B2
公开(公告)日：2008-11-04
申请号：US11192517
申请日：2005-07-29
申请人： Young Sir Chung , Robert W. Baird , Gregory W. Grynkewich
发明人： Young Sir Chung , Robert W. Baird , Gregory W. Grynkewich
IPC分类号： G11B5/127 , G11B5/33
CPC分类号： G01R33/06 , H01L43/12 , Y10T29/49032 , Y10T29/49034 , Y10T29/49036 , Y10T29/49039 , Y10T29/49041 , Y10T29/49043 , Y10T29/49044
摘要： Methods and apparatus are provided for sensing physical parameters. The apparatus comprises a magnetic tunnel junction (MTJ) and a magnetic field source whose magnetic field overlaps the MTJ and whose proximity to the MTJ varies in response to an input to the sensor. A magnetic shield is provided at least on a face of the MFS away from the MTJ. The MTJ comprises first and second magnetic electrodes separated by a dielectric configured to permit significant tunneling conduction therebetween. The first magnetic region has its spin axis pinned and the second magnetic electrode has its spin axis free. The magnetic field source is oriented closer to the second magnetic electrode than the first magnetic electrode. The overall sensor dynamic range is extended by providing multiple electrically coupled sensors receiving the same input but with different individual response curves and desirably but not essentially formed on the same substrate.
摘要翻译：提供了用于感测物理参数的方法和装置。该装置包括磁隧道结（MTJ）和磁场源，其磁场与MTJ重叠，并且其与MTJ的接近度响应于对传感器的输入而变化。至少在远离MTJ的MFS的面上设有磁屏蔽。 MTJ包括由电介质隔开的第一和第二磁极，其被配置为允许它们之间的显着的隧穿传导。第一磁性区域的自旋轴被固定，第二磁极的自由轴自由。磁场源比第一磁极更靠近第二磁极。通过提供多个电耦合传感器来接收相同的输入但是具有不同的单个响应曲线并且期望地但不是基本上形成在相同的基板上来扩展总传感器动态范围。

4. 发明授权

US07324369B2 MRAM embedded smart power integrated circuits 有权
标题翻译： MRAM嵌入式智能电源集成电路
公开(公告)号：US07324369B2
公开(公告)日：2008-01-29
申请号：US11170874
申请日：2005-06-30
申请人： Young Sir Chung , Robert W. Baird , Mark A. Durlam , Gregory W. Grynkewich , Eric J. Salter
发明人： Young Sir Chung , Robert W. Baird , Mark A. Durlam , Gregory W. Grynkewich , Eric J. Salter
IPC分类号： G11C11/00
CPC分类号： G11C11/1659 , H01F10/3254
摘要： An integrated circuit device includes a magnetic random access memory (“MRAM”) architecture and a smart power integrated circuit architecture formed on the same substrate using the same fabrication process technology. The fabrication process technology is a modular process having a front end process and a back end process. In the example embodiment, the smart power architecture includes a power circuit component, a digital logic component, and an analog control component formed by the front end process, and a sensor architecture formed by the back end process. The MRAM architecture includes an MRAM circuit component formed by the front end process and an MRAM cell array formed by the back end process. In one practical embodiment, the sensor architecture includes a sensor component that is formed from the same magnetic tunnel junction core material utilized by the MRAM cell array. The concurrent fabrication of the MRAM architecture and the smart power architecture facilitates an efficient and cost effective use of the physical space available over active circuit blocks of the substrate, resulting in three-dimensional integration.
摘要翻译：集成电路装置包括使用相同的制造工艺技术在同一衬底上形成的磁性随机存取存储器（“MRAM”）架构和智能电力集成电路架构。制造工艺技术是具有前端工艺和后端工艺的模块化工艺。在该示例性实施例中，智能功率架构包括由前端处理形成的电源电路部件，数字逻辑部件和模拟控制部件以及由后端处理形成的传感器架构。 MRAM架构包括由前端处理形成的MRAM电路部件和由后端处理形成的MRAM单元阵列。在一个实际实施例中，传感器架构包括由MRAM单元阵列使用的相同的磁性隧道结芯体材料形成的传感器部件。 MRAM架构和智能电源架构的并行制造有助于在衬底的有源电路块上可用的物理空间的有效和成本有效的使用，导致三维集成。

5. 发明授权

US07445943B2 Magnetic tunnel junction memory and method with etch-stop layer 有权
标题翻译：磁隧道结记忆和具有蚀刻停止层的方法
公开(公告)号：US07445943B2
公开(公告)日：2008-11-04
申请号：US11584411
申请日：2006-10-19
申请人： Kenneth H. Smith , Brian R. Butcher , Gregory W. Grynkewich , Srinivas V. Pietambaram , Nicholas D. Rizzo
发明人： Kenneth H. Smith , Brian R. Butcher , Gregory W. Grynkewich , Srinivas V. Pietambaram , Nicholas D. Rizzo
IPC分类号： H01L21/00
CPC分类号： H01L43/12
摘要： Methods and apparatus are provided for magnetoresistive memories employing magnetic tunnel junction (MTJ). The apparatus comprises a MTJ (61, 231), first (60, 220) and second (66, 236) electrodes coupled, respectively, to first (62, 232) and second (64, 234) magnetic layers of the MTJ (61, 231), first (54, 204) and second (92, 260) write conductors magnetically coupled to the MTJ (61, 231) and spaced apart from the first (60, 220) and second (66, 236) electrodes, and at least one etch-stop layer (82, 216) located between the first write conductor (54, 204) and the first electrode (60, 220), having an etch rate in a reagent for etching the MTJ (61, 231) and/or the first electrode (60, 220) that is at most 25% of the etch rate of the MTJ (61, 231) and/or first conductor (60, 220) to the same reagent, so as to allow portions of the MTJ (61, 231) and first electrode (60, 220) to be removed without affecting the underlying first write conductor (54, 204). In a further embodiment, a second etch-stop layer (90, 250) is located between the second electrode (66, 236) and the second write conductor (92, 260). Improved yield and performance are obtained.
摘要翻译：提供了采用磁隧道结（MTJ）的磁阻存储器的方法和装置。该装置包括MTJ（61,231），第一（60,220）和第二（66,236）电极，其分别耦合到MTJ（61）的第一（62,232）和第二（64,234）磁性层，231），第一（54,204）和第二（92,260）写入导体，其磁耦合到MTJ（61,231）并且与第一（60,220）和第二（66,236）电极间隔开，以及位于所述第一写入导体（54,204）和所述第一电极（60,220）之间的至少一个蚀刻停止层（82,216）具有用于蚀刻所述MTJ（61,231）的试剂中的蚀刻速率和 /或第一电极（60,220），其至多为MTJ（61,231）和/或第一导体（60,220）的蚀刻速率的25％的相同试剂，以便允许部分 MTJ（61,231）和第一电极（60,220）被去除而不影响下面的第一写入导体（54,204）。在另一实施例中，第二蚀刻停止层（90,250）位于第二电极（66,236）和第二写入导体（92,260）之间。获得了提高的产量和性能。

6. 发明授权

US07169622B2 Magnetoresistive random access memory devices and methods for fabricating the same 有权
标题翻译：磁阻随机存取存储器件及其制造方法
公开(公告)号：US07169622B2
公开(公告)日：2007-01-30
申请号：US10912979
申请日：2004-08-05
申请人： Gregory W. Grynkewich , Brian R. Butcher , Mark A. Durlam , Clarence J. Tracy
发明人： Gregory W. Grynkewich , Brian R. Butcher , Mark A. Durlam , Clarence J. Tracy
IPC分类号： H01L21/00
CPC分类号： G11C11/16 , B82Y10/00 , H01L27/228
摘要： Fabricating a magnetoresistive random access memory cell and a structure for a magnetoresistive random access memory cell begins by providing a substrate having a transistor formed therein. A contact element is formed electrically coupled to the transistor and a dielectric material is deposited within an area partially bounded by the contact element. A digit line is formed within the dielectric material, the digit line overlying a portion of the contact element. A conductive layer is formed overlying the digit line and in electrical communication with the contact element.
摘要翻译：制造磁阻随机存取存储器单元和用于磁阻随机存取存储单元的结构开始于提供其中形成有晶体管的衬底。形成电耦合到晶体管的接触元件，并且电介质材料沉积在由接触元件部分界定的区域内。在电介质材料内形成数字线，数字线覆盖接触元件的一部分。导电层形成在数字线上方并与接触元件电连通。

7. 发明授权

US06518071B1 Magnetoresistive random access memory device and method of fabrication thereof 失效
标题翻译：磁阻随机存取存储器件及其制造方法
公开(公告)号：US06518071B1
公开(公告)日：2003-02-11
申请号：US10109429
申请日：2002-03-28
申请人： Mark A. Durlam , Mark F. Deherrera , Kelly W. Kyler , Brian R. Butcher , Gregory W. Grynkewich , Steven M. Smith , Charles Snyder , Jon M. Slaughter
发明人： Mark A. Durlam , Mark F. Deherrera , Kelly W. Kyler , Brian R. Butcher , Gregory W. Grynkewich , Steven M. Smith , Charles Snyder , Jon M. Slaughter
IPC分类号： H01L2100
CPC分类号： H01L43/12
摘要： A method of fabricating a MRAM device with a taper comprising the steps of providing a substrate, forming a dielectric region with positioned on the substrate, patterning and isotropically etching through the dielectric region to the substrate to form a trench, depositing the MRAM device within the trench wherein the MRAM device includes a first ferromagnetic region with a width positioned on the substrate, a non-ferromagnetic spacer layer with a width positioned on the first ferromagnetic region, and a second ferromagnetic region with a width positioned on the non-ferromagnetic spacer layer wherein the taper is formed by making the width of the first ferromagnetic region greater than the width of the non-ferromagnetic spacer layer, and the width of the non-ferromagnetic spacer layer greater than the width of the second ferromagnetic region so that the first ferromagnetic region is separated from the second ferromagnetic region.
摘要翻译：一种制造具有锥形的MRAM器件的方法，包括以下步骤：提供衬底，形成位于衬底上的电介质区域，对介质区域进行图案化和各向同性地蚀刻到衬底以形成沟槽，将MRAM器件沉积在沟槽，其中MRAM器件包括位于衬底上的宽度的第一铁磁区域，具有位于第一铁磁区域上的宽度的非铁磁间隔层，以及位于非铁磁间隔层上的宽度的第二铁磁区域其中所述锥形通过使所述第一铁磁性区域的宽度大于所述非铁磁间隔层的宽度而形成，并且所述非铁磁隔离层的宽度大于所述第二铁磁区域的宽度，使得所述第一铁磁性区域区域与第二铁磁区域分离。

8. 发明授权

US06783994B2 Method of fabricating a self-aligned magnetic tunneling junction and via contact 失效
标题翻译：制造自对准磁隧道结和通孔接触的方法
公开(公告)号：US06783994B2
公开(公告)日：2004-08-31
申请号：US10133136
申请日：2002-04-26
申请人： Nicholas D. Rizzo , Kelly W. Kyler , Gregory W. Grynkewich
发明人： Nicholas D. Rizzo , Kelly W. Kyler , Gregory W. Grynkewich
IPC分类号： H01L2100
CPC分类号： H01L27/228 , B82Y10/00 , G11C11/15 , G11C11/16 , H01L21/76838 , H01L43/12
摘要： A method of fabricating a magnetoresistive random access memory device comprising the steps of providing a substrate, forming a first conductive layer positioned on the substrate, forming a conductive material stack region with a flat surface, the conductive material stack region being positioned on a portion of the first conductive layer, and forming a magnetoresistive random access memory device positioned on the flat surface of the conductive material stack region, the magnetoresistive random access memory device being isolated from the first conductive layer and subsequent layers grown thereon.
摘要翻译：一种制造磁阻随机存取存储器件的方法，包括以下步骤：提供衬底，形成位于衬底上的第一导电层，形成具有平坦表面的导电材料堆叠区域，所述导电材料堆叠区域位于所述第一导电层，以及形成位于所述导电材料堆叠区域的平坦表面上的磁阻随机存取存储器件，所述磁阻随机存取存储器件与所述第一导电层及其后生长的层隔离。

9. 发明授权

US5650356A Method for reducing corrosion in openings on a semiconductor wafer 失效
标题翻译：降低半导体晶圆上的开口腐蚀的方法
公开(公告)号：US5650356A
公开(公告)日：1997-07-22
申请号：US613327
申请日：1996-03-11
申请人： Gordon M. Grivna , Gregory W. Grynkewich , Thomas S. Roche
发明人： Gordon M. Grivna , Gregory W. Grynkewich , Thomas S. Roche
IPC分类号： C23C22/68 , H01L21/02 , H01L21/321 , H01L21/3213 , H01L21/44
CPC分类号： H01L21/02071 , C23C22/68 , H01L21/321 , Y10S438/906 , Y10S438/958
摘要： A method is provided for reducing corrosion in openings on a semiconductor wafer. An etched opening is provided in a dielectric material on the semiconductor wafer. The etched opening and the dielectric material are cleaned with a basic solution. The exposed metal surface is treated with a hydrogen peroxide solution before exposing the exposed metal surface to an aqueous solution.
摘要翻译：提供了一种用于减少半导体晶片上的开口中的腐蚀的方法。蚀刻的开口设置在半导体晶片上的电介质材料中。蚀刻的开口和电介质材料用碱性溶液清洗。在将暴露的金属表面暴露于水溶液之前，用过氧化氢溶液处理暴露的金属表面。

10. 发明授权

US07279341B2 Method for fabricating a flux concentrating system for use in a magnetoelectronics device 失效
标题翻译：制造用于磁电装置的通量集中系统的方法
公开(公告)号：US07279341B2
公开(公告)日：2007-10-09
申请号：US11125955
申请日：2005-05-09
申请人： Thomas V. Meixner , Gregory W. Grynkewich , Jaynal A. Molla , J. Jack Ren , Richard G. Williams , Brian R. Butcher , Mark A. Durlam
发明人： Thomas V. Meixner , Gregory W. Grynkewich , Jaynal A. Molla , J. Jack Ren , Richard G. Williams , Brian R. Butcher , Mark A. Durlam
IPC分类号： H01L21/465
CPC分类号： H01L27/222 , B82Y10/00 , G11C11/16 , H01L43/12
摘要： A method for fabricating a flux concentrating system (62) for use in a magnetoelectronics device is provided. The method comprises the steps of providing a bit line (10) formed in a substrate (12) and forming a first material layer (24) overlying the bit line (10) and the substrate (12). Etching is performed to form a trench (58) in the first material layer (24) and a cladding layer (56) is deposited in the trench (52). A buffer material layer (58) is formed overlying the cladding layer (56) and a portion of the buffer material layer (58) and a portion of the cladding layer (56) is removed.
摘要翻译：提供了一种用于制造用于磁电装置的通量集中系统（62）的方法。该方法包括以下步骤：提供在衬底（12）中形成的位线（10），并形成覆盖位线（10）和衬底（12）的第一材料层（24）。进行蚀刻以在第一材料层（24）中形成沟槽（58），并且在沟槽（52）中沉积包层（56）。缓冲材料层（58）形成在覆层（56）上，缓冲材料层（58）的一部分和包覆层（56）的一部分被去除。

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