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1. 发明授权

US06784510B1 Magnetoresistive random access memory device structures 有权
标题翻译：磁阻随机存取存储器件结构
公开(公告)号：US06784510B1
公开(公告)日：2004-08-31
申请号：US10417851
申请日：2003-04-16
申请人： Gregory W. Grynkewich , Mark Deherrera , Mark A. Durlam , Clarence J. Tracy
发明人： Gregory W. Grynkewich , Mark Deherrera , Mark A. Durlam , Clarence J. Tracy
IPC分类号： H01L2900
CPC分类号： H01L27/228 , B82Y10/00
摘要： A method for fabricating an MRAM device structure includes providing a substrate on which is formed a first transistor and a second transistor. An operative memory element device is formed in electrical contact with the first transistor. At least a portion of a false memory element device is formed in electrical contact with the second transistor. A first dielectric layer is deposited overlying the at least a portion of a false memory element device and the operative memory element device. The first dielectric layer is etched to simultaneously form a first via to the at least a portion of a false memory element device and a second via to the operative memory element device. An electrically conductive interconnect layer is deposited so the electrically conductive interconnect layer extends from the at least a portion of a false memory element device to the operative memory element device.
摘要翻译：一种用于制造MRAM器件结构的方法包括提供其上形成有第一晶体管和第二晶体管的衬底。操作存储元件装置形成为与第一晶体管电接触。假存储元件器件的至少一部分形成为与第二晶体管电接触。第一介电层沉积在伪存储元件器件和操作存储元件器件的至少一部分上。蚀刻第一电介质层以同时形成第一通孔到伪存储元件器件的至少一部分，并将第二通孔形成到操作存储元件器件。沉积导电互连层，使得导电互连层从假存储元件器件的至少一部分延伸到可操作存储元件器件。

2. 发明授权

US06890770B2 Magnetoresistive random access memory device structures and methods for fabricating the same 有权
标题翻译：磁阻随机存取存储器件结构及其制造方法
公开(公告)号：US06890770B2
公开(公告)日：2005-05-10
申请号：US10885869
申请日：2004-07-06
申请人： Gregory W. Grynkewich , Mark Deherrera , Mark A. Durlam , Clarence J. Tracy
发明人： Gregory W. Grynkewich , Mark Deherrera , Mark A. Durlam , Clarence J. Tracy
IPC分类号： G11C20060101 , G11C8/02 , H01L21/00 , H01L21/8246 , H01L27/22 , H01L29/00 , H01L29/82
CPC分类号： H01L27/228 , B82Y10/00
摘要： A method for fabricating an MRAM device structure includes providing a substrate on which is formed a first transistor and a second transistor. An operative memory element device is formed in electrical contact with the first transistor. At least a portion of a false memory element device is formed in electrical contact with the second transistor. A first dielectric layer is deposited overlying the at least a portion of a false memory element device and the operative memory element device. The first dielectric layer is etched to simultaneously form a first via to the at least a portion of a false memory element device and a second via to the operative memory element device. An electrically conductive interconnect layer is deposited so the electrically conductive interconnect layer extends from the at least a portion of a false memory element device to the operative memory element device.
摘要翻译：一种用于制造MRAM器件结构的方法包括提供其上形成有第一晶体管和第二晶体管的衬底。操作存储元件装置形成为与第一晶体管电接触。假存储元件器件的至少一部分形成为与第二晶体管电接触。第一介电层沉积在伪存储元件器件和操作存储元件器件的至少一部分上。蚀刻第一电介质层以同时形成第一通孔到伪存储元件器件的至少一部分，并将第二通孔形成到操作存储元件器件。沉积导电互连层，使得导电互连层从假存储元件器件的至少一部分延伸到可操作存储元件器件。

3. 发明授权

US07169622B2 Magnetoresistive random access memory devices and methods for fabricating the same 有权
标题翻译：磁阻随机存取存储器件及其制造方法
公开(公告)号：US07169622B2
公开(公告)日：2007-01-30
申请号：US10912979
申请日：2004-08-05
申请人： Gregory W. Grynkewich , Brian R. Butcher , Mark A. Durlam , Clarence J. Tracy
发明人： Gregory W. Grynkewich , Brian R. Butcher , Mark A. Durlam , Clarence J. Tracy
IPC分类号： H01L21/00
CPC分类号： G11C11/16 , B82Y10/00 , H01L27/228
摘要： Fabricating a magnetoresistive random access memory cell and a structure for a magnetoresistive random access memory cell begins by providing a substrate having a transistor formed therein. A contact element is formed electrically coupled to the transistor and a dielectric material is deposited within an area partially bounded by the contact element. A digit line is formed within the dielectric material, the digit line overlying a portion of the contact element. A conductive layer is formed overlying the digit line and in electrical communication with the contact element.
摘要翻译：制造磁阻随机存取存储器单元和用于磁阻随机存取存储单元的结构开始于提供其中形成有晶体管的衬底。形成电耦合到晶体管的接触元件，并且电介质材料沉积在由接触元件部分界定的区域内。在电介质材料内形成数字线，数字线覆盖接触元件的一部分。导电层形成在数字线上方并与接触元件电连通。

4. 发明授权

US06798004B1 Magnetoresistive random access memory devices and methods for fabricating the same 有权
标题翻译：磁阻随机存取存储器件及其制造方法
公开(公告)号：US06798004B1
公开(公告)日：2004-09-28
申请号：US10421095
申请日：2003-04-22
申请人： Gregory W. Grynkewich , Brian R. Butcher , Mark A. Durlam , Clarence J. Tracy
发明人： Gregory W. Grynkewich , Brian R. Butcher , Mark A. Durlam , Clarence J. Tracy
IPC分类号： H01L2976
CPC分类号： G11C11/16 , B82Y10/00 , H01L27/228
摘要： Fabricating a magnetoresistive random access memory cell and a structure for a magnetoresistive random access memory cell begins by providing a substrate having a transistor formed therein. A contact element is formed electrically coupled to the transistor and a dielectric material is deposited within an area partially bounded by the contact element. A digit line is formed within the dielectric material, the digit line overlying a portion of the contact element. A conductive layer is formed overlying the digit line and in electrical communication with the contact element.
摘要翻译：制造磁阻随机存取存储器单元和用于磁阻随机存取存储单元的结构开始于提供其中形成有晶体管的衬底。形成电耦合到晶体管的接触元件，并且电介质材料沉积在由接触元件部分界定的区域内。在电介质材料内形成数字线，数字线覆盖接触元件的一部分。导电层形成在数字线上方并与接触元件电连通。

5. 发明授权

US06911156B2 Methods for fabricating MRAM device structures 有权
标题翻译：制造MRAM器件结构的方法
公开(公告)号：US06911156B2
公开(公告)日：2005-06-28
申请号：US10417537
申请日：2003-04-16
申请人： Gregory W. Grynkewich , Brian R. Butcher , Mark A. Durlam , Kelly Kyler , Kenneth H. Smith , Clarence J. Tracy
发明人： Gregory W. Grynkewich , Brian R. Butcher , Mark A. Durlam , Kelly Kyler , Kenneth H. Smith , Clarence J. Tracy
IPC分类号： G11B5/127 , G11C11/16 , H01L21/00 , H01L43/12 , H04R31/00 , H05K3/02
CPC分类号： G11C11/16 , H01L43/12 , Y10T29/49041 , Y10T29/49044 , Y10T29/49156 , Y10T29/49165
摘要： A method for fabricating a magnetic memory element structure comprises providing a dielectric layer having a conducting via. A first magnetic layer is formed overlying the dielectric layer and is in electrical communication with the conducting via. A non-magnetic layer and a second magnetic layer are formed overlying the first magnetic layer. A first conductive layer is deposited overlying the second magnetic layer and is patterned. A portion of the second magnetic layer is exposed and is transformed to form an inactive portion and an active portion. The active portion comprises a portion of a memory element and the inactive portion comprises an insulator. A sidewall spacer is formed about at least one sidewall of the first conductive layer and a masking tab is formed that overlies a portion of the memory element and extends to overlie at least a portion of the conducting via.
摘要翻译：一种用于制造磁存储元件结构的方法，包括提供具有导电通孔的电介质层。第一磁性层形成在电介质层上并与导电通孔电连通。在第一磁性层上形成非磁性层和第二磁性层。将第一导电层沉积在第二磁性层上并被图案化。第二磁性层的一部分被暴露并被变换以形成非活性部分和活性部分。有源部分包括存储元件的一部分，非活性部分包括绝缘体。围绕第一导电层的至少一个侧壁形成侧壁间隔物，并且形成覆盖存储元件的一部分并延伸以覆盖导电通孔的至少一部分的掩蔽突片。

6. 发明授权

US07476329B2 Methods for contacting conducting layers overlying magnetoelectronic elements of MRAM devices 有权
标题翻译：用于接触覆盖MRAM器件的电磁元件的导电层的方法
公开(公告)号：US07476329B2
公开(公告)日：2009-01-13
申请号：US11050191
申请日：2005-02-02
申请人： Gregory W. Grynkewich , Brian R. Butcher , Mark A. Durlam , Kelly Kyler , Charles A. Synder , Kenneth H. Smith , Clarence J. Tracy , Richard Williams
发明人： Gregory W. Grynkewich , Brian R. Butcher , Mark A. Durlam , Kelly Kyler , Charles A. Synder , Kenneth H. Smith , Clarence J. Tracy , Richard Williams
IPC分类号： H01L21/00
CPC分类号： H01L27/222 , B82Y10/00 , G11C11/15 , H01L43/12
摘要： A method for contacting an electrically conductive layer overlying a magnetoelectronics element includes forming a memory element layer overlying a dielectric region. A first electrically conductive layer is deposited overlying the memory element layer. A first dielectric layer is deposited overlying the first electrically conductive layer and is patterned and etched to form a first masking layer. Using the first masking layer, the first electrically conductive layer is etched. A second dielectric layer is deposited overlying the first masking layer and the dielectric region. A portion of the second dielectric layer is removed to expose the first masking layer. The second dielectric layer and the first masking layer are subjected to an etching chemistry such that the first masking layer is etched at a faster rate than the second dielectric layer. The etching exposes the first electrically conductive layer.
摘要翻译：用于使覆盖磁电元件的导电层接触的方法包括形成覆盖电介质区域的存储元件层。沉积在存储元件层上的第一导电层。第一电介质层沉积在第一导电层上，并被图案化和蚀刻以形成第一掩模层。使用第一掩模层，蚀刻第一导电层。沉积第二介电层，覆盖第一掩模层和电介质区域。去除第二介电层的一部分以露出第一掩模层。对第二介电层和第一掩模层进行蚀刻化学处理，使得以比第二介电层更快的速率蚀刻第一掩模层。蚀刻暴露第一导电层。

7. 发明授权

US06881351B2 Methods for contacting conducting layers overlying magnetoelectronic elements of MRAM devices 有权
标题翻译：用于接触覆盖MRAM器件的电磁元件的导电层的方法
公开(公告)号：US06881351B2
公开(公告)日：2005-04-19
申请号：US10421096
申请日：2003-04-22
申请人： Gregory W. Grynkewich , Brian R. Butcher , Mark A. Durlam , Kelly Kyler , Charles A. Synder , Kenneth H. Smith , Clarence J. Tracy , Richard Williams
发明人： Gregory W. Grynkewich , Brian R. Butcher , Mark A. Durlam , Kelly Kyler , Charles A. Synder , Kenneth H. Smith , Clarence J. Tracy , Richard Williams
IPC分类号： G11C11/15 , H01L21/8246 , H01L43/12 , H01L21/00
CPC分类号： H01L27/222 , B82Y10/00 , G11C11/15 , H01L43/12
摘要： A method for contacting an electrically conductive layer overlying a magnetoelectronics element includes forming a memory element layer overlying a dielectric region. A first electrically conductive layer is deposited overlying the memory element layer. A first dielectric layer is deposited overlying the first electrically conductive layer and is patterned and etched to form a first masking layer. Using the first masking layer, the first electrically conductive layer is etched. A second dielectric layer is deposited overlying the first masking layer and the dielectric region. A portion of the second dielectric layer is removed to expose the first masking layer. The second dielectric layer and the first masking layer are subjected to an etching chemistry such that the first masking layer is etched at a faster rate than the second dielectric layer. The etching exposes the first electrically conductive layer.
摘要翻译：用于使覆盖磁电元件的导电层接触的方法包括形成覆盖电介质区域的存储元件层。沉积在存储元件层上的第一导电层。第一电介质层沉积在第一导电层上，并被图案化和蚀刻以形成第一掩模层。使用第一掩模层，蚀刻第一导电层。沉积第二介电层，覆盖第一掩模层和电介质区域。去除第二介电层的一部分以露出第一掩模层。对第二介电层和第一掩模层进行蚀刻化学处理，使得以比第二介电层更快的速率蚀刻第一掩模层。蚀刻暴露第一导电层。

8. 发明授权

US5700721A Structure and method for metallization of semiconductor devices 失效
标题翻译：半导体器件金属化的结构和方法
公开(公告)号：US5700721A
公开(公告)日：1997-12-23
申请号：US658041
申请日：1996-06-04
申请人： Hank Hukyoo Shin , Clarence J. Tracy , Robert L. Duffin , John L. Freeman, Jr. , Gordon Grivna , Syd R. Wilson
发明人： Hank Hukyoo Shin , Clarence J. Tracy , Robert L. Duffin , John L. Freeman, Jr. , Gordon Grivna , Syd R. Wilson
IPC分类号： H01L23/532 , H01L21/443
CPC分类号： H01L23/53219 , H01L2924/0002
摘要： A metallization alloy for semiconductor devices comprising aluminum, copper, and tungsten is provided. In a method for applying the metallization, the metal is sputtered onto a semiconductor substrate having devices formed therein. After deposition, the metallization is patterned and etched using conventional semiconductor photoresist and etch techniques.
摘要翻译：提供了一种用于包括铝，铜和钨的半导体器件的金属化合金。在施加金属化的方法中，将金属溅射到其上形成有器件的半导体衬底上。沉积后，使用常规的半导体光致抗蚀剂和蚀刻技术对金属化进行构图和蚀刻。

9. 发明授权

US5554889A Structure and method for metallization of semiconductor devices 失效
标题翻译：半导体器件金属化的结构和方法
公开(公告)号：US5554889A
公开(公告)日：1996-09-10
申请号：US430105
申请日：1995-04-27
申请人： Hank H. Shin , Clarence J. Tracy , Robert L. Duffin , John L. Freeman, Jr. , Gordon Grivna , Syd R. Wilson
发明人： Hank H. Shin , Clarence J. Tracy , Robert L. Duffin , John L. Freeman, Jr. , Gordon Grivna , Syd R. Wilson
IPC分类号： H01L23/532 , A01L23/48 , A01L23/52 , A01L29/40
CPC分类号： H01L23/53219 , H01L2924/0002
摘要： A metallization alloy for semiconductor devices comprising aluminum, copper, and tungsten is provided. In a method for applying the metallization, the metal is sputtered onto a semiconductor substrate having devices formed therein. After deposition, the metallization is patterned and etched using conventional semiconductor photoresist and etch techniques.
摘要翻译：提供了一种用于包括铝，铜和钨的半导体器件的金属化合金。在施加金属化的方法中，将金属溅射到其上形成有器件的半导体衬底上。沉积后，使用常规的半导体光致抗蚀剂和蚀刻技术对金属化进行构图和蚀刻。

10. 发明授权

US4717446A Method of detecting the endpoint of the etch of epitaxially grown silicon 失效
标题翻译：检测外延生长硅蚀刻终点的方法
公开(公告)号：US4717446A
公开(公告)日：1988-01-05
申请号：US909043
申请日：1986-09-18
申请人： Andrew G. Nagy , Donald K. Stemple , Clarence J. Tracy
发明人： Andrew G. Nagy , Donald K. Stemple , Clarence J. Tracy
IPC分类号： G01B11/06 , H01L21/66 , H01L21/306
CPC分类号： B24B37/013 , G01B11/0683 , H01L22/26
摘要： A method of detecting the endpoint of expitaxially grown silicon using a monitor wafer is described. A monitor wafer having a substrate, an oxide layer, and a polysilicon layer is process in an epi chamber along with working wafers. The monitor wafer is used to determine the endpoint of the working wafers epi layer when the epi layer is etched.
摘要翻译：描述了使用监视器晶片检测外延生长的硅的端点的方法。具有衬底，氧化物层和多晶硅层的监测晶片与工作晶片一起在外延室中进行。当外延层被蚀刻时，监测晶片用于确定工作晶片外延层的端点。

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