专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

21. 发明授权

US08637958B2 Structure and method for forming isolation and buried plate for trench capacitor 有权
标题翻译：用于形成沟槽电容器的隔离和掩埋板的结构和方法
公开(公告)号：US08637958B2
公开(公告)日：2014-01-28
申请号：US13617576
申请日：2012-09-14
申请人： Abhishek Dube , Subramanian S. Iyer , Babar Ali Khan , Oh-jung Kwon , Junedong Lee , Paul C. Parries , Chengwen Pei , Gerd Pfeiffer , Ravi Todi , Geng Wang
发明人： Abhishek Dube , Subramanian S. Iyer , Babar Ali Khan , Oh-jung Kwon , Junedong Lee , Paul C. Parries , Chengwen Pei , Gerd Pfeiffer , Ravi Todi , Geng Wang
IPC分类号： H01L21/02
CPC分类号： H01L29/945 , H01L21/76229 , H01L21/84 , H01L29/66181
摘要： A structure and method for forming isolation and a buried plate for a trench capacitor is disclosed. Embodiments of the structure comprise an epitaxial layer serving as the buried plate, and a bounded deep trench isolation area serving to isolate one or more deep trench structures. Embodiments of the method comprise angular implanting of the deep trench isolation area to form a P region at the base of the deep trench isolation area that serves as an anti-punch through implant.
摘要翻译：公开了用于形成隔离的结构和方法以及用于沟槽电容器的掩埋板。该结构的实施例包括用作掩埋板的外延层和用于隔离一个或多个深沟槽结构的有界深沟槽隔离区。该方法的实施例包括深沟槽隔离区域的角度注入，以在用作抗穿孔植入物的深沟槽隔离区域的底部形成P区。

22. 发明授权

US08415252B2 Selective copper encapsulation layer deposition 有权
标题翻译：选择性铜包层沉积
公开(公告)号：US08415252B2
公开(公告)日：2013-04-09
申请号：US12683857
申请日：2010-01-07
申请人： Tien-Jen Cheng , Abhishek Dube , Zhengwen Li , Huilong Zhu
发明人： Tien-Jen Cheng , Abhishek Dube , Zhengwen Li , Huilong Zhu
IPC分类号： H01L21/44
CPC分类号： H01L21/76834 , H01L21/76826 , H01L21/76832 , H05K3/282 , H05K3/388 , H05K3/4682
摘要： A metal interconnect structure provides high adhesive strength between copper atoms in a copper-containing structure and a self-aligned copper encapsulation layer, which is selectively deposited only on exposed copper surfaces. A lower level metal interconnect structure comprises a first dielectric material layer and a copper-containing structure embedded in a lower metallic liner. After a planarization process that forms the copper-containing structure, a material that forms Cu—S bonds with exposed surfaces of the copper-containing structure is applied to the surface of the copper-containing structure. The material is selectively deposited only on exposed Cu surfaces, thereby forming a self-aligned copper encapsulation layer, and provides a high adhesion strength to the copper surface underneath. A dielectric cap layer and an upper level metal interconnect structure can be subsequently formed on the copper encapsulation layer.
摘要翻译：金属互连结构在含铜结构中的铜原子和自对准铜封装层之间提供高粘合强度，其仅选择性地沉积在暴露的铜表面上。下层金属互连结构包括第一介电材料层和嵌入在下金属衬里中的含铜结构。在形成含铜结构的平坦化工艺之后，将含铜结构体的露出表面形成Cu-S键的材料施加到含铜结构体的表面。该材料仅选择性地沉积在暴露的Cu表面上，从而形成自对准的铜封装层，并且对下面的铜表面提供高粘附强度。随后可以在铜封装层上形成电介质盖层和上层金属互连结构。

23. 发明授权

US08394712B2 Cavity-free interface between extension regions and embedded silicon-carbon alloy source/drain regions 有权
标题翻译：扩展区域和嵌入式硅 - 碳合金源极/漏极区域之间的无空隙界面
公开(公告)号：US08394712B2
公开(公告)日：2013-03-12
申请号：US13101260
申请日：2011-05-05
申请人： Abhishek Dube , Viorel Ontalus
发明人： Abhishek Dube , Viorel Ontalus
IPC分类号： H01L21/20
CPC分类号： H01L21/823481 , H01L21/823412 , H01L21/823807 , H01L21/823878 , H01L29/665 , H01L29/66545 , H01L29/66628 , H01L29/66636 , H01L29/7848
摘要： A gate stack is formed on a silicon substrate, and source/drain extension regions are formed around the gate stack. A dielectric spacer is formed around the gate stack. A pair of trenches is formed around the gate stack and the dielectric spacer by an etch so that sidewalls of the source/drain extension regions are exposed. Within each trench, an n-doped silicon liner is deposited on the sidewalls of the trenches by a first selective epitaxy process so that the interface between the dielectric spacer and the source/drain extension region is covered. Within each trench, an n-doped single crystalline silicon-carbon alloy is subsequently deposited to fill the trench by a second selective epitaxy process. A combination of an n-doped single crystalline silicon liner and an n-doped single crystalline silicon-carbon alloy functions as embedded source/drain regions of an n-type field effect transistor (NFET), which applies a tensile stress to the channel of the transistor.
摘要翻译：在硅衬底上形成栅极叠层，并且在栅极堆叠周围形成源极/漏极延伸区域。在栅极堆叠周围形成介电隔离物。通过蚀刻在栅极堆叠和电介质间隔物周围形成一对沟槽，使得源极/漏极延伸区域的侧壁被暴露。在每个沟槽内，通过第一选择性外延工艺将n掺杂硅衬垫沉积在沟槽的侧壁上，以便覆盖介质间隔物与源极/漏极延伸区之间的界面。在每个沟槽内，随后沉积n掺杂的单晶硅 - 碳合金以通过第二选择性外延工艺填充沟槽。 n掺杂单晶硅衬垫和n掺杂单晶硅碳合金的组合用作n型场效应晶体管（NFET）的嵌入式源极/漏极区域，其对该沟道施加拉伸应力晶体管。

24. 发明申请

US20120248436A1 REDUCED PATTERN LOADING FOR DOPED EPITAXIAL PROCESS AND SEMICONDUCTOR STRUCTURE 失效
标题翻译：用于掺杂外延工艺和半导体结构的减少图案加载
公开(公告)号：US20120248436A1
公开(公告)日：2012-10-04
申请号：US13075450
申请日：2011-03-30
申请人： Abhishek Dube , Viorel Ontalus , Kathryn T. Schonenberg , Zhengmao Zhu
发明人： Abhishek Dube , Viorel Ontalus , Kathryn T. Schonenberg , Zhengmao Zhu
IPC分类号： H01L23/48 , H01L21/20
CPC分类号： H01L21/823425 , H01L21/02529 , H01L21/02576 , H01L21/823412 , H01L22/12 , H01L22/34 , H01L29/66636 , H01L29/7848
摘要： A semiconductor substrate having transistor structures and test structures with spacing between the transistor structures smaller than the spacing between the test structures is provided. A first iteratively performed deposition and etch process includes: depositing a first doped epitaxial layer having a first concentration of a dopant over the semiconductor substrate, and etching the first doped epitaxial layer. A second iteratively performed deposition and etch process includes: depositing a second doped epitaxial layer having a second concentration of the dopant higher than the first concentration over the semiconductor substrate, and etching the second doped epitaxial layer. The first concentration results in a first net growth rate over the transistor structures and the second concentration results in a lower, second net growth rate over the test structures than the transistor structures, resulting in reduced pattern loading.
摘要翻译：提供了具有晶体管结构的半导体衬底和在晶体管结构之间具有小于测试结构之间的间隔的测试结构。第一迭代执行的沉积和蚀刻工艺包括：在半导体衬底上沉积具有掺杂剂的第一浓度的第一掺杂外延层，并蚀刻第一掺杂外延层。第二迭代进行的沉积和蚀刻工艺包括：在半导体衬底上沉积具有高于第一浓度的掺杂剂的第二浓度的第二掺杂外延层，并蚀刻第二掺杂外延层。第一个浓度导致超过晶体管结构的第一净增长率，而第二浓度导致比晶体管结构高出测试结构的较低的第二净增长率，导致模式负载减小。

25. 发明申请

US20120068193A1 STRUCTURE AND METHOD FOR INCREASING STRAIN IN A DEVICE 有权
标题翻译：在设备中增加应变的结构和方法
公开(公告)号：US20120068193A1
公开(公告)日：2012-03-22
申请号：US12886903
申请日：2010-09-21
申请人： KEVIN K. CHAN , Abhishek Dube , Viorel C. Ontalus
发明人： KEVIN K. CHAN , Abhishek Dube , Viorel C. Ontalus
IPC分类号： H01L29/78 , H01L21/20
CPC分类号： H01L29/7847 , H01L21/26506 , H01L21/26566 , H01L21/26593 , H01L29/165 , H01L29/66636 , H01L29/78 , H01L29/7848
摘要： A method and structure are disclosed for increasing strain in a device, specifically an n-type field effect transistor (NFET) complementary metal-oxide-semiconductor (CMOS) device. Embodiments of this invention include growing an epitaxial layer, performing a cold carbon or cluster carbon pre-amorphization implantation to implant substitutional carbon into the epitaxial layer, forming a tensile cap over the epitaxial layer, and then annealing to recrystallize the amorphous layer to create a stress memorization technique (SMT) effect. The epitaxial layer will therefore include substitutional carbon and have a memorized tensile stress induced by the SMT. Embodiments of this invention can also include a lower epitaxial layer under the epitaxial layer, the lower epitaxial layer comprising for example, a silicon carbon phosphorous (SiCP) layer.
摘要翻译：公开了用于增加器件中应变的方法和结构，特别是n型场效应晶体管（NFET）互补金属氧化物半导体（CMOS）器件。本发明的实施例包括生长外延层，进行冷碳或簇碳预非晶化注入以将取代碳注入到外延层中，在外延层上形成拉伸帽，然后退火以使非晶层重结晶以产生应力记忆技术（SMT）效应。因此，外延层将包括取代碳并具有由SMT引起的记忆拉伸应力。本发明的实施例还可以包括在外延层下面的下部外延层，下部外延层包括例如硅碳磷（SiCP）层。

26. 发明授权

US08035141B2 Bi-layer nFET embedded stressor element and integration to enhance drive current 有权
标题翻译：双层nFET嵌入式应力元件并集成增强驱动电流
公开(公告)号：US08035141B2
公开(公告)日：2011-10-11
申请号：US12607104
申请日：2009-10-28
申请人： Kevin K. Chan , Abhishek Dube , Jinghong Li , Viorel Ontalus , Zhengmao Zhu
发明人： Kevin K. Chan , Abhishek Dube , Jinghong Li , Viorel Ontalus , Zhengmao Zhu
IPC分类号： H01L29/76
CPC分类号： H01L29/7848 , H01L29/165 , H01L29/66636 , H01L29/7834 , Y10S257/90 , Y10S257/902 , Y10S257/903
摘要： A semiconductor structure including a bi-layer nFET embedded stressor element is disclosed. The bi-layer nFET embedded stressor element can be integrated into any CMOS process flow. The bi-layer nFET embedded stressor element includes an implant damaged free first layer of a first epitaxy semiconductor material having a lattice constant that is different from a lattice constant of a semiconductor substrate and imparts a tensile strain in a device channel of an nFET gate stack. Typically, and when the semiconductor is composed of silicon, the first layer of the bi-layer nFET embedded stressor element is composed of Si:C. The bi-layer nFET embedded stressor element further includes a second layer of a second epitaxy semiconductor material that has a lower resistance to dopant diffusion than the first epitaxy semiconductor material. Typically, and when the semiconductor is composed of silicon, the second layer of the bi-layer nFET embedded stressor element is composed of silicon. Only the second layer of the bi-layer nFET embedded stressor element includes the implanted source/drain regions.
摘要翻译：公开了一种包括双层nFET嵌入式应力元件的半导体结构。双层nFET嵌入式应力元件可以集成到任何CMOS工艺流程中。双层nFET嵌入式应力元件包括具有不同于半导体衬底的晶格常数的晶格常数的第一外延半导体材料的免费第一层的植入物，并且在nFET栅极堆叠的器件沟道中施加拉伸应变。通常，当半导体由硅组成时，双层nFET嵌入的应力元件的第一层由Si：C组成。双层nFET嵌入式应力元件还包括具有比第一外延半导体材料更低的掺杂剂扩散阻力的第二外延半导体材料层。通常，当半导体由硅组成时，双层nFET嵌入的应力元件的第二层由硅组成。双层nFET嵌入式应力元件的第二层仅包括注入的源极/漏极区域。

27. 发明申请

US20100090288A1 METHOD OF FORMING SOURCE AND DRAIN OF A FIELD-EFFECT-TRANSISTOR AND STRUCTURE THEREOF 有权
标题翻译：形成源极和场效应晶体管的方法及其结构
公开(公告)号：US20100090288A1
公开(公告)日：2010-04-15
申请号：US12248970
申请日：2008-10-10
申请人： Judson R. Holt , Abhishek Dube , Eric C.T. Harley , Shwu-Jen Jeng , Jeremy J. Kempisty , Hasan Munir Nayfeh , Keith Howard Tabakman
发明人： Judson R. Holt , Abhishek Dube , Eric C.T. Harley , Shwu-Jen Jeng , Jeremy J. Kempisty , Hasan Munir Nayfeh , Keith Howard Tabakman
IPC分类号： H01L29/00 , H01L21/8238
CPC分类号： H01L29/7848 , H01L27/11 , H01L27/1104 , H01L29/1083 , H01L29/165 , H01L29/66628 , H01L29/66636
摘要： A semiconductor fabrication method involving the use of eSiGe is disclosed. The eSiGe approach is useful for applying the desired stresses to the channel region of a field effect transistor, but also can introduce complications into the semiconductor fabrication process. Embodiments of the present invention disclose a two-step fabrication process in which a first layer of eSiGe is applied using a low hydrogen flow rate, and a second eSiGe layer is applied using a higher hydrogen flow rate. This method provides a way to balance the tradeoff of morphology, and fill consistency when using eSiGe. Embodiments of the present invention promote a pinned morphology, which reduces device sensitivity to epitaxial thickness, while also providing a more consistent fill volume, amongst various device widths, thereby providing a more consistent eSiGe semiconductor fabrication process.
摘要翻译：公开了涉及使用eSiGe的半导体制造方法。 eSiGe方法对于将期望的应力施加到场效应晶体管的沟道区域是有用的，但是也可能在半导体制造工艺中引入复杂性。本发明的实施方案公开了两步制备方法，其中使用低氢气流速施加第一层eSiGe，并且使用更高的氢气流速施加第二eSiGe层。这种方法提供了一种平衡形态权衡的方法，并在使用eSiGe时填补一致性。本发明的实施例促进了钉扎形态，其降低了对外延厚度的器件灵敏度，同时还在各种器件宽度之间提供更一致的填充体积，从而提供更一致的eSiGe半导体制造工艺。

28. 发明授权

US08551845B2 Structure and method for increasing strain in a device 有权
标题翻译：增加器件应变的结构和方法
公开(公告)号：US08551845B2
公开(公告)日：2013-10-08
申请号：US12886903
申请日：2010-09-21
申请人： Kevin K. Chan , Abhishek Dube , Viorel C. Ontalus
发明人： Kevin K. Chan , Abhishek Dube , Viorel C. Ontalus
IPC分类号： H01L21/336
CPC分类号： H01L29/7847 , H01L21/26506 , H01L21/26566 , H01L21/26593 , H01L29/165 , H01L29/66636 , H01L29/78 , H01L29/7848
摘要： A method and structure are disclosed for increasing strain in a device, specifically an n-type field effect transistor (NFET) complementary metal-oxide-semiconductor (CMOS) device. Embodiments of this invention include growing an epitaxial layer, performing a cold carbon or cluster carbon pre-amorphization implantation to implant substitutional carbon into the epitaxial layer, forming a tensile cap over the epitaxial layer, and then annealing to recrystallize the amorphous layer to create a stress memorization technique (SMT) effect. The epitaxial layer will therefore include substitutional carbon and have a memorized tensile stress induced by the SMT. Embodiments of this invention can also include a lower epitaxial layer under the epitaxial layer, the lower epitaxial layer comprising for example, a silicon carbon phosphorous (SiCP) layer.
摘要翻译：公开了用于增加器件中应变的方法和结构，特别是n型场效应晶体管（NFET）互补金属氧化物半导体（CMOS）器件。本发明的实施例包括生长外延层，进行冷碳或簇碳预非晶化注入以将取代碳注入到外延层中，在外延层上形成拉伸帽，然后退火以使非晶层重结晶以产生应力记忆技术（SMT）效应。因此，外延层将包括取代碳并具有由SMT引起的记忆拉伸应力。本发明的实施例还可以包括在外延层下面的下部外延层，下部外延层包括例如硅碳磷（SiCP）层。

29. 发明授权

US08426265B2 Method for growing strain-inducing materials in CMOS circuits in a gate first flow 有权
标题翻译：在栅极第一流中在CMOS电路中增长应变诱导材料的方法
公开(公告)号：US08426265B2
公开(公告)日：2013-04-23
申请号：US12938457
申请日：2010-11-03
申请人： Bo Bai , Linda Black , Abhishek Dube , Judson R. Holt , Viorel C. Ontalus , Kathryn T. Schonenberg , Matthew W. Stoker , Keith H. Tabakman
发明人： Bo Bai , Linda Black , Abhishek Dube , Judson R. Holt , Viorel C. Ontalus , Kathryn T. Schonenberg , Matthew W. Stoker , Keith H. Tabakman
IPC分类号： H01L21/8238
CPC分类号： H01L21/823807 , H01L21/823828
摘要： A method of manufacturing a complementary metal oxide semiconductor (CMOS) circuit, in which the method includes a reactive ion etch (RIE) of a CMOS circuit substrate that forms recesses, the CMOS circuit substrate including: an n-type field effect transistor (n-FET) region; a p-type field effect transistor (p-FET) region; an isolation region disposed between the n-FET and p-FET regions; and a gate wire comprising an n-FET gate, a p-FET gate, and gate material extending transversely from the n-FET gate across the isolation region to the p-FET gate, in which the recesses are formed adjacent to sidewalls of a reduced thickness; growing silicon germanium (SiGe) in the recesses; depositing a thin insulator layer on the CMOS circuit substrate; masking at least the p-FET region; removing the thin insulator layer from an unmasked n-FET region and an unmasked portion of the isolation region; etching the CMOS circuit substrate with hydrogen chloride (HCl) to remove the SiGe from the recesses in the n-FET region; and growing silicon carbon (SiC) in the exposed recesses.
摘要翻译：一种制造互补金属氧化物半导体（CMOS）电路的方法，其中所述方法包括形成凹部的CMOS电路基板的反应离子蚀刻（RIE），所述CMOS电路基板包括：n型场效应晶体管（n -FET）区域; p型场效应晶体管（p-FET）区域; 设置在n-FET和p-FET区之间的隔离区; 以及栅极线，其包括n-FET栅极，p-FET栅极和栅极材料，栅极材料从跨越隔离区域的n-FET栅极横向延伸到p-FET栅极，其中凹部形成为邻近于厚度减小在凹槽中生长硅锗（SiGe）; 在CMOS电路衬底上沉积薄的绝缘体层; 至少掩蔽p-FET区域; 从未掩蔽的n-FET区域和所述隔离区域的未屏蔽部分去除所述薄绝缘体层; 用氯化氢（HCl）蚀刻CMOS电路衬底以从n-FET区域中的凹槽去除SiGe; 并在暴露的凹槽中生长硅碳（SiC）。

30. 发明授权

US08421191B2 Monolayer dopant embedded stressor for advanced CMOS 有权
标题翻译：单层掺杂剂嵌入式应力器用于高级CMOS
公开(公告)号：US08421191B2
公开(公告)日：2013-04-16
申请号：US13533499
申请日：2012-06-26
申请人： Kevin K. Chan , Abhishek Dube , Judson R. Holt , Jinghong Li , Joseph S. Newbury , Viorel Ontalus , Dae-Gyu Park , Zhengmao Zhu
发明人： Kevin K. Chan , Abhishek Dube , Judson R. Holt , Jinghong Li , Joseph S. Newbury , Viorel Ontalus , Dae-Gyu Park , Zhengmao Zhu
IPC分类号： H01L31/117
CPC分类号： H01L29/7848 , H01L21/823807 , H01L21/823814 , H01L29/165 , H01L29/6656 , H01L29/66636 , H01L29/7834
摘要： Semiconductor structures are disclosed that include at least one FET gate stack located on a semiconductor substrate. The at least one FET gate stack includes source and drain extension regions located within the semiconductor substrate. A device channel is also present between the source and drain extension regions and beneath the at least one gate stack. Embedded stressor elements are located on opposite sides of the at least one FET gate stack and within the semiconductor substrate. Each stressor element includes a lower layer of a first epitaxy doped semiconductor material having a lattice constant that is different from a lattice constant of the semiconductor substrate and imparts a strain in the device channel, and an upper layer of a second epitaxy doped semiconductor material. At least one monolayer of dopant is located within the upper layer of each of the embedded stressor elements.
摘要翻译：公开了包括位于半导体衬底上的至少一个FET栅叠层的半导体结构。所述至少一个FET栅极堆叠包括位于半导体衬底内的源极和漏极延伸区域。器件沟道也存在于源极延伸区域和漏极延伸区域之间以及至少一个栅极堆叠层下方。嵌入式应力元件位于至少一个FET栅极堆叠的相对侧并且位于半导体衬底内。每个应力元件包括第一外延掺杂半导体材料的下层，其具有不同于半导体衬底的晶格常数的晶格常数并且在器件沟道中施加应变，以及第二外延掺杂半导体材料的上层。至少一个单层的掺杂剂位于每个嵌入的应力元件的上层内。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式