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21. 发明申请

US20050060428A1 Apparatus and method for caching lookups based upon TCP traffic flow characteristics 有权
标题翻译：基于TCP流量特性来缓存查找的装置和方法
公开(公告)号：US20050060428A1
公开(公告)日：2005-03-17
申请号：US10662007
申请日：2003-09-11
申请人： Everett Corl , Gordon Davis , Clark Jeffries , Natarajan Vaidhyanathan , Colin Verrilli
发明人： Everett Corl , Gordon Davis , Clark Jeffries , Natarajan Vaidhyanathan , Colin Verrilli
IPC分类号： G06F15/173 , H04L12/56 , H04L29/06
CPC分类号： H04L45/00 , H04L69/22
摘要： The classification system of a network device includes a cache in which a mapping between predefined characteristics of TCP/IP packets and associated actions are stored in response to the first “Frequent Flyer” packet in of a session. Selected characteristics from subsequent received packets of that session are correlated with the predefined characteristics and the stored actions are applied to the received packets if the selected characteristics and the predefined characteristics match, thus reducing the processing required for subsequent packets. The packets selected for caching may be data packets. For mismatched characteristics, the full packet search of the classification system is used to determine the action to apply to the received packet.
摘要翻译：网络设备的分类系统包括缓存，其中响应于会话中的第一“频繁传单”分组而存储TCP / IP分组的预定义特性与相关动作之间的映射。如果所选择的特征和预定义的特征匹配，则从该会话的后续接收到的分组中选出的特征与预定义的特征相关联，并且将存储的动作应用于所接收的分组，从而减少后续分组所需的处理。选择用于缓存的数据包可能是数据包。对于不匹配的特征，分类系统的全分组搜索用于确定应用于接收到的分组的动作。

22. 发明申请

US20050050018A1 Data structure supporting session timer and variable aging function including self adjustable 2MSL 审中-公开
标题翻译：数据结构支持会话定时器和可变老化功能，包括自调节2MSL
公开(公告)号：US20050050018A1
公开(公告)日：2005-03-03
申请号：US10654502
申请日：2003-09-03
申请人： Claude Basso , Gordon Davis , Marco Heddes , Dongming Hwang , Colin Verrilli
发明人： Claude Basso , Gordon Davis , Marco Heddes , Dongming Hwang , Colin Verrilli
IPC分类号： G06F17/30
CPC分类号： G06F16/20
摘要： Dynamic data search structures are described that are capable of handling large numbers of active entries and a high rate of additions and deletions of active entries while complying with 2MSL requirements and providing precise time-out capabilities. A free queue which is integrated with the timing loop of session entries provides available sessions for new entries in the search structure and removes obsolete sessions from the tree. Multiples of such timing loops can be used to maintain multiple timing intervals. One such timing loop may contain soft entries still attached to the search structure but which are eligible to be removed and to be reused to accommodate new sessions. A spare buffer pool is also included in the data structure to add and remove buffers to maintain delays.
摘要翻译：描述了能够处理大量活动条目的动态数据搜索结构，以及符合2MSL要求并提供精确超时能力的活动条目的增加和删除的高速率。与会话条目的定时循环集成的空闲队列为搜索结构中的新条目提供可用会话，并从树中删除过时的会话。这种定时循环的倍数可用于维持多个定时间隔。一个这样的定时循环可以包含仍然附着到搜索结构但是有资格被移除并被重新使用以容纳新会话的软条目。数据结构中还包括备用缓冲池，以添加和删除缓冲区以维持延迟。

23. 外观设计

USD411506S Cargo net 失效
公开(公告)号：USD411506S
公开(公告)日：1999-06-29
申请号：US74433
申请日：1997-08-07
申请人： Donald Gordon Davis
设计人： Donald Gordon Davis

24. 发明申请

US20080010390A1 Facilitating Inter-DSP Data Communications 审中-公开
公开(公告)号：US20080010390A1
公开(公告)日：2008-01-10
申请号：US11856509
申请日：2007-09-17
申请人： Youseff Abdelilah , Bartholomew Blaner , Gordon Davis , Jeffrey Derby , Joseph Garvey , Malcolm Ware , Hua Ye
发明人： Youseff Abdelilah , Bartholomew Blaner , Gordon Davis , Jeffrey Derby , Joseph Garvey , Malcolm Ware , Hua Ye
IPC分类号： G06F3/00
CPC分类号： G06F13/28
摘要： A method, computer program product and system for facilitating inter-digital signal processing (DSP) data communications. A direct memory access (DMA) controller may be configured to facilitate transfers of data between a first and a second DSP processor core coupled to the DMA controller. The DMA controller may read a data structure, referred to as a “buffer descriptor block,” to perform the data transfer. The buffer descriptor block may store both a source address and a destination address indicating where the data is to be retrieved and stored. The buffer descriptor block may further store a value, e.g., number of bytes, indicating a size of the data to be transferred. The DMA controller may then transfer the data located at the source address in the first DSP processor core, with a size, e.g., number of bytes, indicated from the buffer descriptor block, to the destination address in the second DSP processor core.

25. 发明申请

US20070079106A1 Method and apparatus for translating a virtual address to a real address using blocks of contiguous page table entries 有权
标题翻译：使用连续页表项的块将虚拟地址翻译成实地址的方法和装置
公开(公告)号：US20070079106A1
公开(公告)日：2007-04-05
申请号：US11232773
申请日：2005-09-22
申请人： Gordon Davis
发明人： Gordon Davis
IPC分类号： G06F12/00 , G06F7/00
CPC分类号： G06F12/1018 , G06F2212/1044
摘要： A page table mechanism translates virtual addresses to real addresses. In a first aspect, page table entries are contained in equal-sized blocks, the entries within each block corresponding to contiguous pages of virtual address space. Preferably, the common high-order portion of the virtual address is contained in segments distributed among multiple page table entries of the block. In a second aspect, the virtual address indexes a binary tree definitional structure. Decode logic traverses a binary tree defined by the definitional structure by testing selective bits of the virtual address to reach a leaf of the binary tree, which defines the location of data defining the real address.
摘要翻译：页表机制将虚拟地址转换为实际地址。在第一方面，页表条目包含在等大小的块中，每个块内的条目对应于虚拟地址空间的连续页面。优选地，虚拟地址的公共高阶部分包含在分块在块的多个表表项之间的段中。在第二方面，虚拟地址索引二进制树定义结构。解码逻辑遍历由定义结构定义的二叉树，通过测试虚拟地址的选择性位以到达二叉树的叶，该二叉树定义了定义实际地址的数据的位置。

26. 发明申请

US20070033303A1 System and method for exchanging messages in a multi-processor environment 失效
标题翻译：用于在多处理器环境中交换消息的系统和方法
公开(公告)号：US20070033303A1
公开(公告)日：2007-02-08
申请号：US11198042
申请日：2005-08-05
申请人： Jeffrey Bridges , Gordon Davis , Thomas Sartorius , Michael Siegel
发明人： Jeffrey Bridges , Gordon Davis , Thomas Sartorius , Michael Siegel
IPC分类号： G06F13/28
CPC分类号： G06F13/28
摘要： A method and system for messaging between processors and co-processors connected through a bus. The method permits a multi-thread system processor to request the services of a processor or co-processor located on the bus. Message control blocks are stored in a memory which identify the physical address of the target processor, as well as a memory location in the memory dedicated to the thread requesting the service. When the system processor requests service of a processor or co-processor, a DCR command is created pointing to the message control block. A message is built from information contained in the message control block or transferred to the processor or co-processor. The return address for the processor or co-processor message is concatenated with the thread number, so that the processor or co-processor can create a return message specifically identifying memory space dedicated to the requesting thread for storage of the response message.
摘要翻译：用于通过总线连接的处理器和协处理器之间的消息传递的方法和系统。该方法允许多线程系统处理器请求位于总线上的处理器或协处理器的服务。消息控制块存储在识别目标处理器的物理地址的存储器中，以及专用于请求服务的线程的存储器中的存储器位置。当系统处理器请求处理器或协处理器的服务时，创建指向消息控制块的DCR命令。消息由消息控制块中包含的信息构建或传送到处理器或协处理器。处理器或协处理器消息的返回地址与线程号连接，使得处理器或协处理器可以创建专用于识别请求线程的存储空间的返回消息以存储响应消息。

27. 发明申请

US20060190613A1 Method, program and system for efficiently hashing packet keys into a firewall connection table 失效
标题翻译：方法，程序和系统，用于将数据包密钥高效地散列到防火墙连接表中
公开(公告)号：US20060190613A1
公开(公告)日：2006-08-24
申请号：US11063950
申请日：2005-02-23
申请人： Everett Corl , Gordon Davis , Clark Jeffries , Steven Perrin , Hiroshi Takada , Victoria Thio
发明人： Everett Corl , Gordon Davis , Clark Jeffries , Steven Perrin , Hiroshi Takada , Victoria Thio
IPC分类号： G06F15/16
CPC分类号： H04L29/12009 , H04L29/12462 , H04L29/12481 , H04L45/745 , H04L61/255 , H04L61/2557
摘要： A method for increasing the capacity of a connection table in a firewall accelerator by means of mapping packets in one session with some common security actions into one table entry. For each of five Network Address Translation (NAT) configurations, a hash function is specified. The hash function takes into account which of four possible arrival types a packet at a firewall accelerator may have. When different arrival types of packets in the same session are processed, two or more arrival types may have the same hash value.
摘要翻译：一种通过将一个会话中的分组映射到一个表条目中的一些常见安全措施来增加防火墙加速器中连接表的容量的方法。对于五种网络地址转换（NAT）配置中的每一种，都指定了一个散列函数。散列函数考虑了防火墙加速器可能具有的四个可能的到达类型中的哪一个。当处理相同会话中的不同到达类型的分组时，两个或多个到达类型可以具有相同的哈希值。

28. 发明申请

US20060039376A1 Method and structure for enqueuing data packets for processing 失效
标题翻译：排队处理数据包的方法和结构
公开(公告)号：US20060039376A1
公开(公告)日：2006-02-23
申请号：US10868725
申请日：2004-06-15
申请人： Claude Basso , Jean Calvignac , Chih-jen Chang , Gordon Davis , Fabrice Verplanken
发明人： Claude Basso , Jean Calvignac , Chih-jen Chang , Gordon Davis , Fabrice Verplanken
IPC分类号： H04L12/56 , H04L12/28
CPC分类号： H04L49/90 , H04L49/9042 , H04L49/9073 , H04L69/22
摘要： A method and structure is provided for buffering data packets having a header and a remainder in a network processor system. The network processor system has a processor on a chip and at least one buffer on the chip. Each buffer on the chip is configured to buffer the header of the packets in a preselected order before execution in the processor, and the remainder of the packet is stored in an external buffer apart from the chip. The method comprises utilizing the header information to identify the location and extent of the remainder of the packet. The entire selected packet is stored in the external buffer when the buffer of the stored header of the given packet is full, and moving only the header of a selected packet stored in the external buffer to the buffer on the chip when the buffer on the chip has space therefor.
摘要翻译：提供了一种在网络处理器系统中缓冲具有报头和余数的数据分组的方法和结构。网络处理器系统在芯片上具有处理器和芯片上的至少一个缓冲器。芯片上的每个缓冲器被配置为在处理器中执行之前以预先选择的顺序缓冲数据包的报头，并且数据包的剩余部分存储在与芯片分离的外部缓冲器中。该方法包括利用报头信息来识别分组的其余部分的位置和范围。当给定分组的存储报头的缓冲器已满时，整个所选分组被存储在外部缓冲器中，并且当芯片上的缓冲器仅将存储在外部缓冲器中的选定分组的报头移动到芯片上的缓冲器时有空间。

29. 发明申请

US20050237939A1 Method and system for managing multi-field classification rules relating to ingress contexts and egress contexts 失效
标题翻译：用于管理与入口上下文和出口上下文相关的多字段分类规则的方法和系统
公开(公告)号：US20050237939A1
公开(公告)日：2005-10-27
申请号：US10832958
申请日：2004-04-27
申请人： Everett Corl , Gordon Davis , Marco Heddes , Piyush Patel , Ravinder Sabhikhi
发明人： Everett Corl , Gordon Davis , Marco Heddes , Piyush Patel , Ravinder Sabhikhi
IPC分类号： G06F15/00 , G06F15/18 , G06F17/00 , G06N5/02 , G06N99/00 , H04J3/14 , H04L12/26 , G06N1/00
CPC分类号： G06N99/005
摘要： The present invention relates to a method and system for managing a plurality of multi-field classification rules. The method includes providing a first table that includes a plurality of entries corresponding to a plurality of rules relating to an ingress context and providing a second table that includes a plurality of entries corresponding to a plurality of rules relating to an egress context. The method also includes utilizing the first table and the second table to identify any rules relating to the ingress context and any rules relating to the egress context that match a search key.
摘要翻译：本发明涉及一种用于管理多个多场分类规则的方法和系统。该方法包括提供第一表格，该第一表格包括对应于与入口上下文有关的多个规则的多个条目，并提供第二表格，该第二表格包括对应于与出口上下文有关的多个规则的多个条目。该方法还包括利用第一表和第二表来识别与入口上下文有关的任何规则以及与搜索关键字匹配的出口上下文相关的任何规则。

30. 发明授权

US06957182B1 Audio coder utilizing repeated transmission of packet portion 有权
标题翻译：音频编码器利用分组部分的重复传输
公开(公告)号：US06957182B1
公开(公告)日：2005-10-18
申请号：US09763466
申请日：1999-09-14
申请人： Rory Stewart Turnbull , Andrew Gordon Davis
发明人： Rory Stewart Turnbull , Andrew Gordon Davis
IPC分类号： G10L19/005 , H04L1/08 , H04L12/56 , G10L19/02
CPC分类号： G10L19/005 , H04L1/08
摘要： A coder generates a first output providing first data from which a decoder can produce a reconstructed signal and a second output providing second, enhancement, data whereby a decoder receiving both the first and second data can produce a higher quality reconstructed signal. Packets of data are assembled for transmission, each packet containing primary data which includes the first data in respect of a temporal portion of the signal and the second data in respect of the same portion of the signal and secondary data which includes the first data in respect of a different temporal portion of the signal.
摘要翻译：编码器产生提供第一数据的第一输出，解码器从该第一数据产生重构信号，第二输出提供第二增强数据，由此接收第一和第二数据的解码器可以产生更高质量的重建信号。数据包组合用于传输，每个数据包包含主数据，其中包括关于信号的时间部分的第一数据和关于信号的相同部分的第二数据以及包括第一数据的次要数据的信号的不同时间部分。

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