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1. 发明申请

US20060200686A1 Power saving methods and apparatus to selectively enable cache bits based on known processor state 有权
标题翻译：省电方法和装置，用于基于已知的处理器状态选择性地启用高速缓存位
公开(公告)号：US20060200686A1
公开(公告)日：2006-09-07
申请号：US11073284
申请日：2005-03-04
申请人： Brian Stempel , James Dieffenderfer , Jeffrey Bridges , Rodney Smith , Thomas Sartorius
发明人： Brian Stempel , James Dieffenderfer , Jeffrey Bridges , Rodney Smith , Thomas Sartorius
IPC分类号： G06F1/26
CPC分类号： G06F9/382 , G06F9/30152 , G06F9/3816 , G06F12/0875 , Y02D10/13
摘要： A processor capable of fetching and executing variable length instructions is described having instructions of at least two lengths. The processor operates in multiple modes. One of the modes restricts instructions that can be fetched and executed to the longer length instructions. An instruction cache is used for storing variable length instructions and their associated predecode bit fields in an instruction cache line and storing the instruction address and processor operating mode state information at the time of the fetch in a tag line. The processor operating mode state information indicates the program specified mode of operation of the processor. The processor fetches instructions from the instruction cache for execution. As a result of an instruction fetch operation, the instruction cache may selectively enable the writing of predecode bit fields in the instruction cache and may selectively enable the reading of predecode bit fields stored in the instruction cache based on the processor state at the time of the fetch.
摘要翻译：描述具有至少两个长度的指令的能够获取和执行可变长度指令的处理器。处理器以多种模式运行。其中一种模式限制了可以获取并执行到较长长度指令的指令。指令高速缓存用于在指令高速缓存行中存储可变长度指令及其相关联的预解码位字段，并且在获取标签行时存储指令地址和处理器操作模式状态信息。处理器操作模式状态信息指示处理器的程序指定的操作模式。处理器从指令缓存器中获取指令以执行。作为指令提取操作的结果，指令高速缓存可以选择性地启用指令高速缓存中的预解码位字段的写入，并且可以基于处理器状态来选择性地启用存储在指令高速缓存中的预解码位字段的读取取。

2. 发明申请

US20070180199A1 Cache locking without interference from normal allocations 有权
标题翻译：缓存锁定，不受正常分配的干扰
公开(公告)号：US20070180199A1
公开(公告)日：2007-08-02
申请号：US11343765
申请日：2006-01-31
申请人： Victor Augsburg , James Dieffenderfer , Jeffrey Bridges , Thomas Sartorius
发明人： Victor Augsburg , James Dieffenderfer , Jeffrey Bridges , Thomas Sartorius
IPC分类号： G06F12/00
CPC分类号： G06F12/0888 , G06F9/30047 , G06F9/3824
摘要： A Block Normal Cache Allocation (BNCA) mode is defined for a processor. In BNCA mode, cache entries may only be allocated by predetermined instructions. Normal memory access instructions (for example, as part of interrupt code) may execute and will retrieve data from main memory in the event of a cache miss; however, these instructions are not allowed to allocate entries in the cache. Only the predetermined instructions (for example, those used to establish locked cache entries) may allocate entries in the cache. When the locked entries are established, the processor exits BNCA mode, and any memory access instruction may allocate cache entries. BNCA mode may be indicated by setting a bit in a configuration register.
摘要翻译：为处理器定义块正常缓存分配（BNCA）模式。在BNCA模式中，缓存条目只能通过预定指令分配。正常存储器访问指令（例如，作为中断代码的一部分）可以执行并且将在高速缓存未命中的情况下从主存储器检索数据; 但是，这些指令不允许在缓存中分配条目。只有预定的指令（例如，用于建立锁定的高速缓存条目的指令）可以在高速缓存中分配条目。当锁定条目建立时，处理器退出BNCA模式，任何存储器访问指令都可以分配高速缓存条目。可以通过在配置寄存器中设置位来指示BNCA模式。

3. 发明申请

US20070005933A1 Preventing multiple translation lookaside buffer accesses for a same page in memory 审中-公开
标题翻译：防止内存中同一页面的多个翻译后备缓冲区访问
公开(公告)号：US20070005933A1
公开(公告)日：2007-01-04
申请号：US11174097
申请日：2005-06-29
申请人： Brian Kopec , Victor Augsburg , James Dieffenderfer , Jeffrey Bridges , Thomas Sartorius
发明人： Brian Kopec , Victor Augsburg , James Dieffenderfer , Jeffrey Bridges , Thomas Sartorius
IPC分类号： G06F12/00
CPC分类号： G06F9/3802 , G06F12/1027 , G06F2212/655 , Y02D10/13
摘要： A processor includes a memory configured to store data in a plurality of pages, a TLB, and a TLB controller. The TLB is configured to search, when accessed by an instruction having a virtual address, for address translation information that allows the virtual address to be translated into a physical address of one of the plurality of pages, and to provide the address translation information if the address translation information is found within the TLB. The TLB controller is configured to determine whether a current instruction and a subsequent instruction seek access to a same page within the plurality of pages, and if so, to prevent TLB access by the subsequent instruction, and to utilize the results of the TLB access of a previous instruction for the current instruction.
摘要翻译：处理器包括被配置为在多个页面中存储数据的存储器，TLB和TLB控制器。 TLB被配置为当通过具有虚拟地址的指令访问时，搜索允许将虚拟地址转换成多个页面之一的物理地址的地址转换信息，并且如果地址转换信息在TLB内找到。 TLB控制器被配置为确定当前指令和后续指令是否寻求对多个页面中的同一页面的访问，如果是，则防止后续指令的TLB访问，并且利用TLB访问的结果当前指令的上一条指令。

4. 发明申请

US20060265572A1 Handling cache miss in an instruction crossing a cache line boundary 有权
标题翻译：处理高速缓存未命中，跨越高速缓存线边界
公开(公告)号：US20060265572A1
公开(公告)日：2006-11-23
申请号：US11132749
申请日：2005-05-18
申请人： Brian Stempel , Jeffrey Bridges , Rodney Smith , Thomas Sartorius
发明人： Brian Stempel , Jeffrey Bridges , Rodney Smith , Thomas Sartorius
IPC分类号： G06F9/30
CPC分类号： G06F9/30149 , G06F9/30047 , G06F9/30181 , G06F9/3802 , G06F9/3814 , G06F9/3816 , G06F9/3875 , G06F12/0875 , G06F12/0886 , G06F2212/655
摘要： A fetch section of a processor comprises an instruction cache and a pipeline of several stages for obtaining instructions. Instructions may cross cache line boundaries. The pipeline stages process two addresses to recover a complete boundary crossing instruction. During such processing, if the second piece of the instruction is not in the cache, the fetch with regard to the first line is invalidated and recycled. On this first pass, processing of the address for the second part of the instruction is treated as a pre-fetch request to load instruction data to the cache from higher level memory, without passing any of that data to the later stages of the processor. When the first line address passes through the fetch stages again, the second line address follows in the normal order, and both pieces of the instruction are can be fetched from the cache and combined in the normal manner.
摘要翻译：处理器的获取部分包括指令高速缓存和用于获取指令的若干级的流水线。指令可能会跨越缓存行边界。流水线处理两个地址以恢复完整的边界交叉指令。在这种处理过程中，如果第二条指令不在高速缓存中，则关于第一行的提取将被无效再循环。在该第一遍中，对于指令的第二部分的地址的处理被视为从高级存储器将指令数据加载到高速缓存的预取请求，而不将该数据传递到处理器的后期。当第一行地址再次通过读取级时，第二行地址以正常顺序跟随，并且可以从高速缓存中取出两条指令并以正常方式进行组合。

5. 发明申请

US20060212675A1 Method and system for optimizing translation lookaside buffer entries 有权
标题翻译：优化翻译后备缓冲区条目的方法和系统
公开(公告)号：US20060212675A1
公开(公告)日：2006-09-21
申请号：US11083691
申请日：2005-03-17
申请人： Thomas Sartorius , Jeffrey Bridges , James Dieffenderfer , Victor Augsburg
发明人： Thomas Sartorius , Jeffrey Bridges , James Dieffenderfer , Victor Augsburg
IPC分类号： G06F12/00
CPC分类号： G06F12/1027 , G06F2212/652
摘要： A system for optimizing translation lookaside buffer entries is provided. The system includes a translation lookaside buffer configured to store a number of entries, each entry having a size attribute, each entry referencing a corresponding page, and control logic configured to modify the size attribute of an existing entry in the translation lookaside buffer if a new page is contiguous with an existing page referenced by the existing entry. The existing entry after having had its size attribute modified references a consolidated page comprising the existing page and the new page.
摘要翻译：提供了一种用于优化翻译后备缓冲区条目的系统。该系统包括翻译后备缓冲器，其被配置为存储多个条目，每个条目具有大小属性，每个条目引用对应的页面，以及控制逻辑，被配置为修改翻译后备缓冲器中现有条目的大小属性，如果新的页面与现有条目引用的现有页面是连续的。修改其大小属性后的现有条目引用包含现有页面和新页面的合并页面。

6. 发明申请

US20060200654A1 Stop waiting for source operand when conditional instruction will not execute 审中-公开
标题翻译：当条件指令不执行时，停止等待源操作数
公开(公告)号：US20060200654A1
公开(公告)日：2006-09-07
申请号：US11073165
申请日：2005-03-04
申请人： James Dieffenderfer , Jeffrey Bridges , Michael McIlvaine , Thomas Sartorius
发明人： James Dieffenderfer , Jeffrey Bridges , Michael McIlvaine , Thomas Sartorius
IPC分类号： G06F9/44
CPC分类号： G06F9/3824 , G06F9/3001 , G06F9/30072
摘要： The delay of non-executing conditional instructions, that would otherwise be imposed while waiting for late operand data, is alleviated based on an early recognition that such instructions will not execute on the current pass through a pipeline processor. At an appropriate point prior to execution, a determination regarding the condition is made. If the condition is such that the instruction will not execute on this pass through the pipeline, the hold with regard to the conditional instruction may be terminated, that is to say skipped or stopped prior to completion of receiving all the associated operand data. Flow of the non-executing instruction through the pipeline, for example, need not wait for an earlier instruction to compute and write source operand data for use by the conditional instruction.
摘要翻译：基于早期识别这种指令将不会在当前通过流水线处理器的过程中执行的情况下，缓解不执行条件指令的延迟，否则将等待后期操作数数据施加。在执行之前的适当时刻，作出关于条件的确定。如果条件使得指令不会在通过流水线的该通过上执行，关于条件指令的保持可以被终止，也就是说在完成接收所有相关联的操作数数据之前被跳过或停止。例如，通过流水线的不执行指令的流程不需要等待较早的指令来计算和写入源操作数数据以供条件指令使用。

7. 发明申请

US20060190711A1 Method and apparatus for managing a return stack 有权
标题翻译：用于管理返回堆栈的方法和装置
公开(公告)号：US20060190711A1
公开(公告)日：2006-08-24
申请号：US11061975
申请日：2005-02-18
申请人： Rodney Smith , James Dieffenderfer , Jeffrey Bridges , Thomas Sartorius
发明人： Rodney Smith , James Dieffenderfer , Jeffrey Bridges , Thomas Sartorius
IPC分类号： G06F9/00
CPC分类号： G06F9/3806 , G06F9/30054 , G06F9/4486
摘要： A processor includes a return stack circuit used for predicting procedure return addresses for instruction pre-fetching, wherein a return stack controller determines the number of return levels associated with a given return instruction, and pops that number of return addresses from the return stack. Popping multiple return addresses from the return stack permits the processor to pre-fetch the return address of the original calling procedure in a chain of successive procedure calls. In one embodiment, the return stack controller reads the number of return levels from a value embedded in the return instruction. A complementary compiler calculates the return level values for given return instructions and embeds those values in them at compile-time. In another embodiment, the return stack circuit dynamically tracks the number of return levels by counting the procedure calls (branches) in a chain of successive procedure calls.
摘要翻译：处理器包括用于预测用于指令预取的过程返回地址的返回堆栈电路，其中返回堆栈控制器确定与给定返回指令相关联的返回电平的数量，并且从返回堆栈中弹出该返回地址的数量。从返回堆栈弹出多个返回地址允许处理器在连续的过程调用链中预取原始调用过程的返回地址。在一个实施例中，返回堆栈控制器从嵌入在返回指令中的值读取返回电平的数量。补充编译器计算给定返回指令的返回值，并在编译时嵌入这些值。在另一个实施例中，返回堆栈电路通过对连续过程调用链中的过程调用（分支）进行计数来动态地跟踪返回电平的数量。

8. 发明申请

US20060184738A1 Unaligned memory access prediction 有权
标题翻译：未对齐的内存访问预测
公开(公告)号：US20060184738A1
公开(公告)日：2006-08-17
申请号：US11062221
申请日：2005-02-17
申请人： Jeffrey Bridges , Victor Augsburg , James Dieffenderfer , Thomas Sartorius
发明人： Jeffrey Bridges , Victor Augsburg , James Dieffenderfer , Thomas Sartorius
IPC分类号： G06F9/44
CPC分类号： G06F9/30043 , G06F9/30145 , G06F9/30189 , G06F9/3824 , G06F9/3832 , G06F9/3855
摘要： In an instruction execution pipeline, the misalignment of memory access instructions is predicted. Based on the prediction, an additional micro-operation is generated in the pipeline prior to the effective address generation of the memory access instruction. The additional micro-operation accesses the memory falling across a predetermined address boundary. Predicting the misalignment and generating a micro-operation early in the pipeline ensures that sufficient pipeline control resources are available to generate and track the additional micro-operation, avoiding a pipeline flush if the resources are not available at the time of effective address generation. The misalignment prediction may employ known conditional branch prediction techniques, such as a flag, a bimodal counter, a local predictor, a global predictor, and combined predictors. A misalignment predictor may be enabled or biased by a memory access instruction flag or misaligned instruction type.
摘要翻译：在指令执行流水线中，预测存储器访问指令的未对准。基于该预测，在存储器访问指令的有效地址生成之前，在流水线中生成附加的微操作。附加的微操作访问落在预定地址边界上的存储器。预测未对准并在管道早期生成微操作确保足够的流水线控制资源可用于生成和跟踪附加的微操作，如果资源在有效地址生成时不可用，则避免管道冲洗。不对准预测可以使用已知的条件分支预测技术，例如标志，双模计数器，局部预测器，全局预测器和组合预测器。未对准预测器可能被存储器访问指令标志或未对准指令类型使能或偏置。

9. 发明申请

US20070174592A1 Early conditional selection of an operand 有权
标题翻译：早期有条件地选择操作数
公开(公告)号：US20070174592A1
公开(公告)日：2007-07-26
申请号：US11336357
申请日：2006-01-20
申请人： James Dieffenderfer , Jeffrey Bridges , Michael McIlvaine , Thomas Sartorius
发明人： James Dieffenderfer , Jeffrey Bridges , Michael McIlvaine , Thomas Sartorius
IPC分类号： G06F15/00 , G06F9/44 , G06F7/38
CPC分类号： G06F9/30072 , G06F9/30036 , G06F9/30094 , G06F9/3016 , G06F9/30167
摘要： Delays due to waiting for operands that will not be used by a select operand instruction, are alleviated based on an early recognition that such operand data is not required in order to complete the processing of the select operand instruction. At appropriate points prior to execution, determinations are made regarding a selection criterion or criteria specified by the select operand instruction, conditions that affect the selection criteria, and the availability of operands. A hold circuit uses the determinations to control the activation and release of a hold signal that controls processor pipeline stalls. A stall required to wait for operand data is skipped or a stall is terminated early, if the selected operand is available even though the other operand, that will not be used, is not available. A stall due to waiting for operands is maintained until the selection criteria is met and the selected operand is fetched and made available.
摘要翻译：由于等待操作数不被选择操作数指令使用的延迟，基于早期识别，为了完成选择操作数指令的处理而不需要这种操作数数据，可以减轻延迟。在执行之前的适当点，确定关于由选择操作数指令指定的选择标准或标准，影响选择标准的条件以及操作数的可用性。保持电路使用该确定来控制控制处理器流水线停顿的保持信号的激活和释放。如果所选择的操作数可用，即使不使用另一个操作数不可用，则跳过等待操作数数据所需的档位或提前终止档位。维持由于等待操作数而导致的停顿，直到满足选择标准并且所选择的操作数被获取并可用。

10. 发明申请

US20070097722A1 Circuit and method for subdividing a CAMRAM bank by controlling a virtual ground 有权
标题翻译：通过控制虚拟地面对CAMRAM组进行细分的电路和方法
公开(公告)号：US20070097722A1
公开(公告)日：2007-05-03
申请号：US11262062
申请日：2005-10-28
申请人： Michael Phan , Chiaming Chai , Jeffrey Bridges , Jeffrey Fischer
发明人： Michael Phan , Chiaming Chai , Jeffrey Bridges , Jeffrey Fischer
IPC分类号： G11C15/00
CPC分类号： G11C15/00 , G11C8/12 , G11C15/04
摘要： A CAM bank is functionally divided into two or more sub-banks, without replication CAM driver circuits, by disabling all match line discharge circuits in the bank, and selectively enabling the discharge circuits in comprising sub-banks. At least one selectively actuated switching circuit is interposed between the virtual ground node of each discharging comparator in the discharge circuit of a sub-bank and circuit ground. When the switching circuit is in a non-conductive state, the virtual ground node is maintained at a voltage level sufficiently above circuit ground to preclude discharging a connected match line within the CAM access time. When the switching circuit is placed in a conductive state, the virtual ground node is pulled to circuit ground and the connected match line may be discharged by a miscompare. Control signals, which may be decode from address bits, are distributed to the switching circuits to defined the CAM sub-banks.
摘要翻译：通过禁用组中的所有匹配线放电电路，并且选择性地使能包括子组的放电电路，CAM组在功能上被划分为两个或更多个子组，而不需要复制CAM驱动器电路。至少一个选择性致动的切换电路插入在子组的放电电路中的每个放电比较器的虚拟接地节点和电路接地之间。当开关电路处于非导通状态时，虚拟接地节点保持在足够高于电路接地的电压电平，以防止在CAM访问时间内放电连接的匹配线。当开关电路处于导通状态时，虚拟接地节点被拉到电路接地，并且连接的匹配线可能被误比较地放电。可以从地址位解码的控制信号被分配到切换电路以定义CAM子库。

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