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1. 发明授权

US08726132B2 Checksum verification accelerator 失效
标题翻译：校验和验证加速器
公开(公告)号：US08726132B2
公开(公告)日：2014-05-13
申请号：US13302688
申请日：2011-11-22
申请人： Francois Abel , Claude Basso , Jean L. Calvignac , Natarajan Vaidhyanathan , Fabrice Jean Verplanken
发明人： Francois Abel , Claude Basso , Jean L. Calvignac , Natarajan Vaidhyanathan , Fabrice Jean Verplanken
IPC分类号： H03M13/00
CPC分类号： H04L1/0079 , H04L1/0061 , H04L1/0072
摘要： Disclosed is a method and system for validating a data packet by a network processor supporting a first network protocol and a second network protocol and utilizing shared hardware. The network processor receives a data packet; identifies a network packet protocol for the data packet; and processes the data packet according to the network packet protocol comprising: updating a first register with a first partial packet length specific to the first network protocol; updating a second register with a second partial packet length specific to the second network protocol; and updating a third register with a first checksum computed from fields independent of the network protocol. The system produces a second checksum utilizing a function that combines values from the first register, the second register, and the third register. The system validates the data packet by comparing the data packet checksum to the second checksum.
摘要翻译：公开了一种用于通过支持第一网络协议和第二网络协议的网络处理器来验证数据分组并利用共享硬件的方法和系统。网络处理器接收数据包; 识别数据包的网络包协议; 并根据网络分组协议对数据分组进行处理，包括：以第一网络协议特有的第一部分分组长度更新第一寄存器; 用第二网络协议特有的第二部分分组长度更新第二寄存器; 以及用独立于网络协议的字段计算的具有第一校验和的更新第三寄存器。该系统利用组合来自第一寄存器，第二寄存器和第三寄存器的值的函数产生第二校验和。系统通过将数据包校验和与第二个校验和进行比较来验证数据包。

2. 发明授权

US08619782B2 Bidirectional packet flow transformation 失效
标题翻译：双向分组流转换
公开(公告)号：US08619782B2
公开(公告)日：2013-12-31
申请号：US13325624
申请日：2011-12-14
申请人： Claude Basso , Jean L Calvignac , Natarajan Vaidhyanathan , Fabrice Verplanken
发明人： Claude Basso , Jean L Calvignac , Natarajan Vaidhyanathan , Fabrice Verplanken
IPC分类号： H04L12/28 , H04L12/56 , G06F7/00 , G06F17/00
CPC分类号： H04L29/0653 , H04L45/50 , H04L47/2441
摘要： A network packet includes a packet key that includes one or more source-destination field pairs that each include a source field and a destination field. For each selected source-destination field pair, first and second sections are selected in the packet key. A source field value is extracted from the source field and a destination field value is extracted from the destination field. For each source bit of the source field value: a destination bit is selected from the destination field; an OR logic function is applied to the source bit and the destination bit to generate a first resulting value is stored at the same bit position as the source bit in the first section; an AND logic function is applied to the source bit and the destination bit to generate a second resulting value stored at the same bit position as the source bit in the second section.
摘要翻译：网络分组包括分组密钥，其包括一个或多个源 - 目的地字段对，每个源对目的字段对都包括源字段和目的地字段。对于每个选择的源 - 目的地字段对，在分组密钥中选择第一和第二部分。从源字段提取源字段值，并从目标字段提取目的字段值。对于源字段值的每个源位：从目标字段中选择目标位; 将OR逻辑功能应用于源位，并将目标位产生为第一结果值，存储在与第一段中的源位相同的位位置; 将AND逻辑功能应用于源位和目标位，以产生存储在与第二部分中的源位相同的位位置处的第二个结果值。

3. 发明申请

US20130182707A1 MANAGING A GLOBAL FORWARDING TABLE IN A DISTRIBUTED SWITCH 有权
标题翻译：在分布式交换机中管理全局前向表
公开(公告)号：US20130182707A1
公开(公告)日：2013-07-18
申请号：US13352973
申请日：2012-01-18
申请人： Debra L. Angst , Claude Basso , Josep Cors , Rekha Mundhra , Natarajan Vaidhyanathan
发明人： Debra L. Angst , Claude Basso , Josep Cors , Rekha Mundhra , Natarajan Vaidhyanathan
IPC分类号： H04L12/56
CPC分类号： H04L12/44 , H04L12/18 , H04L12/4625 , H04L41/12 , H04L45/02 , H04L45/16 , H04L45/54 , H04L47/15 , H04L49/201 , H04L49/65 , H04L69/28
摘要： Apparatuses and methods to manage a global forwarding table in a distributed switch are provided. A particular method may include managing a global forwarding table in a distributed switch. The distributed switch may include a plurality of switch forwarding units. The method may start a timer for an entry in the global forwarding table, and the entry may include a multicast destination address and corresponding multicast membership information. The method may also, in response to expiration of the timer of the entry, check at least one hit status to determine whether at least one switch forwarding unit of the plurality of switch forwarding units has forwarded multicast data to the corresponding multicast membership information of the multicast destination address of the entry. The method may further determine whether the entry is a cast-out candidate based on the hit status.
摘要翻译：提供了在分布式交换机中管理全局转发表的设备和方法。特定方法可以包括管理分布式交换机中的全局转发表。分布式交换机可以包括多个交换机转发单元。该方法可以启动全局转发表中的条目的定时器，并且该条目可以包括多播目的地地址和相应的多播成员资格信息。该方法还可以响应于条目的定时器的到期来检查至少一个命中状态，以确定多个交换机转发单元中的至少一个交换机转发单元是否已经将多播数据转发到相应的组播成员信息组播目的地址。该方法还可以基于命中状态进一步确定该条目是否是舍弃候选者。

4. 发明申请

US20120218885A1 SELECTION OF RECEIVE-QUEUE BASED ON PACKET ATTRIBUTES 失效
标题翻译：基于分组属性选择接收队列
公开(公告)号：US20120218885A1
公开(公告)日：2012-08-30
申请号：US13466914
申请日：2012-05-08
申请人： Francois Abel , Claude Basso , Jean L. Calvignac , Natarajan Vaidhyanathan , Fabrice Verplanken , Colin B. Verrilli
发明人： Francois Abel , Claude Basso , Jean L. Calvignac , Natarajan Vaidhyanathan , Fabrice Verplanken , Colin B. Verrilli
IPC分类号： H04L12/24
CPC分类号： H04L47/6215
摘要： According to embodiments of the invention, there is provided a method for operating a network processor. The network processor receiving a first data packet in a stream of data packets and a set of receive-queues adapted to store receive data packets. The network processor processing the first data packet by reading a flow identification in the first data packet; determining a quality of service for the first data packet; mapping the flow identification and the quality of service into an index for selecting a first receive-queue for routing the first data packet; and utilizing the index to route the first data packet to the first receive-queue.
摘要翻译：根据本发明的实施例，提供了一种用于操作网络处理器的方法。网络处理器接收数据包流中的第一数据包和适于存储接收数据包的一组接收队列。网络处理器通过读取第一数据分组中的流标识来处理第一数据分组; 确定第一数据分组的服务质量; 将流标识和服务质量映射到用于选择用于路由第一数据分组的第一接收队列的索引; 以及利用所述索引将所述第一数据分组路由到所述第一接收队列。

5. 发明申请

US20120204190A1 Merging Result from a Parser in a Network Processor with Result from an External Coprocessor 失效
标题翻译：从具有外部协处理器结果的网络处理器中的解析器合并结果
公开(公告)号：US20120204190A1
公开(公告)日：2012-08-09
申请号：US13365778
申请日：2012-02-03
申请人： Claude Basso , Jean L. Calvignac , Chih-jen Chang , Philippe Damon , Natarajan Vaidhyanathan , Fabrice J. Verplanken , Colin B. Verrilli
发明人： Claude Basso , Jean L. Calvignac , Chih-jen Chang , Philippe Damon , Natarajan Vaidhyanathan , Fabrice J. Verplanken , Colin B. Verrilli
IPC分类号： G06F9/46
CPC分类号： G06F9/546 , G06F9/544
摘要： A mechanism is provided for merging in a network processor results from a parser and results from an external coprocessor providing processing support requested by said parser. The mechanism enqueues in a result queue both parser results needing to be merged with a coprocessor result and parser results which have no need to be merged with a coprocessor result. An additional queue is used to enqueue the addresses of the result queue where the parser results are stored. The result from the coprocessor is received in a simple response register. The coprocessor result is read by the result queue management logic from the response register and merged to the corresponding incomplete parser result read in the result queue at the address enqueued in the additional queue.
摘要翻译：提供了一种机制，用于在来自解析器的网络处理器结果和来自提供由所述解析器请求的处理支持的外部协处理器的结果中合并。结果队列中的机制排队，解析器结果需要与协处理器结果合并，并且不需要与协处理器结果合并的解析器结果。使用一个附加队列来排列存储解析器结果的结果队列的地址。协处理器的结果是在简单的响应寄存器中接收的。协处理器结果由响应寄存器的结果队列管理逻辑读取，并被合并到在附加队列中排队的地址的结果队列中读取的相应的不完整解析器结果。

6. 发明申请

US20120192190A1 Host Ethernet Adapter for Handling Both Endpoint and Network Node Communications 失效
标题翻译：用于处理端点和网络节点通信的主机以太网适配器
公开(公告)号：US20120192190A1
公开(公告)日：2012-07-26
申请号：US13011663
申请日：2011-01-21
申请人： Claude Basso , Jean L. Calvignac , Chih-jen Chang , Philippe Damon , Natarajan Vaidhyanathan , Fabrice J. Verplanken , Colin B. Verrilli
发明人： Claude Basso , Jean L. Calvignac , Chih-jen Chang , Philippe Damon , Natarajan Vaidhyanathan , Fabrice J. Verplanken , Colin B. Verrilli
IPC分类号： G06F9/46
CPC分类号： G06F15/1735
摘要： A host Ethernet adapter (HEA) and method of managing network communications is provided. The HEA includes a host interface configured for communication with a multi-core processor over a processor bus. The host interface comprises a receive processing element including a receive processor, a receive buffer and a scheduler for dispatching packets from the receive buffer to the receive processor; a send processing element including a send processor and a send buffer; and a completion queue scheduler (CQS) for dispatching completion queue elements (CQE) from the head of the completion queue (CQ) to threads of the multi-core processor in a network node mode. The method comprises operatively coupling an Ethernet adapter to a multi-core processor system via a processor bus, selectively assigning a first plurality of packets to a first queue pair for servicing in an endpoint mode, running a device driver on the multi-core processing system, the device driver controlling the servicing of the first queue pair by dispatching the first plurality of packets to only one processor core of the multi-core processor system, selectively assigning a second plurality of packets to a second queue pair for servicing in a network node mode; and the Ethernet adapter controlling the servicing of the second queue pair by dispatching the second plurality of packets to multiple processor threads.
摘要翻译：提供主机以太网适配器（HEA）和管理网络通信的方法。 HEA包括被配置为通过处理器总线与多核处理器进行通信的主机接口。所述主机接口包括接收处理元件，所述接收处理元件包括接收处理器，接收缓冲器和用于从所述接收缓冲器向所述接收处理器分发分组的调度器; 包括发送处理器和发送缓冲器的发送处理元件; 以及用于从完成队列（CQ）的头部将网络节点模式中的多核处理器的线程调度完成队列元素（CQE）的完成队列调度器（CQS）。该方法包括经由处理器总线可操作地将以太网适配器耦合到多核处理器系统，选择性地将第一多个分组分配到第一队列对以在端点模式下进行服务，在多核处理系统上运行设备驱动程序所述设备驱动程序通过将所述第一多个分组分派到所述多核处理器系统的一个处理器核心来控制所述第一队列对的服务，选择性地将第二多个分组分配给第二队列对以在网络节点中进行服务模式; 以及所述以太网适配器通过将所述第二多个分组分派到多个处理器线程来控制所述第二队列对的服务。

7. 发明申请

US20120155267A1 SELECTION OF RECEIVE-QUEUE BASED ON PACKET ATTRIBUTES 审中-公开
标题翻译：基于分组属性选择接收队列
公开(公告)号：US20120155267A1
公开(公告)日：2012-06-21
申请号：US13302285
申请日：2011-11-22
申请人： Francois Abel , Claude Basso , Jean L. Calvignac , Natarajan Vaidhyanathan , Fabrice Verplanken , Colin B. Verrilli
发明人： Francois Abel , Claude Basso , Jean L. Calvignac , Natarajan Vaidhyanathan , Fabrice Verplanken , Colin B. Verrilli
IPC分类号： H04L12/26
CPC分类号： H04L47/6215
摘要： According to embodiments of the invention, there is provided a method, a system, and a computer program product for operating a network processor. The network processor processing a received data packet by reading a flow identification in the data packet; determining a quality of service criteria (QoSC) for the data packet; mapping the flow identification and the QoSC into an index for selecting a receive-queue for routing the data packet; and utilizing the index to route the data packet to the receive-queue.
摘要翻译：根据本发明的实施例，提供了一种用于操作网络处理器的方法，系统和计算机程序产品。网络处理器通过读取数据分组中的流标识来处理接收到的数据分组; 确定数据包的服务质量标准（QoSC）; 将流标识和QoSC映射到用于选择用于路由数据分组的接收队列的索引; 并利用索引将数据包路由到接收队列。

8. 发明申请

US20120151307A1 CHECKSUM VERIFICATION ACCELERATOR 失效
标题翻译：检查验证加速器
公开(公告)号：US20120151307A1
公开(公告)日：2012-06-14
申请号：US13302688
申请日：2011-11-22
申请人： Francois Abel , Claude Basso , Jean L. Calvignac , Natarajan Vaidhyanathan , Fabrice Verplanken
发明人： Francois Abel , Claude Basso , Jean L. Calvignac , Natarajan Vaidhyanathan , Fabrice Verplanken
IPC分类号： G06F11/00
CPC分类号： H04L1/0079 , H04L1/0061 , H04L1/0072
摘要： Disclosed is a method and system for validating a data packet by a network processor supporting a first network protocol and a second network protocol and utilizing shared hardware. The network processor receives a data packet; identifies a network packet protocol for the data packet; and processes the data packet according to the network packet protocol comprising: updating a first register with a first partial packet length specific to the first network protocol; updating a second register with a second partial packet length specific to the second network protocol; and updating a third register with a first checksum computed from fields independent of the network protocol. The system produces a second checksum utilizing a function that combines values from the first register, the second register, and the third register. The system validates the data packet by comparing the data packet checksum to the second checksum.
摘要翻译：公开了一种用于通过支持第一网络协议和第二网络协议的网络处理器来验证数据分组并利用共享硬件的方法和系统。网络处理器接收数据包; 识别数据包的网络包协议; 并根据网络分组协议对数据分组进行处理，包括：以第一网络协议特有的第一部分分组长度更新第一寄存器; 用第二网络协议特有的第二部分分组长度更新第二寄存器; 以及用独立于网络协议的字段计算的具有第一校验和的更新第三寄存器。该系统利用组合来自第一寄存器，第二寄存器和第三寄存器的值的函数产生第二校验和。系统通过将数据包校验和与第二个校验和进行比较来验证数据包。

9. 发明授权

US07715428B2 Multicore communication processing 有权
标题翻译：多核通讯处理
公开(公告)号：US07715428B2
公开(公告)日：2010-05-11
申请号：US11669419
申请日：2007-01-31
申请人： Claude Basso , Jean L. Calvignac , Chih-jen Chang , Philippe Damon , Herman D. Dierks, Jr. , Christoph Raisch , Jan-Bernd Themann , Natarajan Vaidhyanathan , Fabrice J. Verplanken , Colin B. Verrilli
发明人： Claude Basso , Jean L. Calvignac , Chih-jen Chang , Philippe Damon , Herman D. Dierks, Jr. , Christoph Raisch , Jan-Bernd Themann , Natarajan Vaidhyanathan , Fabrice J. Verplanken , Colin B. Verrilli
IPC分类号： H04L12/66 , H04J3/16 , H04J3/22
CPC分类号： H04L47/50
摘要： Mechanisms for processing of communications between data processing devices are provided. With the mechanisms of the illustrative embodiments, a set of techniques that enables sustaining media speed by distributing transmit and receive-side processing over multiple processing cores is provided. In addition, these techniques also enable designing multi-threaded network interface controller (NIC) hardware that efficiently hides the latency of direct memory access (DMA) operations associated with data packet transfers over an input/output (I/O) bus. Multiple processing cores may operate concurrently using separate instances of a communication protocol stack and device drivers to process data packets for transmission with separate hardware implemented send queue managers in a network adapter processing these data packets for transmission. Multiple hardware receive packet processors in the network adapter may be used, along with a flow classification engine, to route received data packets to appropriate receive queues and processing cores for processing.
摘要翻译：提供了用于处理数据处理设备之间的通信的机制。利用说明性实施例的机制，提供了一组通过在多个处理核上分发发送和接收侧处理来维持媒体速度的技术。此外，这些技术还可以设计出多线程网络接口控制器（NIC）硬件，可有效地隐藏通过输入/输出（I / O）总线传输数据分组的直接存储器访问（DMA）操作的延迟。多个处理核心可以使用通信协议栈和设备驱动程序的单独实例同时运行，以处理用于传输的数据分组，其中单独的硬件实现了处理这些数据分组以进行传输的网络适配器中的发送队列管理器。可以使用网络适配器中的多个硬件接收分组处理器以及流分类引擎将接收到的数据分组路由到适当的接收队列和处理核心进行处理。

10. 发明申请

US20090103536A1 Method and System for Reducing Look-Up Time in Packet Forwarding on Computer Networks 有权
标题翻译：减少计算机网络中数据包转发查找时间的方法和系统
公开(公告)号：US20090103536A1
公开(公告)日：2009-04-23
申请号：US11780444
申请日：2007-07-19
申请人： Claude Basso , Bay Van Nguyen , Max Robert Povse , Natarajan Vaidhyanathan , Colin Beaton Verrilli
发明人： Claude Basso , Bay Van Nguyen , Max Robert Povse , Natarajan Vaidhyanathan , Colin Beaton Verrilli
IPC分类号： H04L12/56
CPC分类号： H04L29/00 , H04L45/742
摘要： A method and system for reducing the lookup time in packet forwarding on computer networks. A first lookup is performed in a memory tree to find a first protocol forwarding entry in the memory tree. The forwarding entry includes first protocol (e.g., EGP) information and cached associated second protocol (e.g., IGP) information. Both EGP and IGP information are retrievable with the first lookup and used in the determination of an EGP route for the data packet. If the cached IGP information has been invalidated due to address updates, a second lookup can be performed to find an original IGP entry in the memory tree, the information from which can be cached in the EGP forwarding entry if a background maintenance task has finished designating all the EGP entries as having out-of-date caches.
摘要翻译：一种用于减少计算机网络上的分组转发中的查找时间的方法和系统。在存储器树中执行第一次查找以在存储器树中找到第一协议转发条目。转发条目包括第一协议（例如，EGP）信息和缓存的相关联的第二协议（例如，IGP）信息。 EGP和IGP信息都可以通过第一次查找进行检索，并用于确定数据包的EGP路由。如果缓存的IGP信息由于地址更新而被无效，则可以执行第二次查找以在存储器树中找到原始IGP条目，如果后台维护任务已经完成指定，则可以将其从EGP转发条目缓存到其中所有EGP条目都具有过期缓存。

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