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1. 发明申请

US20080072005A1 Facilitating Inter-DSP Data Communications 失效
标题翻译：促进DSP间数据通信
公开(公告)号：US20080072005A1
公开(公告)日：2008-03-20
申请号：US11944028
申请日：2007-11-21
申请人： Youseff Abdelilah , Bartholomew Blaner , Gordon Davis , Jeffrey Derby , Joseph Garvey , Malcolm Ware , Hua Ye
发明人： Youseff Abdelilah , Bartholomew Blaner , Gordon Davis , Jeffrey Derby , Joseph Garvey , Malcolm Ware , Hua Ye
IPC分类号： G06F12/02
CPC分类号： G06F13/28
摘要： A method, computer program product and system for facilitating inter-digital signal processing (DSP) data communications. A direct memory access (DMA) controller may be configured to facilitate transfers of data between a first and a second DSP processor core coupled to the DMA controller. The DMA controller may read a data structure, referred to as a “buffer descriptor block,” to perform the data transfer. The buffer descriptor block may store both a source address and a destination address indicating where the data is to be retrieved and stored. The buffer descriptor block may further store a value, e.g., number of bytes, indicating a size of the data to be transferred. The DMA controller may then transfer the data located at the source address in the first DSP processor core, with a size, e.g., number of bytes, indicated from the buffer descriptor block, to the destination address in the second DSP processor core.
摘要翻译：一种用于促进数字间数字信号处理（DSP）数据通信的方法，计算机程序产品和系统。直接存储器访问（DMA）控制器可以被配置为便于在耦合到DMA控制器的第一和第二DSP处理器核之间传输数据。 DMA控制器可以读取被称为“缓冲器描述符块”的数据结构来执行数据传送。缓冲器描述符块可以存储指示要检索和存储数据的源地址和目的地址。缓冲器描述符块还可以存储指示要传送的数据的大小的值，例如字节数。然后，DMA控制器可以将位于第一DSP处理器核心中的源地址处的数据以从缓冲器描述符块指示的大小（例如，字节数）传送到第二DSP处理器核心中的目的地地址。

2. 发明申请

US20050188129A1 Facilitating inter-DSP data communications 失效
标题翻译：促进DSP间数据通信
公开(公告)号：US20050188129A1
公开(公告)日：2005-08-25
申请号：US10783757
申请日：2004-02-20
申请人： Youseff Abdelilah , Bartholomew Blaner , Gordon Davis , Jeffrey Derby , Joseph Garvey , Malcolm Ware , Hua Ye
发明人： Youseff Abdelilah , Bartholomew Blaner , Gordon Davis , Jeffrey Derby , Joseph Garvey , Malcolm Ware , Hua Ye
IPC分类号： G06F3/00 , G06F13/28 , H04L29/06
CPC分类号： G06F13/28
摘要： A method, computer program product and system for facilitating inter-digital signal processing (DSP) data communications. A direct memory access (DMA) controller may be configured to facilitate transfers of data between a first and a second DSP processor core coupled to the DMA controller. The DMA controller may read a data structure, referred to as a “buffer descriptor block,” to perform the data transfer. The buffer descriptor block may store both a source address and a destination address indicating where the data is to be retrieved and stored. The buffer descriptor block may further store a value, e.g., number of bytes, indicating a size of the data to be transferred. The DMA controller may then transfer the data located at the source address in the first DSP processor core, with a size, e.g., number of bytes, indicated from the buffer descriptor block, to the destination address in the second DSP processor core.
摘要翻译：一种用于促进数字间数字信号处理（DSP）数据通信的方法，计算机程序产品和系统。直接存储器访问（DMA）控制器可以被配置为便于在耦合到DMA控制器的第一和第二DSP处理器核之间传输数据。 DMA控制器可以读取被称为“缓冲器描述符块”的数据结构来执行数据传送。缓冲器描述符块可以存储指示要检索和存储数据的源地址和目的地址。缓冲器描述符块还可以存储指示要传送的数据的大小的值，例如字节数。然后，DMA控制器可以将位于第一DSP处理器核心中的源地址处的数据以从缓冲器描述符块指示的大小（例如，字节数）传送到第二DSP处理器核心中的目的地地址。

3. 发明申请

US20080010390A1 Facilitating Inter-DSP Data Communications 审中-公开
公开(公告)号：US20080010390A1
公开(公告)日：2008-01-10
申请号：US11856509
申请日：2007-09-17
申请人： Youseff Abdelilah , Bartholomew Blaner , Gordon Davis , Jeffrey Derby , Joseph Garvey , Malcolm Ware , Hua Ye
发明人： Youseff Abdelilah , Bartholomew Blaner , Gordon Davis , Jeffrey Derby , Joseph Garvey , Malcolm Ware , Hua Ye
IPC分类号： G06F3/00
CPC分类号： G06F13/28
摘要： A method, computer program product and system for facilitating inter-digital signal processing (DSP) data communications. A direct memory access (DMA) controller may be configured to facilitate transfers of data between a first and a second DSP processor core coupled to the DMA controller. The DMA controller may read a data structure, referred to as a “buffer descriptor block,” to perform the data transfer. The buffer descriptor block may store both a source address and a destination address indicating where the data is to be retrieved and stored. The buffer descriptor block may further store a value, e.g., number of bytes, indicating a size of the data to be transferred. The DMA controller may then transfer the data located at the source address in the first DSP processor core, with a size, e.g., number of bytes, indicated from the buffer descriptor block, to the destination address in the second DSP processor core.

4. 发明申请

US20060143708A1 System and method for detecting keyboard logging 有权
公开(公告)号：US20060143708A1
公开(公告)日：2006-06-29
申请号：US11021139
申请日：2004-12-23
申请人： Joseph Garvey , Kevin Himberger , Clark Jeffries , Mohammad Peyravian
发明人： Joseph Garvey , Kevin Himberger , Clark Jeffries , Mohammad Peyravian
IPC分类号： G06F12/14
CPC分类号： G06F21/566
摘要： A kernel based detection of keyboard logger applications is achieved by configuring a call interface to the kernel to characterize a system call pattern for processes accessing a keyboard. A monitor thread iteratively examines a plurality of threads to test open( ), read( ), write( ), and syscall( ) system routines for conditions indicative of presence of a keyboard logger application. A thread whose system call pattern is characterized by such conditions is marked as a keyboard logger.

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