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    • 12. 发明授权
      US06970047B1 Programmable lock detector and corrector 有权
    • Programmable lock detector and corrector
    • 可编程锁定检测器和校正器
    • US06970047B1
    • 2005-11-29
    • US10628656
    • 2003-07-28
    • Phillip Johnson , Gary Powell , William Andrews
    • Phillip Johnson , Gary Powell , William Andrews
    • H03K5/13 , H03K5/15 , H03L7/081 , H03L7/095 , H03L7/10
    • H03L7/0814 , H03K5/15013 , H03L7/095 , H03L7/10 , Y10S331/02
    • An apparatus and method for programmable lock detection and correction (PLDC) to a programmable accuracy in a digital delay-locked loop (DLL) based multiphase clock generator (MCG) is based on a DLL that utilizes a digital count to control the delay of a digitally controlled, multiple-tap delay line in its feedback path where stability of the digital count is used to qualify the determination of lock to a programmable accuracy and lock determination is based on combinatorial evaluation of the multiple phase outputs for the proper waveform relationships. The incidence of false lock corresponding to excessive delay through the delay line is addressed by a LOOPRESET signal that results in a reset of the digital count that controls the delay through the delay line. Additionally, programmability of the stability interval, the digital counter step size, and the accuracy of the lock provide control over lock acquisition time.
    • 基于数字延迟锁定环（DLL）的多相时钟发生器（MCG）中的可编程锁定检测和校正（PLDC）的装置和方法，其基于利用数字计数来控制延迟锁定环 在其反馈路径中的数字控制的多抽头延迟线，其中使用数字计数的稳定性来将锁定的确定限定到可编程精度和锁定确定，基于用于适当波形关系的多相输出的组合评估。 通过延迟线对应于过度延迟的假锁的发生率由LOOPRESET信号来解决，该LOOPRESET信号导致数字计数的复位，该数字计数通过延迟线控制延迟。 此外，稳定性间隔的可编程性，数字计数器步长和锁的精度提供了对锁获取时间的控制。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Espacenet 法律信息 同族专利 专利引用
    • 14. 发明授权
      US08164499B1 Shared-array multiple-output digital-to-analog converter 有权
    • Shared-array multiple-output digital-to-analog converter
    • 共享阵列多输出数模转换器
    • US08164499B1
    • 2012-04-24
    • US12813540
    • 2010-06-11
    • Richard Booth , Paulius Mosinskis , Phillip Johnson , David Onimus
    • Richard Booth , Paulius Mosinskis , Phillip Johnson , David Onimus
    • H03M1/00
    • H03M1/662 , H03M1/747
    • In an exemplary decision-feedback equalizer (DFE) of a serializer/deserializer (SerDes) receiver, a single current mirror array is shared by multiple current digital-to-analog converter (IDAC) functions. The DFE has an initial amplifier stage that applies an initial coefficient COEFF0 to an input data signal and a number of (e.g., five) additional amplifier stages that apply additional coefficients (e.g., COEFF1-COEFF5) to different delayed versions of the recovered output data stream. The outputs of the initial and multiple additional amplifier stages are summed to generate an equalized data signal that is applied to a clock-and-data recovery (CDR) circuit. Due to certain characteristics of the equalizer function, the multiple additional amplifier stages can be implemented using a single shared current mirror array, which save significant amounts of chip area compared to conventional implementations in which each additional amplifier stage has its own dedicated current mirror array.
    • 在串行器/解串器（SerDes）接收器的示例性判决反馈均衡器（DFE）中，单个电流镜阵列由多个当前数模转换器（IDAC）功能共享。 DFE具有初始放大器级，其将初始系数COEFF0应用于输入数据信号和将附加系数（例如，COEFF1-COEFF5）应用于恢复的输出数据的不同延迟版本的（例如，五个）附加放大器级 流。 将初始和多个附加放大器级的输出相加以产生施加到时钟和数据恢复（CDR）电路的均衡数据信号。 由于均衡器功能的某些特性，可以使用单个共享电流镜阵列实现多个附加放大器级，与传统实现相比，其保留了大量的芯片面积，其中每个附加放大器级具有其自己的专用电流镜阵列。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Espacenet 法律信息 同族专利 专利引用
    • 16. 发明授权
      US07521969B2 Switch sequencing circuit systems and methods 有权
    • Switch sequencing circuit systems and methods
    • 开关排序电路系统及方法
    • US07521969B2
    • 2009-04-21
    • US11494862
    • 2006-07-28
    • Richard Booth , Phillip Johnson
    • Richard Booth , Phillip Johnson
    • H03K19/094
    • H03K19/018528 , H03K19/094
    • Systems and methods are disclosed herein to provide improved I/O techniques. For example, in accordance with an embodiment of the present invention, an integrated circuit includes a driver that receives data signals and provides an output signal based on the data signals, with the driver having a plurality of transistors with a first set of the plurality of transistors adapted to provide a first logical value as the output signal and a second set of the plurality of transistors adapted to provide a second logical value as the output signal based on the data signals. A sequencing circuit provides the data signals to the driver such that the first set of the plurality of transistors is switched on before the second set of the plurality of transistors is switched off, and the second set of the plurality of transistors is switched on before the first set of the plurality of transistors is switched off.
    • 本文公开了提供改进的I / O技术的系统和方法。 例如，根据本发明的实施例，集成电路包括接收数据信号并基于数据信号提供输出信号的驱动器，驱动器具有多个具有第一组多个晶体管的晶体管， 适于提供作为输出信号的第一逻辑值的晶体管和适于基于数据信号提供第二逻辑值作为输出信号的多个晶体管的第二组。 排序电路将数据信号提供给驱动器，使得多个晶体管的第一组在多个晶体管的第二组关断之前被接通，并且多个晶体管的第二组在之前被接通 关闭多个晶体管的第一组。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Espacenet 法律信息 同族专利 专利引用
    • 17. 发明申请
      US20070121711A1 PLL with programmable jitter for loopback serdes testing and the like 审中-公开
    • PLL with programmable jitter for loopback serdes testing and the like
    • 具有可编程抖动的PLL，用于环回serdes测试等
    • US20070121711A1
    • 2007-05-31
    • US11289892
    • 2005-11-30
    • Glen Offord , Phillip Johnson
    • Glen Offord , Phillip Johnson
    • H04L5/16
    • G01R31/31717 , G01R31/31709 , G01R31/31715 , H03L7/0891 , H03L7/18
    • In one embodiment of the invention, a phase-locked loop (PLL) can be programmably controlled to add jitter to its PLL output clock. Such a PLL can be used to programmably inject jitter into the outgoing serial data signal generated by a serializer/de-serializer (serdes) that can be operated in an internal loopback mode, in which the outgoing serial data signal is internally looped back from the transmitter side of the serdes to the serdes receiver side. Jitter logic associated with the PLL can be operated in a register-based mode that does not rely on any externally generated jitter clock. Such register-based processing enables effective (1) internal loopback testing of unpackaged devices at the wafer stage as well as package devices at the package stage and (2) external loopback testing at the system level.
    • 在本发明的一个实施例中，可编程地控制锁相环（PLL）以将抖动增加到其PLL输出时钟。 这样的PLL可用于将抖动编程为由可在内部环回模式中操作的串行器/解串器（serdes）生成的输出串行数据信号中，其中输出串行数据信号从内部循环回 发射机侧的serdes到serdes接收机侧。 与PLL相关的抖动逻辑可以在不依赖任何外部产生的抖动时钟的基于寄存器的模式下工作。 这种基于寄存器的处理使得能够有效地（1）在晶片级的未封装的器件以及封装阶段的封装器件进行内部环回测试，以及（2）在系统级的外部环回测试。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 18. 发明申请
      US20070030936A1 Clock-and-data-recovery system having a multi-phase clock generator for one or more channel circuits 有权
    • Clock-and-data-recovery system having a multi-phase clock generator for one or more channel circuits
    • 具有用于一个或多个信道电路的多相时钟发生器的时钟和数据恢复系统
    • US20070030936A1
    • 2007-02-08
    • US11199287
    • 2005-08-08
    • Phillip Johnson , Zheng Chen , Barry Britton
    • Phillip Johnson , Zheng Chen , Barry Britton
    • H04L7/00
    • H04L7/0338 , H03L7/0812
    • In one embodiment of the invention, a clock-and-data-recovery (CDR) system has a multi-phase clock generator that generates a plurality of phase-offset clock signals and one or more channel circuits, each receiving a (different) input data signal and all of the phase-offset clock signals and generates an output data stream and a recovered clock signal. Each channel circuit has a plurality of data registers (e.g., flip-flops), each receiving the input data signal at its clock input port and a different one of the phase-offset clock signals at its data input port, such that the flip-flop is triggered at each (rising) edge in the input data signal. The channel circuit processes the outputs from the different flip-flops to select an appropriate phase-offset clock signal for use in sampling the input data signal to generate the output data stream, where the recovered clock signal is generated from the selected phase-offset clock signal.
    • 在本发明的一个实施例中，时钟和数据恢复（CDR）系统具有产生多个相位偏移时钟信号的多相时钟发生器和一个或多个信道电路，每个信道电路接收（不同的）输入 数据信号和所有相位偏移时钟信号，并产生输出数据流和恢复的时钟信号。 每个通道电路具有多个数据寄存器（例如，触发器），每个数据寄存器在其时钟输入端口接收输入数据信号，并在其数据输入端口接收不同的相位偏移时钟信号， 触发器在输入数据信号的每个（上升沿）触发。 通道电路处理来自不同触发器的输出以选择合适的相位偏移时钟信号，以用于对输入数据信号进行采样以产生输出数据流，其中从所选择的相位偏移时钟产生恢复的时钟信号 信号。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
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