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1. 发明授权

US07466177B2 Pulse-width control loop for clock with pulse-width ratio within wide range 有权
标题翻译：时钟脉冲宽度控制回路，脉宽范围宽
公开(公告)号：US07466177B2
公开(公告)日：2008-12-16
申请号：US11491159
申请日：2006-07-24
申请人： Hong-Yi Huang , Wei-Ming Chiu , Yuan-Hua Chu
发明人： Hong-Yi Huang , Wei-Ming Chiu , Yuan-Hua Chu
IPC分类号： H03K3/17
CPC分类号： H03K5/151 , H03K5/1565
摘要： A pulse-width control loop (PWCL) for clock with any pulse-width ratio within a wide range is provided. A differential programmable charge pump is employed to stabilize the current source by complementary connection. The differential programmable charge pump has a pair of differential charge pumps and a current source module to adjust the ratio of charge to discharge, so as to accelerate the range of the adjustable pulse-width ratio of the output clock and increase the output resolution. Further, a ratioless input control stage is employed to simplify the circuit design and avoid static power consumption. Moreover, the control stage adjusts rising pulse width and dropping pulse width at one period, thereby accelerating the lock speed and the range of the adjustable pulse-width ratio (i.e., duty cycle) of the input clock.
摘要翻译：提供了在宽范围内具有任何脉冲宽度比的时钟的脉冲宽度控制回路（PWCL）。采用差分可编程电荷泵通过互补连接来稳定电流源。差分可编程电荷泵具有一对差动电荷泵和电流源模块，用于调节充放电比例，从而加快输出时钟可调脉宽比的范围，提高输出分辨率。此外，采用无竞争的输入控制级以简化电路设计并避免静态功耗。此外，控制级在一个周期调节上升脉冲宽度和下降脉冲宽度，从而加速锁定速度和输入时钟的可调脉冲宽度比（即占空比）的范围。

2. 发明授权

US06967514B2 Method and apparatus for digital duty cycle adjustment 失效
标题翻译：用于数字占空比调整的方法和装置
公开(公告)号：US06967514B2
公开(公告)日：2005-11-22
申请号：US10277738
申请日：2002-10-21
申请人： Jade M. Kizer , Roxanne T. Vu
发明人： Jade M. Kizer , Roxanne T. Vu
IPC分类号： H03K5/00 , H03K5/156 , H03K19/003 , H03K3/17
CPC分类号： H03K5/1565 , H03K2005/00058 , H03K2005/00208
摘要： Adjusting a clock duty cycle. An incremental error signal is generated in response to the clock signal. A cumulative error signal is generated in response to the incremental error signal. The incremental error signal is reset and the duty cycle of the clock signal is adjusted in response to the cumulative error signal.
摘要翻译：调整时钟占空比。响应于时钟信号产生增量误差信号。响应于增量误差信号产生累积误差信号。复位增量误差信号，并根据累积误差信号调整时钟信号的占空比。

3. 发明授权

US08248130B2 Duty cycle correction circuit 有权
标题翻译：占空比校正电路
公开(公告)号：US08248130B2
公开(公告)日：2012-08-21
申请号：US12786496
申请日：2010-05-25
申请人： Vinod Jain , Deependra K. Jain , Krishna Thakur , Avinish Chandra Tripathi , Sanjay Kumar Wadhwa
发明人： Vinod Jain , Deependra K. Jain , Krishna Thakur , Avinish Chandra Tripathi , Sanjay Kumar Wadhwa
IPC分类号： H03K3/17 , H03K5/04 , H03K7/08
CPC分类号： H03K5/1565
摘要： A duty cycle correction circuit for correcting the duty cycle of a clock signal generated by a clock generator includes a complementary buffer chain, level shifter circuits and a self-bias circuit. A clock signal with a distorted duty cycle and its complement are provided to the level shifter circuits. The level shifter circuits reduce the magnitude of voltage of the clock signal and the complement and generate level shifted signals. The level shifted signals are provided to a differential amplifier that generates a control signal indicating the magnitude of distortion in the duty cycle. The control signal is used to correct the duty cycle of the clock signal. The self-bias circuit is used to bias the differential amplifier.
摘要翻译：用于校正由时钟发生器产生的时钟信号的占空比的占空比校正电路包括互补缓冲链，电平移位器电路和自偏置电路。具有失真占空比的时钟信号及其补码提供给电平移位器电路。电平移位器电路减小时钟信号和补码的电压幅值，并产生电平移位信号。电平移位信号被提供给差分放大器，该差分放大器产生指示占空比中的失真幅度的控制信号。控制信号用于校正时钟信号的占空比。自偏置电路用于偏置差分放大器。

4. 发明授权

US07554377B1 Apparatus and method for signal voltage limiting 有权
标题翻译：信号电压限制的装置和方法
公开(公告)号：US07554377B1
公开(公告)日：2009-06-30
申请号：US11856242
申请日：2007-09-17
申请人： Charles Yong Yi Guan
发明人： Charles Yong Yi Guan
IPC分类号： H03K3/17
CPC分类号： H03K5/082 , H03F3/45094 , H03F2200/456 , H03F2203/45028 , H03K5/2481
摘要： A circuit and method for limiting a signal voltage in which the minimum and maximum levels of the output signal can be controlled by selectively applying different lower and higher reference voltages from which the minimum and maximum output signal levels are derived.
摘要翻译：用于限制信号电压的电路和方法，其中可以通过选择性地施加从其导出最小和最大输出信号电平的不同的较低和较高参考电压来控制输出信号的最小和最大电平。

5. 发明授权

US07436233B2 Normal mode and green mode pulse width modulation controller 有权
标题翻译：正常模式和绿色模式脉宽调制控制器
公开(公告)号：US07436233B2
公开(公告)日：2008-10-14
申请号：US11555426
申请日：2006-11-01
申请人： Hsian-Pei Yee , Tung Sheng Chang
发明人： Hsian-Pei Yee , Tung Sheng Chang
IPC分类号： H03K3/17
CPC分类号： H03K7/08 , H02M3/156 , H02M2001/0032 , Y02B70/16
摘要： A PWM controller that effectively transitions between normal mode and green power mode is disclosed. A driver provides a normal drive signal during normal operation. A pulse width detector detects the pulse width of the PWM signal and if the pulse width drops below a threshold the normal mode drive signal will be turned off and a pulse ON time measurer will begin storing the pulse ON time. When the total ON time reaches a total ON time threshold or the output voltage drops below a voltage limit, a green mode drive signal will be output to the power converter. During green mode the driver will continue sending the green mode drive signal at intervals until a heavy load condition when the green mode drive signal will be shut off and the driver will resume sending the normal mode drive signal.
摘要翻译：公开了在正常模式和绿色功率模式之间有效转换的PWM控制器。驾驶员在正常操作期间提供正常的驱动信号。脉冲宽度检测器检测PWM信号的脉冲宽度，如果脉冲宽度下降到阈值以下，则正常模式驱动信号将被关闭，脉冲ON时间测量器将开始存储脉冲接通时间。当总导通时间达到总导通时间阈值或输出电压下降到电压限制以下时，绿色模式驱动信号将被输出到功率转换器。在绿色模式期间，当绿色模式驱动信号关闭并且驱动器将恢复发送普通模式驱动信号时，驱动器将会间隔地继续发送绿色模式驱动信号，直到重负载状态。

6. 发明授权

US07791388B2 Duty cycle error calculation circuit for a clock generator having a delay locked loop and duty cycle correction circuit 有权
标题翻译：具有延迟锁定环和占空比校正电路的时钟发生器的占空比误差计算电路
公开(公告)号：US07791388B2
公开(公告)日：2010-09-07
申请号：US12203700
申请日：2008-09-03
申请人： Tyler Gomm
发明人： Tyler Gomm
IPC分类号： H03K3/17
CPC分类号： H03K5/1565 , H03K5/26 , H03L7/07 , H03L7/0805 , H03L7/0814
摘要： A system and method for generating a correction signal for correcting duty cycle error of a first clock signal relative to a second complementary clock signal. Changes to a time difference between high- and low-portions of the first clock signal are detected and the correction signal is generated in response to and accordance with the detected changes.
摘要翻译：一种用于产生用于校正第一时钟信号相对于第二互补时钟信号的占空比误差的校正信号的系统和方法。检测对第一时钟信号的高低部分之间的时间差的变化，并且响应于并根据检测到的变化产生校正信号。

7. 发明授权

US07091763B1 Clock generation 有权
标题翻译：时钟生成
公开(公告)号：US07091763B1
公开(公告)日：2006-08-15
申请号：US10701005
申请日：2003-11-03
申请人： Phillip Johnson , William Andrews , Fulong Zhang , Gary Powell
发明人： Phillip Johnson , William Andrews , Fulong Zhang , Gary Powell
IPC分类号： H03K3/17
CPC分类号： H03K5/1565 , G06F1/10 , H03L7/07
摘要： Clock generation techniques are disclosed to provide clock generation with duty cycle replication. The clock generation techniques may further compensate for clock insertion delays and minimize distortion due to clock distribution networks.
摘要翻译：时钟生成技术被公开以提供占空比复制的时钟生成。时钟产生技术可以进一步补偿时钟插入延迟并且最小化由于时钟分配网络引起的失真。

8. 发明授权

US6133771A Device for generating pulses of high-precision programmable duration 有权
标题翻译：用于产生高精度可编程持续时间的脉冲的装置
公开(公告)号：US6133771A
公开(公告)日：2000-10-17
申请号：US263757
申请日：1999-03-05
申请人： Salvatore Portaluri , Valerio Pisati , Luigi Zangrandi
发明人： Salvatore Portaluri , Valerio Pisati , Luigi Zangrandi
IPC分类号： H03K7/08 , H03K3/17
CPC分类号： H03K7/08
摘要： A device generates pulses of high-precision with programmable duration. The device includes first, second and third pulse generator circuits. The first pulse generator circuit receives at an input a pulse generation command signal, and provides at an output a first pulse for loading the contents of a register in a counter. The second pulse generator circuit is triggered by the first pulse provided by the first pulse generator circuit. The third pulse generator circuit is triggered by a second pulse provided by the second pulse generator circuit, and generates a third pulse to restart the second pulse generator circuit. The second pulse provided by the second pulse generator circuit forms a clock signal for the counter to produce a decrement in the counter. The output signal from the counter is the pulsed signal to be generated. The duration of the pulsed signal is determined by the content of the counter.
摘要翻译：器件产生具有可编程持续时间的高精度脉冲。该装置包括第一，第二和第三脉冲发生器电路。第一脉冲发生器电路在输入端接收脉冲产生指令信号，并在输出端提供用于将寄存器的内容装入计数器的第一脉冲。第二脉冲发生器电路由第一脉冲发生器电路提供的第一脉冲触发。第三脉冲发生器电路由第二脉冲发生器电路提供的第二脉冲触发，并产生第三脉冲以重新启动第二脉冲发生器电路。由第二脉冲发生器电路提供的第二脉冲为计数器形成时钟信号以产生计数器的减量。来自计数器的输出信号是要产生的脉冲信号。脉冲信号的持续时间由计数器的内容决定。

9. 发明授权

US5696463A Address transition detecting circuit which generates constant pulse width signal 失效
标题翻译：地址转换检测电路产生恒定脉宽信号
公开(公告)号：US5696463A
公开(公告)日：1997-12-09
申请号：US789512
申请日：1997-01-27
申请人： Geoun Tae Kwon
发明人： Geoun Tae Kwon
IPC分类号： A23L1/304 , A23L2/52 , A23L2/68 , G11C8/18 , H03K3/17
CPC分类号： G11C8/18 , A23L2/52 , A23L2/68 , A23L33/16
摘要： An address transition detecting circuit comprising a first address transition detecting stage for generating a first address transition detection signal, the first address transition detection signal having a pulse width which is constant and stable when a supply voltage is relatively low, a second address transition detecting stage for generating a second address transition detection signal, the second address transition detection signal having the same pulse width as that of the first address transition detection signal from the first address transition detecting stage when the supply voltage is relatively high, a switching stage for switching selectively the first and second address transition detection signals from the first and second address transition detecting stages to an output line, and a supply voltage detecting stage for detecting a level of the supply voltage and controlling the switching stage in accordance with the detected level.
摘要翻译：一种地址转换检测电路，包括用于产生第一地址转换检测信号的第一地址转换检测级，当电源电压相对较低时具有恒定且稳定的脉冲宽度的第一地址转换检测信号，第二地址转换检测级用于产生第二地址转换检测信号，所述第二地址转变检测信号具有与当所述电源电压相对较高时来自所述第一地址转变检测级的第一地址转移检测信号相同的脉冲宽度，用于选择性地切换的切换级从第一和第二地址转换检测级到输出线的第一和第二地址转换检测信号，以及用于检测电源电压电平并根据检测电平控制开关级的电源电压检测级。

10. 发明授权

US07279947B2 PWM buffer circuit for adjusting a frequency and a duty cycle of a PWM signal 有权
标题翻译： PWM缓冲电路，用于调整PWM信号的频率和占空比
公开(公告)号：US07279947B2
公开(公告)日：2007-10-09
申请号：US10657181
申请日：2003-09-09
申请人： Chun-Iung Chiu , Wen-shi Huang
发明人： Chun-Iung Chiu , Wen-shi Huang
IPC分类号： H03K3/17
CPC分类号： H03K7/08 , H02P7/29
摘要： A PWM buffer circuit includes a duty cycle converting circuit and a frequency-fixed PWM signal generating circuit. The duty cycle converting circuit is used for receiving a first PWM signal and then generating a duty cycle reference voltage on the basis of the first PWM signal. The duty cycle reference voltage is a one-to-one mapping function of the first duty cycle. The frequency-fixed PWM signal generating circuit is used for receiving the duty cycle reference voltage and then outputting a second PWM signal with a fixed frequency. The second PWM signal has a second duty cycle, which is determined in accordance with the duty cycle reference voltage. In addition, the second duty cycle is a one-to-one mapping function of the duty cycle reference voltage.
摘要翻译： PWM缓冲电路包括占空比转换电路和频率固定的PWM信号发生电路。占空比转换电路用于接收第一PWM信号，然后基于第一PWM信号产生占空比参考电压。占空比参考电压是第一个占空比的一对一映射函数。频率固定的PWM信号发生电路用于接收占空比参考电压，然后输出具有固定频率的第二PWM信号。第二PWM信号具有第二占空比，其根据占空比参考电压来确定。此外，第二占空比是占空比参考电压的一对一映射函数。

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