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1. 发明授权

US08164499B1 Shared-array multiple-output digital-to-analog converter 有权
标题翻译：共享阵列多输出数模转换器
公开(公告)号：US08164499B1
公开(公告)日：2012-04-24
申请号：US12813540
申请日：2010-06-11
申请人： Richard Booth , Paulius Mosinskis , Phillip Johnson , David Onimus
发明人： Richard Booth , Paulius Mosinskis , Phillip Johnson , David Onimus
IPC分类号： H03M1/00
CPC分类号： H03M1/662 , H03M1/747
摘要： In an exemplary decision-feedback equalizer (DFE) of a serializer/deserializer (SerDes) receiver, a single current mirror array is shared by multiple current digital-to-analog converter (IDAC) functions. The DFE has an initial amplifier stage that applies an initial coefficient COEFF0 to an input data signal and a number of (e.g., five) additional amplifier stages that apply additional coefficients (e.g., COEFF1-COEFF5) to different delayed versions of the recovered output data stream. The outputs of the initial and multiple additional amplifier stages are summed to generate an equalized data signal that is applied to a clock-and-data recovery (CDR) circuit. Due to certain characteristics of the equalizer function, the multiple additional amplifier stages can be implemented using a single shared current mirror array, which save significant amounts of chip area compared to conventional implementations in which each additional amplifier stage has its own dedicated current mirror array.
摘要翻译：在串行器/解串器（SerDes）接收器的示例性判决反馈均衡器（DFE）中，单个电流镜阵列由多个当前数模转换器（IDAC）功能共享。 DFE具有初始放大器级，其将初始系数COEFF0应用于输入数据信号和将附加系数（例如，COEFF1-COEFF5）应用于恢复的输出数据的不同延迟版本的（例如，五个）附加放大器级流。将初始和多个附加放大器级的输出相加以产生施加到时钟和数据恢复（CDR）电路的均衡数据信号。由于均衡器功能的某些特性，可以使用单个共享电流镜阵列实现多个附加放大器级，与传统实现相比，其保留了大量的芯片面积，其中每个附加放大器级具有其自己的专用电流镜阵列。

2. 发明授权

US08441292B1 Delaying data signals 有权
标题翻译：延迟数据信号
公开(公告)号：US08441292B1
公开(公告)日：2013-05-14
申请号：US12813573
申请日：2010-06-11
申请人： Phillip Johnson , Richard Booth , Paulius Mosinskis
发明人： Phillip Johnson , Richard Booth , Paulius Mosinskis
IPC分类号： H03L7/00
CPC分类号： H03K5/135 , H03M9/00
摘要： In one embodiment, multiple (serializer/deserializer) SERDES channels are aligned by selectively slipping one or more of the incoming serial data streams one bit at a time prior to deserialization. Within each SERDES channel, a slip circuit slips the corresponding serial data stream by one bit (i.e., one unit interval (UI)) by extending the high portion of the duty cycle of a corresponding clock signal. The high portion of the clock signal is extended using a 3-to-1 mux that selects a fixed high signal, such as the high power supply rail, as an intermediate mux output signal whenever transitioning between two different applied clock signals that are offset from one another by one UI. In this way, the slip circuit avoids glitches that might otherwise result from switching directly between the two clock signals.
摘要翻译：在一个实施例中，通过在反序列化之前一次选择性地滑动一个或多个输入串行数据流一比特来对齐多个（串行器/解串器）SERDES通道。在每个SERDES通道内，滑动电路通过延长对应的时钟信号的占空比的高部分，将对应的串行数据流滑移一位（即，一个单位间隔（UI））。时钟信号的高部分使用3对1多路复用器进行扩展，其选择固定的高信号，例如高电源轨，作为中间多路复用器输出信号，无论何时在两个不同的施加时钟信号之间进行转换另一个用户界面。以这种方式，滑动电路可以避免由两个时钟信号之间直接切换引起的毛刺。

3. 发明授权

US07586344B1 Dynamic delay or advance adjustment of oscillating signal phase 有权
标题翻译：振荡信号相位的动态延迟或提前调整
公开(公告)号：US07586344B1
公开(公告)日：2009-09-08
申请号：US11872950
申请日：2007-10-16
申请人： Richard Booth , Phillip Johnson , Zheng Chen
发明人： Richard Booth , Phillip Johnson , Zheng Chen
IPC分类号： H03B19/00
CPC分类号： G06F1/06 , H03K21/406
摘要： In one embodiment, the invention can be a clock-generating circuit having one or more clock-processing circuits, each outputting a clock signal having an adjustable phase. Each clock-processing circuit comprises a divider and a divisor control circuit. Each divider divides an input clock signal by a respective divisor value and outputs a corresponding output clock signal whose period is determined by the divisor value and the period of the input clock signal. Each divider receives the respective divisor value from the corresponding divisor control circuit, wherein the divisor value is selected in order to achieve a desired frequency and phase for the corresponding output clock signal. Temporarily changing a divisor value can advance or delay the phase of the corresponding output clock signal without having to reset the divider.
摘要翻译：在一个实施例中，本发明可以是具有一个或多个时钟处理电路的时钟发生电路，每个时钟处理电路输出具有可调相位的时钟信号。每个时钟处理电路包括除法器和除数控制电路。每个除法器将输入时钟信号除以相应的除数值，并输出相应的输出时钟信号，其周期由除数值和输入时钟信号的周期确定。每个分频器从相应的除数控制电路接收相应的除数值，其中选择除数值以便为相应的输出时钟信号实现期望的频率和相位。临时改变除数值可以提前或延迟对应的输出时钟信号的相位，而不必复位分频器。

4. 发明授权

US07521969B2 Switch sequencing circuit systems and methods 有权
标题翻译：开关排序电路系统及方法
公开(公告)号：US07521969B2
公开(公告)日：2009-04-21
申请号：US11494862
申请日：2006-07-28
申请人： Richard Booth , Phillip Johnson
发明人： Richard Booth , Phillip Johnson
IPC分类号： H03K19/094
CPC分类号： H03K19/018528 , H03K19/094
摘要： Systems and methods are disclosed herein to provide improved I/O techniques. For example, in accordance with an embodiment of the present invention, an integrated circuit includes a driver that receives data signals and provides an output signal based on the data signals, with the driver having a plurality of transistors with a first set of the plurality of transistors adapted to provide a first logical value as the output signal and a second set of the plurality of transistors adapted to provide a second logical value as the output signal based on the data signals. A sequencing circuit provides the data signals to the driver such that the first set of the plurality of transistors is switched on before the second set of the plurality of transistors is switched off, and the second set of the plurality of transistors is switched on before the first set of the plurality of transistors is switched off.
摘要翻译：本文公开了提供改进的I / O技术的系统和方法。例如，根据本发明的实施例，集成电路包括接收数据信号并基于数据信号提供输出信号的驱动器，驱动器具有多个具有第一组多个晶体管的晶体管，适于提供作为输出信号的第一逻辑值的晶体管和适于基于数据信号提供第二逻辑值作为输出信号的多个晶体管的第二组。排序电路将数据信号提供给驱动器，使得多个晶体管的第一组在多个晶体管的第二组关断之前被接通，并且多个晶体管的第二组在之前被接通关闭多个晶体管的第一组。

5. 发明申请

US20080024171A1 Switch sequencing circuit systems and methods 有权
标题翻译：开关排序电路系统及方法
公开(公告)号：US20080024171A1
公开(公告)日：2008-01-31
申请号：US11494862
申请日：2006-07-28
申请人： Richard Booth , Phillip Johnson
发明人： Richard Booth , Phillip Johnson
IPC分类号： H03K19/094
CPC分类号： H03K19/018528 , H03K19/094
摘要： Systems and methods are disclosed herein to provide improved I/O techniques. For example, in accordance with an embodiment of the present invention, an integrated circuit includes a driver that receives data signals and provides an output signal based on the data signals, with the driver having a plurality of transistors with a first set of the plurality of transistors adapted to provide a first logical value as the output signal and a second set of the plurality of transistors adapted to provide a second logical value as the output signal based on the data signals. A sequencing circuit provides the data signals to the driver such that the first set of the plurality of transistors is switched on before the second set of the plurality of transistors is switched off, and the second set of the plurality of transistors is switched on before the first set of the plurality of transistors is switched off.
摘要翻译：本文公开了提供改进的I / O技术的系统和方法。例如，根据本发明的实施例，集成电路包括接收数据信号并基于数据信号提供输出信号的驱动器，驱动器具有多个具有第一组多个晶体管的晶体管，适于提供作为输出信号的第一逻辑值的晶体管和适于基于数据信号提供第二逻辑值作为输出信号的多个晶体管的第二组。排序电路将数据信号提供给驱动器，使得多个晶体管的第一组在多个晶体管的第二组关断之前被接通，并且多个晶体管的第二组在之前被接通关闭多个晶体管的第一组。

6. 发明申请

US20070136619A1 Jitter tolerant delay-locked loop circuit 有权
标题翻译：抖动容限延迟锁定环路
公开(公告)号：US20070136619A1
公开(公告)日：2007-06-14
申请号：US11302097
申请日：2005-12-13
申请人： Zheng (Jeff) Chen , Phillip Johnson , Fulong Zhang
发明人： Zheng (Jeff) Chen , Phillip Johnson , Fulong Zhang
IPC分类号： G06F1/00
CPC分类号： G06F1/04 , G06F1/12
摘要： Systems and methods are disclosed herein to provide improved jitter tolerant delay-locked loop circuitry. For example, in accordance with an embodiment of the present invention, an integrated circuit includes a plurality of delay cells each having a plurality of programmable delay taps. Each delay cell is adapted to provide a delayed clock signal delayed by a selected number of the delay taps. A phase detector is adapted to compare a first clock signal with a selected one of the delayed clock signals to obtain a comparison result and provide a plurality of control signals in response to the comparison result. An arithmetic logic unit (ALU) is adapted to vary the selected number of delay taps in response to the control signals provided by the phase detector.
摘要翻译：本文公开了系统和方法以提供改进的抖动容限延迟锁定环路。例如，根据本发明的实施例，集成电路包括多个延迟单元，每个延迟单元具有多个可编程延迟抽头。每个延迟单元适于提供延迟选定数量的延迟抽头的延迟时钟信号。相位检测器适于将第一时钟信号与所选延迟时钟信号中的一个进行比较，以获得比较结果，并响应于比较结果提供多个控制信号。算术逻辑单元（ALU）适于响应于由相位检测器提供的控制信号来改变选定数量的延迟抽头。

7. 外观设计

USD261970S Display device 失效
公开(公告)号：USD261970S
公开(公告)日：1981-11-24
申请号：US884653
申请日：1978-03-08
申请人： Thomas J. Alexandris , D. Michael Williams , Phillip Johnson
设计人： Thomas J. Alexandris , D. Michael Williams , Phillip Johnson

8. 发明申请

US20060261882A1 Bandgap generator providing low-voltage operation 审中-公开
标题翻译：带隙发生器提供低电压工作
公开(公告)号：US20060261882A1
公开(公告)日：2006-11-23
申请号：US11131053
申请日：2005-05-17
申请人： Phillip Johnson
发明人： Phillip Johnson
IPC分类号： G05F1/10
CPC分类号： G05F3/30
摘要： A bandgap reference circuit uses a pair of parallel loads and an op-amp driver circuit. The op-amp driver circuit uses NMOS inputs to sense voltage conditions at the loads. The configuration permits low-voltage response at low temperatures as a result of the configuration setting operating voltages above a saturation voltage. The op-amp driver provides an NMOS output, and a low-gain stage converts the NMOS output to an output corresponding to that of a conventional PMOS design.
摘要翻译：带隙参考电路使用一对并联负载和运放驱动电路。运放驱动电路使用NMOS输入来检测负载下的电压状况。由于配置设置工作电压高于饱和电压，配置允许低温下的低电压响应。运算放大器驱动器提供NMOS输出，低增益级将NMOS输出转换为与传统PMOS设计相对应的输出。

9. 发明授权

US07132903B1 Noise-shielding, switch-controlled load circuitry for oscillators and the like 有权
标题翻译：用于振荡器的噪声屏蔽，开关控制负载电路等
公开(公告)号：US07132903B1
公开(公告)日：2006-11-07
申请号：US10613460
申请日：2003-07-03
申请人： Phillip Johnson , Gary Powell , Harold Scholz
发明人： Phillip Johnson , Gary Powell , Harold Scholz
IPC分类号： H03L1/00 , H03B27/00
CPC分类号： H03K3/0322 , H03K5/133 , H03K2005/00208 , H03L7/0812 , H03L7/0995
摘要： A set of interconnected delay stages, such as a voltage-controlled oscillator, has switch-controlled load circuitry connected to each output of each delay stage in the oscillator ring. In one embodiment, for each delay stage output, the switch-controlled load circuitry includes a switch, a transistor, and a current source. The switch is connected between the corresponding delay stage output and the transistor gate, the current source is connected between a power supply and the transistor drain, and the transistor source is connected to ground. In such a configuration, the transistor's gate-to-source capacitance can be applied to the corresponding delay stage output by closing the switch, for example, for lower-frequency operations. In addition, the output impedance of the current source decouples the capacitive load from the power supply, thereby substantially shielding the oscillator ring from noise in the power supply.
摘要翻译：一组互连的延迟级，例如压控振荡器，具有连接到振荡器环中每个延迟级的每个输出的开关控制负载电路。在一个实施例中，对于每个延迟级输出，开关控制的负载电路包括开关，晶体管和电流源。开关连接在相应的延迟级输出和晶体管栅极之间，电流源连接在电源和晶体管漏极之间，晶体管源连接到地。在这种配置中，例如，对于较低频率的操作，晶体管的栅极 - 源极电容可以被施加到相应的延迟级输出。此外，电流源的输出阻抗使电容负载与电源分离，从而基本上屏蔽振荡器环免受电源中的噪声。

10. 发明授权

US5576664A Discrete time digital phase locked loop 失效
标题翻译：离散时间数字锁相环
公开(公告)号：US5576664A
公开(公告)日：1996-11-19
申请号：US556882
申请日：1995-11-02
申请人： Barry W. Herold , Scott R. Humphreys , Phillip Johnson , Raymond L. Barrett, Jr. , Grazyna A. Pajunen
发明人： Barry W. Herold , Scott R. Humphreys , Phillip Johnson , Raymond L. Barrett, Jr. , Grazyna A. Pajunen
IPC分类号： H03L7/091 , H03L7/093 , H03L7/181
CPC分类号： H03L7/091 , H03L7/093 , H03L7/181
摘要： A communication receiver (100) employs a discrete time digital phase locked loop (142) for maintaining a generated signal (144) locked to a reference signal (136). The discrete time digital phase locked loop (142) includes a phase detector (202), an accumulator (219), an adder (227), and a controlled oscillator (232). The accumulator (219) is connected to the phase detector (202) and a reference signal (136) for calculating an accumulator output value equal to a first sum of a current sample generated by the phase detector (202), and all of the plurality of discrete phase error samples produced prior to the current sample. The adder (227) is connected to the phase detector (202) and the accumulator (219) for forming a second sum of the current sample and the accumulator output value. The controlled oscillator (232) receives the second sum, which is utilized for controlling the controlled oscillator (232).
摘要翻译：通信接收器（100）采用离散时间数字锁相环（142）来保持锁定到参考信号（136）的生成信号（144）。离散时间数字锁相环（142）包括相位检测器（202），累加器（219），加法器（227）和受控振荡器（232）。累加器（219）连接到相位检测器（202）和参考信号（136），用于计算等于由相位检测器（202）生成的当前采样的第一和的累加器输出值，并且所有多个在当前样本之前产生的离散相位误差样本。加法器（227）连接到相位检测器（202）和累加器（219），用于形成当前采样和累加器输出值的第二和。受控振荡器（232）接收用于控制受控振荡器（232）的第二和。

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