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11. 发明申请

US20090219100A1 VOLTAGE-CONTROLLED OSCILLATOR GAIN CALIBRATION FOR TWO-POINT MODULATION IN A PHASE-LOCKED LOOP 有权
标题翻译：电压控制振荡器在相位锁定环中进行两点调制的增益校准
公开(公告)号：US20090219100A1
公开(公告)日：2009-09-03
申请号：US12040875
申请日：2008-03-01
申请人： Rajasekhar Pullela , Morten Damgaard , Shahrzad Tadjpour , John E. Vasa , Hoon Lee
发明人： Rajasekhar Pullela , Morten Damgaard , Shahrzad Tadjpour , John E. Vasa , Hoon Lee
IPC分类号： G01R23/00
CPC分类号： H03C3/0925 , H03C3/0933 , H03C3/0941 , H03C3/095 , H03C3/0991
摘要： A phase-locked loop (PLL) is arranged to receive high-pass data at a first input and low-pass data at a second input. A first digital input is coupled to a primary path through a digital-to-analog converter (DAC) and a second digital input is coupled to a feedback path of the PLL. The controller provides the first input and the second input during a calibration procedure. The controller adjusts first and second control inputs in an attempt to keep the input voltage to a voltage-controlled oscillator (VCO) in the PLL constant while determining the gain of the VCO in Hz/LSB.
摘要翻译：锁相环（PLL）被布置成在第一输入处接收高通数据并在第二输入端接收低通数据。第一数字输入通过数模转换器（DAC）耦合到主路径，并且第二数字输入耦合到PLL的反馈路径。控制器在校准过程中提供第一个输入和第二个输入。控制器调整第一和第二控制输入，试图将输入电压保持为PLL中的压控振荡器（VCO），同时以Hz / LSB确定VCO的增益。

12. 发明授权

US07457181B2 Memory device and method of operating the same 失效
标题翻译：存储器件及其操作方法
公开(公告)号：US07457181B2
公开(公告)日：2008-11-25
申请号：US11600552
申请日：2006-11-16
申请人： Hoon Lee , Kee-Won Kwon
发明人： Hoon Lee , Kee-Won Kwon
IPC分类号： G11C7/02
CPC分类号： G11C11/4096 , G11C7/065 , G11C7/1048 , G11C7/1051 , G11C7/106 , G11C11/4091 , G11C2207/002 , G11C2207/065
摘要： A memory device has a global input/output line pair configured for data transfer. The memory device includes a sense amplifier, a detecting unit and a detect control signal generating unit. The sense amplifier is coupled to the global input/output line pair. The detecting unit detects a potential difference between the global input/output line pair. The detect control signal generating unit disables an operation of the sense amplifier and precharges the global input/output line pair to a predetermined voltage. A precharge operation of a memory device may be performed at a higher speed so that a high speed operation of the memory device may be achieved. In addition, the operating time of the sense amplifier may be decreased so that the power consumption of the memory device may be reduced.
摘要翻译：存储器件具有配置用于数据传输的全局输入/输出线对。存储装置包括读出放大器，检测单元和检测控制信号生成单元。读出放大器耦合到全局输入/输出线对。检测单元检测全局输入/输出线对之间的电位差。检测控制信号产生单元禁止读出放大器的操作，并将全局输入/输出线对预充电到预定电压。可以以更高的速度执行存储器件的预充电操作，从而可以实现存储器件的高速操作。此外，可以减小读出放大器的工作时间，从而可以降低存储器件的功耗。

13. 发明申请

US20050207627A1 Fingerprint recognition system and method 审中-公开
标题翻译：指纹识别系统及方法
公开(公告)号：US20050207627A1
公开(公告)日：2005-09-22
申请号：US11087196
申请日：2005-03-22
申请人： Hoon Lee
发明人： Hoon Lee
IPC分类号： G06K9/00 , G06K9/46 , G06K9/52
CPC分类号： G06K9/00067 , G06K9/4647
摘要： A fingerprint recognition method in accordance with one embodiment of the invention comprises capturing a fingerprint image; defining the fingerprint image by pre-processing the image; extracting fingerprint information from the fingerprint image, the fingerprint information comprising fingerprint information captured by way of radon transformation; and performing an authentication process using the fingerprint information.
摘要翻译：根据本发明的一个实施例的指纹识别方法包括捕获指纹图像; 通过预处理图像来定义指纹图像; 从指纹图像提取指纹信息，指纹信息包括通过氡变换捕获的指纹信息; 以及使用指纹信息执行认证处理。

14. 发明申请

US20050149822A1 Method of controlling FEC in EPON 有权
标题翻译：在EPON中控制FEC的方法
公开(公告)号：US20050149822A1
公开(公告)日：2005-07-07
申请号：US11005115
申请日：2004-12-04
申请人： Hoon Lee , Tae Yoo , Hyeong Lee
发明人： Hoon Lee , Tae Yoo , Hyeong Lee
IPC分类号： G01R31/08 , G06F11/00 , G08C15/00 , H03M13/00 , H04J1/16 , H04J3/14 , H04L1/00 , H04L1/20 , H04L12/26
CPC分类号： H04L1/0009 , H04L1/0057 , H04L1/203 , H04Q11/0066 , H04Q11/0067 , H04Q2011/0079 , H04Q2011/0088
摘要： A method of controlling a Forward Error Correction (FEC) operation including: configuring a FEC frame to be transmitted between an OLT and an ONU comprising a FEC frame identifier indicating whether FEC should be performed, data, a first flag indicating that FEC should be performed, and a second flag indicating that the FEC frame is to be FEC encoded; initializing the OLT by disabling a FEC function; determining whether the ONU requires FEC to be performed based on a FEC frame identifier received from the ONU; IPG stretching the FEC frame when the ONU requires to FEC to be performed; and transmitting the FEC frame to the ONU after FEC encoding based on the second flag of an input frame to a PCS sublayer from an upper layer. The method controls an effective operation of a FEC of an ONU and an OLT without changing a Round Trip Time (RTT) according to optical link quality in an EPON. Accordingly, FEC is used only if necessary, thereby simplifying the managing of a link, and preventing an excessive 35% reduction of throughput caused by use of unnecessary FEC.
摘要翻译：一种控制前向纠错（FEC）操作的方法，包括：配置要在OLT和ONU之间传输的FEC帧，包括指示是否应执行FEC的FEC帧标识符，数据，指示应执行FEC的第一标志以及指示FEC帧要被FEC编码的第二标志; 通过禁用FEC功能来初始化OLT; 基于从ONU接收到的FEC帧标识来确定ONU是否需要执行FEC; 当ONU需要执行FEC时，IPG扩展FEC帧; 并且基于来自上层的PCS子层的基于输入帧的第二标志的FEC编码之后将FEC帧发送到ONU。该方法根据EPON中的光链路质量来控制ONU和OLT的FEC的有效操作，而不改变往返时间（RTT）。因此，仅在必要时使用FEC，从而简化链路的管理，并且防止由于使用不必要的FEC导致的吞吐量的过度的35％的降低。

15. 发明申请

US20050148196A1 Method and system for patterning material in a thin film device 审中-公开
标题翻译：在薄膜器件中图案化材料的方法和系统
公开(公告)号：US20050148196A1
公开(公告)日：2005-07-07
申请号：US10746170
申请日：2003-12-26
申请人： Manish Sharma , Thomas Anthony , Hoon Lee
发明人： Manish Sharma , Thomas Anthony , Hoon Lee
IPC分类号： H01L21/302 , H01L21/461 , H01L43/12
CPC分类号： H01L43/12
摘要： An aspect of the present invention is a method of patterning material in a thin-film device. The method includes forming a liftoff stencil, depositing a first layer of material through the liftoff stencil, depositing a second layer of material through the liftoff stencil, removing at least a portion of the liftoff stencil and performing a directional etch on the first and second layer of material.
摘要翻译：本发明的一个方面是在薄膜器件中图案化材料的方法。该方法包括形成剥离模板，将第一层材料沉积通过剥离模板，通过剥离模板沉积第二材料层，去除剥离模板的至少一部分并在第一层和第二层上执行定向蚀刻的材料。

16. 发明申请

US20150027149A1 ELECTRIC EXPANSION VALVE CONTROL FOR A REFRIGERATION SYSTEM 审中-公开
标题翻译：制冷系统用电气膨胀阀控制
公开(公告)号：US20150027149A1
公开(公告)日：2015-01-29
申请号：US13818203
申请日：2011-08-22
申请人： Lee Seunghyeon , Hoon Lee , Byoungjoon Yoo , Young Man Cho
发明人： Lee Seunghyeon , Hoon Lee , Byoungjoon Yoo , Young Man Cho
IPC分类号： F25B49/02 , F25B41/06
CPC分类号： F25B49/02 , F25B41/062 , F25B2341/065 , F25B2600/19 , F25B2600/21 , F25B2600/2513 , F25B2700/171 , F25B2700/2104 , F25B2700/2106 , F25B2700/21151 , F25B2700/21152 , F25B2700/2116 , F25B2700/21162 , F25B2700/21163 , F25B2700/2117 , Y02B30/72
摘要： A refrigeration system including a condenser having a condenser inlet and a condenser outlet, a compressor fluidly connected to the condenser inlet, and an evaporator including an evaporator inlet and an evaporator outlet. The evaporator outlet is fluidly connected to the compressor. A compressor speed sensor senses an operational speed of the compressor. An electric expansion valve (EEV) is fluidly connected to the condenser outlet and the evaporator inlet. The EEV includes a valve member that is selectively positioned to establish a desired opening to pass refrigerant from the condenser to the evaporator. A controller is electrically connected to the EEV and the compressor speed sensor. The controller establishes the desired opening of the valve member based on one of a cooling mode superheat value and a heating mode super heat value, and the operational speed of the compressor.
摘要翻译：一种制冷系统，包括具有冷凝器入口和冷凝器出口的冷凝器，与冷凝器入口流体连接的压缩机以及包括蒸发器入口和蒸发器出口的蒸发器。蒸发器出口流体地连接到压缩机。压缩机速度传感器感测压缩机的操作速度。电动膨胀阀（EEV）流体地连接到冷凝器出口和蒸发器入口。 EEV包括阀构件，其被选择性地定位成建立期望的开口以将制冷剂从冷凝器传递到蒸发器。控制器电连接到EEV和压缩机速度传感器。控制器基于冷却模式过热值和加热模式超热值以及压缩机的操作速度之一建立阀构件的期望打开。

17. 发明申请

US20130037944A1 Chip Stack Packages Having Aligned Through Silicon Vias of Different Areas 审中-公开
标题翻译：芯片堆栈封装通过不同领域的硅片排列
公开(公告)号：US20130037944A1
公开(公告)日：2013-02-14
申请号：US13568367
申请日：2012-08-07
申请人： Byung-Hyun Lee , Hoon Lee
发明人： Byung-Hyun Lee , Hoon Lee
IPC分类号： H01L23/488
CPC分类号： H01L24/14 , H01L23/481 , H01L24/13 , H01L24/16 , H01L24/17 , H01L25/0657 , H01L2224/02372 , H01L2224/0401 , H01L2224/0557 , H01L2224/13007 , H01L2224/13025 , H01L2224/13111 , H01L2224/13124 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/1403 , H01L2224/16146 , H01L2224/1703 , H01L2224/17181 , H01L2224/29099 , H01L2224/73204 , H01L2225/06513 , H01L2225/06517 , H01L2225/06544 , H01L2225/06565 , H01L2924/00014 , H01L2224/05552
摘要： A chip stack package includes a first semiconductor chip, a second semiconductor chip and a third semiconductor chip. The first semiconductor chip includes a first through silicon via that extends through the first semiconductor chip. The second semiconductor chip is stacked on the first semiconductor chip, and includes a second through silicon via that extends through the second semiconductor chip. The second through silicon via is disposed on the first through silicon via, and has a cross-sectional area smaller than that of the first through silicon via. The third semiconductor chip is stacked on the first semiconductor chip, and includes a third through silicon via that extends through the third semiconductor chip. The third through silicon via is disposed on the second through silicon via, and has a cross-sectional area smaller than that of the second through silicon via.
摘要翻译：芯片堆叠封装包括第一半导体芯片，第二半导体芯片和第三半导体芯片。第一半导体芯片包括延伸穿过第一半导体芯片的第一通孔硅通孔。第二半导体芯片堆叠在第一半导体芯片上，并且包括延伸穿过第二半导体芯片的第二通孔硅通孔。第二通硅通孔设置在第一通孔硅通孔上，并且具有小于第一通硅通孔的横截面面积。第三半导体芯片堆叠在第一半导体芯片上，并且包括延伸穿过第三半导体芯片的第三通孔硅通孔。第三贯通硅通孔设置在第二贯通硅通孔上，其截面积小于第二通硅通孔的横截面面积。

18. 发明授权

US08369123B2 Stacked memory module and system 有权
标题翻译：堆叠内存模块和系统
公开(公告)号：US08369123B2
公开(公告)日：2013-02-05
申请号：US13535363
申请日：2012-06-28
申请人： Uk-Song Kang , Hoe-Ju Chung , Jang-Seok Choi , Hoon Lee
发明人： Uk-Song Kang , Hoe-Ju Chung , Jang-Seok Choi , Hoon Lee
IPC分类号： G11C5/02
CPC分类号： G11C5/02 , G11C5/025 , G11C5/04 , G11C8/12 , G11C8/18 , G11C29/14 , H01L23/481 , H01L25/0657 , H01L2224/05001 , H01L2224/05026 , H01L2224/05548 , H01L2224/05573 , H01L2224/13025 , H01L2224/16145 , H01L2924/00014 , H01L2924/15311 , H01L2224/05599 , H01L2224/05099
摘要： A three dimensional memory module and system are formed with at least one slave chip stacked over a master chip. Through semiconductor vias (TSVs) are formed through at least one of the master and slave chips. The master chip includes a memory core for increased capacity of the memory module/system. In addition, capacity organizations of the three dimensional memory module/system resulting in efficient wiring is disclosed for forming multiple memory banks, multiple bank groups, and/or multiple ranks of the three dimensional memory module/system.
摘要翻译：三维存储器模块和系统形成有在主芯片上堆叠的至少一个从芯片。通过半导体通孔（TSV）通过主芯片和从芯片中的至少一个形成。主芯片包括用于增加存储器模块/系统容量的存储器核心。此外，公开了形成有效布线的三维存储器模块/系统的容量组织，用于形成三维存储器模块/系统的多个存储器组，多个存储体组和/或多个等级。

19. 发明授权

US08197522B2 Pedicle screw and operating device thereof 有权
标题翻译：椎弓根螺钉及其操作装置
公开(公告)号：US08197522B2
公开(公告)日：2012-06-12
申请号：US12061326
申请日：2008-04-02
申请人： Keun Ho Park , Jong Myeon Choi , Hoon Lee
发明人： Keun Ho Park , Jong Myeon Choi , Hoon Lee
IPC分类号： A61B17/88
CPC分类号： A61B17/7032 , A61B17/7089 , A61B17/864
摘要： Disclosed is a spine fixation apparatus, more particularly, a pedicle screw implanted into a spine and an operating device for the pedicle screw capable of easily inserting a rod to a head 5 section of the pedicle screw in order to securely fix the spine. The pedicle screw has a head section including a recess part defined by first and second sidewalls, a screw section, and a support unit formed at an upper portion of the recess part of the head section while connecting the first sidewall to the second sidewall.
摘要翻译：公开了一种脊柱固定装置，更具体地，植入脊柱的椎弓根螺钉和用于能够容易地将杆插入椎弓根螺钉的头部5的椎弓根螺钉的操作装置，以便可靠地固定脊柱。椎弓根螺钉具有头部，头部包括由第一和第二侧壁限定的凹部，螺钉部和形成在头部的凹部的上部的支撑单元，同时将第一侧壁连接到第二侧壁。

20. 发明申请

US20110292708A1 3D SEMICONDUCTOR DEVICE 有权
公开(公告)号：US20110292708A1
公开(公告)日：2011-12-01
申请号：US13115501
申请日：2011-05-25
申请人： Uk-song Kang , Dong-hyeon Jang , Seong-jin Jang , Hoon Lee , Jin-ho Kim , Nam-seog Kim , Byung-sik Moon , Woo-dong Lee
发明人： Uk-song Kang , Dong-hyeon Jang , Seong-jin Jang , Hoon Lee , Jin-ho Kim , Nam-seog Kim , Byung-sik Moon , Woo-dong Lee
IPC分类号： G11C5/06 , H01L21/66 , H01L21/50 , G11C8/18 , H01L23/48
CPC分类号： H01L23/481 , G11C5/06 , G11C8/18 , H01L22/32 , H01L24/05 , H01L24/16 , H01L24/17 , H01L24/73 , H01L24/94 , H01L25/0657 , H01L25/50 , H01L2224/0401 , H01L2224/05009 , H01L2224/0557 , H01L2224/05572 , H01L2224/16145 , H01L2224/16146 , H01L2224/17051 , H01L2224/17515 , H01L2224/73204 , H01L2224/94 , H01L2225/06513 , H01L2225/06544 , H01L2225/06596 , H01L2924/00014 , H01L2924/0002 , H01L2924/01006 , H01L2924/01023 , H01L2924/01033 , H01L2924/01047 , H01L2924/01055 , H01L2924/014 , H01L2924/10329 , H01L2924/12042 , H01L2924/14 , H01L2924/15311 , H01L2224/05552 , H01L2924/00
摘要： A three-dimensional (3D) semiconductor device may include a stack of chips, including a master chip and one or more slave chips. I/O connections of slave chips need not be connected to channels on a motherboard, and only electrode pads of a master chip may be connected to the channels. Only the master chip may provide a load to the channels. A through-substrate via (TSV) boundary may be set on a data input path, a data output path, an address/command path, and/or a clock path of a semiconductor device in which the same type of semiconductor chips are stacked.
摘要翻译：三维（3D）半导体器件可以包括一堆芯片，包括主芯片和一个或多个从芯片。从芯片的I / O连接不需要连接到主板上的通道，只有主芯片的电极焊盘可以连接到通道。只有主芯片可以为通道提供负载。可以在堆叠相同类型的半导体芯片的半导体器件的数据输入路径，数据输出路径，地址/命令路径和/或时钟路径上设置贯穿衬底通孔（TSV）边界。

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