专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

11. 发明授权

US5339396A Interconnection network and crossbar switch for the same 失效
标题翻译：互联网和交叉开关为一体
公开(公告)号：US5339396A
公开(公告)日：1994-08-16
申请号：US119601
申请日：1993-09-10
申请人： Akira Muramatsu , Ikuo Yoshihara , Kazuo Nakao , Takehisa Hayashi , Teruo Tanaka , Shigeo Nagashima
发明人： Akira Muramatsu , Ikuo Yoshihara , Kazuo Nakao , Takehisa Hayashi , Teruo Tanaka , Shigeo Nagashima
IPC分类号： G06F13/40 , G06F15/173 , G06F13/00
CPC分类号： G06F15/17375 , G06F13/4022 , G06F15/17381
摘要： In a parallel computer including L=n.sub.1 x n.sub.2 x - - - x n.sub.N processor element or external devices (hereafter represented by processor elements), an interconnection network of processor elements using L x (1/n.sub.1 +1/n.sub.2 +- - - +1/n.sub.N) crossbar switches in total comprises N dimensional lattice coordinates (i.sub.1, i.sub.2, - - - , i.sub.N) , 0.ltoreq.i.sub.1 .ltoreq.n.sub.1-1, 0.ltoreq.i.sub.2 .ltoreq.n.sub.2-1, - - - , 0.ltoreq.i.sub.n .ltoreq.n.sub.N-1 given to each processor element as the processor element number, crossbar switches for decoding a dimensional field in a processor element number having specific position and length depending upon the number of lattice points of a particular dimension and for performing the switching operation with regard to the dimension, interconnection of n.sub.k processor elements having processor element numbers, which are different only in the k-th dimensional coordinate for arbitrary k, i.e., having processor element numbers ##EQU1## by using one of the crossbar switches, each of the crossbar switches having n.sub.k inputs and n.sub.k outputs, and the interconnection performed with respect to all (L/n.sub.k sets) of coordinates(i.sub.1, i.sub.2, - - - , n.sub.k-1, n.sub.k+1, - - - , i.sub.N)of N-1 dimensional subspace excluding the k-th dimension, the interconnection being further performed for all values of k (1.ltoreq.k.ltoreq.N).
摘要翻译：在包括L = n 1 x n 2 x - - - x n N个处理器元件或者外部设备（以下由处理器元件表示）的并行计算机中，使用L x（1 / n1 + 1 / n2 + - - + 1 / nN）交叉开关总共包括N维网格坐标（i1，i2，...，iN），0 （ i1，i2，...，1，...，iN）。。。（i1，i2，...，nk-1，...，iN）通过使用一个交叉开关，每个交叉开关具有nk个输入和nk个输出，并且相对于所有（L / nk组）除了第k维之外的N-1维子空间的坐标（i1，i2， - - ，nk-1，nk + 1， - - ，iN），对于 k（1

12. 发明授权

US5517619A Interconnection network and crossbar switch for the same 失效
标题翻译：互联网和交叉开关为一体
公开(公告)号：US5517619A
公开(公告)日：1996-05-14
申请号：US203265
申请日：1994-02-28
申请人： Akira Muramatsu , Ikuo Yoshihara , Kazuo Nakao , Takehisa Hayashi , Teruo Tanaka , Shigeo Nagashima
发明人： Akira Muramatsu , Ikuo Yoshihara , Kazuo Nakao , Takehisa Hayashi , Teruo Tanaka , Shigeo Nagashima
IPC分类号： G06F13/40 , G06F15/173 , G06F13/38
CPC分类号： G06F15/17375 , G06F13/4022 , G06F15/17381
摘要： In a parallel computer including L=n.sub.1 .times.n.sub.2 .times. - - - .times.n.sub.N processor element or external devices (hereafter represented by processor elements), an interconnection network of processor elements using L.times.(1/n.sub.1 +1/n.sub.2 + - - - +1/n.sub.N) crossbar switches in total comprises N dimensional lattice coordinates (i.sub.1, i.sub.2, - - - , i.sub.N), 0.ltoreq.i.sub.1 .ltoreq.n.sub.1 -1, 0.ltoreq.i.sub.2 .ltoreq.n.sub.2 -1; - - - , 0.ltoreq.i.sub.N ; and .ltoreq.n.sub.N -1 given to each processor element as the processor element number, crossbar switches for decoding a dimensional field in a processor element number having specific position and length depending upon the number of lattice points of a particular dimension and for performing the switching operation with regard to the dimension, interconnection of n.sub.k processor elements having processor element numbers, which are different only in the k-th dimensional coordinate for arbitrary k, i.e., having processor element numbers ##EQU1## by using one of the crossbar switches, each of the crossbar switches having n.sub.k inputs and n.sub.k outputs, and the interconnection performed with respect to all (L/n.sub.k sets) of coordinates (i.sub.1, i.sub.2, - - - , i.sub.k-1, i.sub.k+1, - - - , i.sub.N) of N-1 dimensional subspace excluding the k-th dimension, the interconnection being further performed for all values of k (1.ltoreq.k.ltoreq.N).
摘要翻译：在包括L = n1xn2x - - - xnN处理器元件或以外的设备（以下由处理器元件表示）的并行计算机中，使用Lx（1 / n1 + 1 / n2 + - - + 1 / nN）交叉开关的处理器元件的互连网络总共包括N维网格坐标（i1，i2，...，iN），0

13. 发明授权

US5742766A Parallel computing system for synchronizing processors by using partial switch circuits for broadcasting messages after receiving synchronization signals and judging synchronization thereof 失效
标题翻译：并行计算系统，用于通过使用部分开关电路来同步处理器，用于在接收同步信号之后广播消息并且判断其同步
公开(公告)号：US5742766A
公开(公告)日：1998-04-21
申请号：US34805
申请日：1993-03-19
申请人： Shigeo Takeuchi , Hideo Wada , Naoki Hamanaka , Junji Nakagoshi , Teruo Tanaka , Yasuhiro Ogata , Taturu Toba , Mitsuyoshi Igai
发明人： Shigeo Takeuchi , Hideo Wada , Naoki Hamanaka , Junji Nakagoshi , Teruo Tanaka , Yasuhiro Ogata , Taturu Toba , Mitsuyoshi Igai
IPC分类号： G06F9/52 , G06F15/173 , G06F15/80 , G06F13/12
CPC分类号： G06F15/17343 , G06F15/17381
摘要： An operation complete signal and a convergence result signal from each processor are transferred to the X-direction interconnection switches, AND of these signals is obtained in switch units in each interconnection switch, the signal is sent out to all the Y-direction interconnection switches through a synchronizing signal relay switch and the like in each relay switch, AND of these signals is obtained in each switch unit in the interconnection switches, and the result thereof is transferred to each processor through each synchronizing signal relay switch. With this, a logical product of an operation complete signal and a logical product of a convergence result signal from all the processors are sent in parallel to all the processors.
摘要翻译：来自每个处理器的操作完成信号和收敛结果信号被传送到X方向互连开关，并且这些信号的AND在每个互连开关中以开关单元获得，该信号被发送到所有Y方向互连开关，通过每个继电器开关中的同步信号继电器开关等，在互连开关中的每个开关单元中获得这些信号的AND，并且其结果通过每个同步信号继电器开关传送到每个处理器。由此，来自所有处理器的操作完成信号和收敛结果信号的逻辑积的逻辑积并行发送到所有处理器。

14. 发明授权

US5710932A Parallel computer comprised of processor elements having a local memory and an enhanced data transfer mechanism 失效
标题翻译：由具有本地存储器和增强型数据传输机构的处理器元件组成的并行计算机
公开(公告)号：US5710932A
公开(公告)日：1998-01-20
申请号：US215262
申请日：1994-03-21
申请人： Naoki Hamanaka , Teruo Tanaka
发明人： Naoki Hamanaka , Teruo Tanaka
IPC分类号： G06F15/17 , G06F13/00
CPC分类号： G06F15/17
摘要： A parallel computer includes a plurality of processor elements (1-1 to 1-n) connected by a network (2); each processor element includes a local memory (6) for holding a program and related data, a processor (3) for performing an instruction in said program, a circuit (5) for transferring data to other processor elements, and a circuit (4) for receiving data sent from another processor element; a memory area (92,8) includes of a plurality of reception data areas for temporarily storing data received by said receiving circuit, and memory (92,8) constructed of a plurality of tag areas, provided for each reception data area, for storing a data tag indicating validity of data in the corresponding reception data area; a transmitting circuit (5) for transmitting data with an attached data identifier predetermined by said data; a circuit for writing the data into one of the plurality of reception data areas in response to data received from the network, and writing valid data tag into one of said plurality of reception data areas, the receiving circuit being parallelly-operated with the processor; and, an access circuit (38) for reading both data and tag from one of the reception data areas determined by the data identifier and from the corresponding tag areas, in response to a data identifier designated by the instruction which is produced from said program for requiring data reception, and for repeatedly reading a tag and data from the tag reception data areas until a valid data tag is read therefrom.
摘要翻译：并行计算机包括由网络（2）连接的多个处理器元件（1-1至1-n）; 每个处理器元件包括用于保存程序和相关数据的本地存储器（6），用于执行所述程序中的指令的处理器（3），用于将数据传送到其他处理器元件的电路（5）用于接收从另一处理器元件发送的数据; 存储区域（92,8）包括用于临时存储由所述接收电路接收的数据的多个接收数据区域以及为每个接收数据区域提供的多个标签区域构成的存储器（92,8），用于存储指示对应的接收数据区域中的数据的有效性的数据标签; 发送电路（5），用于利用由所述数据预先确定的附加数据标识符发送数据; 用于响应于从网络接收到的数据将数据写入多个接收数据区之一并将有效数据标签写入所述多个接收数据区之一的电路，所述接收电路与所述处理器并行操作; 以及访问电路（38），用于响应于由所述程序产生的指令指定的数据标识符，用于从由数据标识符确定的接收数据区域中的一个和相应的标签区域读取数据和标签，需要数据接收，并且用于从标签接收数据区重复读取标签和数据，直到从其读取有效的数据标签。

15. 发明授权

US5088034A Compiling method for determining programs to be executed parallelly by respective processors in a parallel computer which transfer data with a data identifier to other processors 失效
标题翻译：用于确定由并行计算机中的各个处理器并行地执行程序的编译方法，该并行计算机将具有数据标识符的数据传送到其他处理器
公开(公告)号：US5088034A
公开(公告)日：1992-02-11
申请号：US301648
申请日：1989-01-25
申请人： Sigeo Ihara , Teruo Tanaka , Kyoko Iwasawa , Naoki Hamanaka
发明人： Sigeo Ihara , Teruo Tanaka , Kyoko Iwasawa , Naoki Hamanaka
IPC分类号： G06F15/16 , G06F9/44 , G06F9/45
CPC分类号： G06F8/45
摘要： A compiler for generating from a serially processed type source program described in a high level language the object codes to be executed in parallel by a parallel processor system which is composed of a plurality of processors marked with respective identification numbers and in which inter-processor data transfer system for identifying data for transfer by data identifiers is adopted. The serially executed source program is first translated to programs to be executed in parallel. The inter-processor data transfer processing is extracted from the flow of processings involved in executing the programs for parallel execution resulting from the above-mentioned translation, and all the interprocessor data transfer processings are attached with data identifiers such that no overlap takes place.
摘要翻译：一种编译器，用于从由高级语言描述的串行处理型源程序生成由并行处理器系统并行执行的目标代码，该并行处理器系统由标有相应标识号的多个处理器组成，并且其中处理器间数据采用用于识别用于由数据标识符传送的数据的传送系统。串行执行的源程序首先被翻译成要并行执行的程序。从执行由上述翻译产生的并行执行程序所涉及的处理流程中提取处理器间数据传送处理，并且所有处理器间数据传送处理都附加有不发生重叠的数据标识符。

16. 发明授权

US5826049A Partial broadcast method in parallel computer and a parallel computer suitable therefor 失效
标题翻译：并行计算机中的部分广播方法和适用于其的并行计算机
公开(公告)号：US5826049A
公开(公告)日：1998-10-20
申请号：US916630
申请日：1992-07-22
申请人： Yasuhiro Ogata , Junji Nakagoshi , Naoki Hamanaka , Hiroyuki Chiba , Shinichi Shutoh , Tatsuo Higuchi , Shigeo Takeuchi , Taturu Toba , Teruo Tanaka
发明人： Yasuhiro Ogata , Junji Nakagoshi , Naoki Hamanaka , Hiroyuki Chiba , Shinichi Shutoh , Tatsuo Higuchi , Shigeo Takeuchi , Taturu Toba , Teruo Tanaka
IPC分类号： G06F15/173 , G06F15/80 , G06F15/163
CPC分类号： G06F15/17368
摘要： In order to determine a transfer path of a message to a receiving-end processor group, a processor includes a routing bit generation circuit, and an exchange switch includes partial broadcast path control circuits and a path control information alteration circuit. In order to define the range of a receiving-end processor group, a network includes transfer control circuits. A crossbar switch includes transfer control circuits associated with output ports and a boundary register group. When a partial broadcast message is transferred from an input port in the downstream direction of an output port, it is decided whether a belonging to the partial broadcast range associated with a connected to the particular input port is connected to the particular output port, whereby the particular partial broadcast message is transferred from the same output port.
摘要翻译：为了确定消息到接收端处理器组的传送路径，处理器包括路由位生成电路，并且交换交换机包括部分广播路径控制电路和路径控制信息改变电路。为了定义接收端处理器组的范围，网络包括传送控制电路。交叉开关包括与输出端口和边界寄存器组相关联的传输控制电路。当在输出端口的下游方向上从输入端口传送部分广播消息时，确定属于与连接到特定输入端口的连接的部分广播范围是否连接到特定输出端口，由此特定的部分广播消息从相同的输出端口传送。

17. 发明授权

US5754792A Switch circuit comprised of logically split switches for parallel transfer of messages and a parallel processor system using the same 失效
标题翻译：由用于并行传送消息的逻辑分割开关组成的开关电路和使用该开关的并行处理器系统
公开(公告)号：US5754792A
公开(公告)日：1998-05-19
申请号：US34359
申请日：1993-03-19
申请人： Shinichi Shutoh , Junji Nakagoshi , Naoki Hamanaka , Shigeo Takeuchi , Teruo Tanaka
发明人： Shinichi Shutoh , Junji Nakagoshi , Naoki Hamanaka , Shigeo Takeuchi , Teruo Tanaka
IPC分类号： G06F11/14 , G06F15/173 , H04L12/56 , H04Q11/04 , G06F13/00
CPC分类号： G06F15/17375 , G06F11/1443 , H04L49/1576 , H04L49/256 , H04Q11/0478
摘要： A parallel processor system including a plurality of processors. When packets of same destination PE number are inputted from different ports, the destination PE number is added with ID numbers of leading ports of split crossbar switches to which the different input ports belong, respectively, by using respective addition circuits, to thereby determine a transfer destination output port for the packets. A plurality of the split crossbar switches having different numbers of input/output ports are realized by partitioning a crossbar switch. By means of an input port select circuit provided in association with each of the output ports, an output request for the packet from the input port belonging to the split crossbar switch to which the associated output port belongs is accepted, while output requests for the packets from the input ports belonging to the other split crossbar switches are inhibited from being accepted, whereby transfer of broadcast packets are inhibited between the split crossbar switches belonging to a physically same crossbar switch. Such situation can be evaded in which same broadcast packets arrive at one and the same processor a number of times.
摘要翻译：一种并行处理器系统，包括多个处理器。当从不同的端口输入相同的目的地PE号码的分组时，通过使用各自的加法电路，分别将目的地PE号码分别与不同的输入端口所属的分离的交叉开关的前导端口的ID号相加，从而确定传送目标输出端口为数据包。通过划分交叉开关来实现具有不同数量的输入/输出端口的多个分开的交叉开关。通过与每个输出端口相关联地提供的输入端口选择电路，接收来自属于相关联的输出端口所属的分离交叉开关的输入端口的分组的输出请求，同时对分组的输出请求从属于其他分割交叉开关的输入端口被禁止被接受，从而在属于物理上相同的交叉开关的分开的交叉开关之间禁止广播分组的传送。可以避免这种情况，其中相同的广播分组多次到达同一个处理器。

18. 发明授权

US5437043A Information processing apparatus having a register file used interchangeably both as scalar registers of register windows and as vector registers 失效
标题翻译：具有可互换使用的寄存器文件作为寄存器窗口的标量寄存器和向量寄存器的信息处理装置
公开(公告)号：US5437043A
公开(公告)日：1995-07-25
申请号：US979327
申请日：1992-11-20
申请人： Hiroaki Fujii , Naoki Hamanaka , Teruo Tanaka , Yasuhiro Inagami , Yoshiko Tamaki
发明人： Hiroaki Fujii , Naoki Hamanaka , Teruo Tanaka , Yasuhiro Inagami , Yoshiko Tamaki
IPC分类号： G06F9/30 , G06F9/318 , G06F9/26 , G06F9/28 , G06F9/40
CPC分类号： G06F9/30127 , G06F9/30112 , G06F9/30138
摘要： An arrangement having a register file having registers greater in number than those which are designated by an instruction, a pipeline ALU, a current window pointer and window number modifier operating in a register window mode, an element counter and address counter operating in a vector register mode, and register determining circuits for determining physical register numbers from the register numbers designated by an instruction in one of the two modes. Each register determining circuit has a first register determining circuit using an output of the window number modifier, for using the register file as a register window configuration, and a second register determining circuit using an output of the element counter, for using the register file as a vector register configuration. Physical registers of the register file are used as scalar registers in the register window mode, and used as vector registers in the vector register modes.
摘要翻译：一种具有寄存器文件的布置，其寄存器数量大于由指令指定的寄存器文件，流水线ALU，以寄存器窗口模式操作的当前窗口指针和窗口编号修改器，在向量寄存器中操作的元件计数器和地址计数器模式和寄存器确定电路，用于根据由两种模式之一指令指定的寄存器号来确定物理寄存器号。每个寄存器确定电路具有使用窗口编号修改器的输出的第一寄存器确定电路，用于使用寄存器文件作为寄存器窗口配置，以及使用元件计数器的输出的第二寄存器确定电路，用于将寄存器文件用作矢量寄存器配置。寄存器文件的物理寄存器在寄存器窗口模式下用作标量寄存器，并用作向量寄存器模式中的向量寄存器。

19. 发明授权

US4910667A Vector processor with vector buffer memory for read or write of vector data between vector storage and operation unit 失效
标题翻译：矢量处理器，带矢量缓冲存储器，用于在矢量存储和操作单元之间读取或写入矢量数据
公开(公告)号：US4910667A
公开(公告)日：1990-03-20
申请号：US184788
申请日：1988-04-22
申请人： Teruo Tanaka , Koichiro Omoda , Yasuhiro Inagami , Takayuki Nakagawa , Mamoru Sugie , Shigeo Nagashima
发明人： Teruo Tanaka , Koichiro Omoda , Yasuhiro Inagami , Takayuki Nakagawa , Mamoru Sugie , Shigeo Nagashima
IPC分类号： G06F12/08 , G06F15/78 , G06F17/16
CPC分类号： G06F15/8053
摘要： In a vector processor having vector registers, a vector buffer storage for temporarily storing vector data is arranged closer to the vector registers than to a main storage, and a vector buffer storage control including an identification storage for storing identification information of the vector data stored at storage locations of the buffer storage and a check circuit for checking if the vector data identification information is in the identificatgion storage is provided. The vector buffer storage control checks if the identification information of the vector data designated by a vector data fetch instruction for the main storage is in the indentification storage, and if it is in the identification storage, it fetches the vector data from the buffer storage and transfers it to the vector register, and if it is not in the identification storage, it instructs to fetch the vector data from the main storage, transfers the vector data fetched from the main storage to the vector register and stores it into the buffer storage.
摘要翻译：在具有向量寄存器的向量处理器中，用于临时存储向量数据的向量缓冲存储器比向主存储器靠近向量寄存器布置，并且向量缓冲器存储控制包括用于存储存储在提供缓冲存储器的存储位置和用于检查矢量数据识别信息是否在识别存储器中的检查电路。向量缓冲存储控制检查由主存储器的矢量数据获取指令指定的矢量数据的识别信息是否在识别存储器中，并且如果它在识别存储器中，则从缓冲存储器中取出向量数据，将其传送到向量寄存器，如果不在识别存储器中，则指示从主存储器获取向量数据，将从主存储器获取的向量数据传送到向量寄存器，并将其存储到缓冲存储器中。

20. 发明授权

US4782441A Vector processor capable of parallely executing instructions and reserving execution status order for restarting interrupted executions 失效
标题翻译：能够平行执行指令并保留执行状态顺序的矢量处理器重新启动中断的执行
公开(公告)号：US4782441A
公开(公告)日：1988-11-01
申请号：US872396
申请日：1986-06-10
申请人： Yasuhiro Inagami , Shigeo Nagashima , Koichiro Omoda , Takayuki Nakagawa , Teruo Tanaka
发明人： Yasuhiro Inagami , Shigeo Nagashima , Koichiro Omoda , Takayuki Nakagawa , Teruo Tanaka
IPC分类号： G06F9/46 , G06F9/38 , G06F9/48 , G06F15/78 , G06F17/16 , G06F9/28 , G06F7/00
CPC分类号： G06F15/8053
摘要： In a processor such as a vector processor in which a plurality of data are processed by one instruction and a plurality of instructions are parallely processed, apparatus is provided for storing, during an interruption of the program currently being executed, the instructions being executed in the conceptual order of appearance in the program of the instruction being executed, and the sequential count of the sets of data processed. The stored information is used to restart the execution of the interrupted program at the appropriate point.
摘要翻译：在其中通过一个指令处理多个数据并且多个指令并行处理的诸如矢量处理器的处理器中，提供装置，用于在当前执行的程序的中断期间存储在正在执行的指令的程序中出现的概念顺序，以及处理的数据组的顺序计数。存储的信息用于在适当的点重新启动中断的程序的执行。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式