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1. 发明授权

US5339396A Interconnection network and crossbar switch for the same 失效
标题翻译：互联网和交叉开关为一体
公开(公告)号：US5339396A
公开(公告)日：1994-08-16
申请号：US119601
申请日：1993-09-10
申请人： Akira Muramatsu , Ikuo Yoshihara , Kazuo Nakao , Takehisa Hayashi , Teruo Tanaka , Shigeo Nagashima
发明人： Akira Muramatsu , Ikuo Yoshihara , Kazuo Nakao , Takehisa Hayashi , Teruo Tanaka , Shigeo Nagashima
IPC分类号： G06F13/40 , G06F15/173 , G06F13/00
CPC分类号： G06F15/17375 , G06F13/4022 , G06F15/17381
摘要： In a parallel computer including L=n.sub.1 x n.sub.2 x - - - x n.sub.N processor element or external devices (hereafter represented by processor elements), an interconnection network of processor elements using L x (1/n.sub.1 +1/n.sub.2 +- - - +1/n.sub.N) crossbar switches in total comprises N dimensional lattice coordinates (i.sub.1, i.sub.2, - - - , i.sub.N) , 0.ltoreq.i.sub.1 .ltoreq.n.sub.1-1, 0.ltoreq.i.sub.2 .ltoreq.n.sub.2-1, - - - , 0.ltoreq.i.sub.n .ltoreq.n.sub.N-1 given to each processor element as the processor element number, crossbar switches for decoding a dimensional field in a processor element number having specific position and length depending upon the number of lattice points of a particular dimension and for performing the switching operation with regard to the dimension, interconnection of n.sub.k processor elements having processor element numbers, which are different only in the k-th dimensional coordinate for arbitrary k, i.e., having processor element numbers ##EQU1## by using one of the crossbar switches, each of the crossbar switches having n.sub.k inputs and n.sub.k outputs, and the interconnection performed with respect to all (L/n.sub.k sets) of coordinates(i.sub.1, i.sub.2, - - - , n.sub.k-1, n.sub.k+1, - - - , i.sub.N)of N-1 dimensional subspace excluding the k-th dimension, the interconnection being further performed for all values of k (1.ltoreq.k.ltoreq.N).
摘要翻译：在包括L = n 1 x n 2 x - - - x n N个处理器元件或者外部设备（以下由处理器元件表示）的并行计算机中，使用L x（1 / n1 + 1 / n2 + - - + 1 / nN）交叉开关总共包括N维网格坐标（i1，i2，...，iN），0 （ i1，i2，...，1，...，iN）。。。（i1，i2，...，nk-1，...，iN）通过使用一个交叉开关，每个交叉开关具有nk个输入和nk个输出，并且相对于所有（L / nk组）除了第k维之外的N-1维子空间的坐标（i1，i2， - - ，nk-1，nk + 1， - - ，iN），对于 k（1

2. 发明授权

US5517619A Interconnection network and crossbar switch for the same 失效
标题翻译：互联网和交叉开关为一体
公开(公告)号：US5517619A
公开(公告)日：1996-05-14
申请号：US203265
申请日：1994-02-28
申请人： Akira Muramatsu , Ikuo Yoshihara , Kazuo Nakao , Takehisa Hayashi , Teruo Tanaka , Shigeo Nagashima
发明人： Akira Muramatsu , Ikuo Yoshihara , Kazuo Nakao , Takehisa Hayashi , Teruo Tanaka , Shigeo Nagashima
IPC分类号： G06F13/40 , G06F15/173 , G06F13/38
CPC分类号： G06F15/17375 , G06F13/4022 , G06F15/17381
摘要： In a parallel computer including L=n.sub.1 .times.n.sub.2 .times. - - - .times.n.sub.N processor element or external devices (hereafter represented by processor elements), an interconnection network of processor elements using L.times.(1/n.sub.1 +1/n.sub.2 + - - - +1/n.sub.N) crossbar switches in total comprises N dimensional lattice coordinates (i.sub.1, i.sub.2, - - - , i.sub.N), 0.ltoreq.i.sub.1 .ltoreq.n.sub.1 -1, 0.ltoreq.i.sub.2 .ltoreq.n.sub.2 -1; - - - , 0.ltoreq.i.sub.N ; and .ltoreq.n.sub.N -1 given to each processor element as the processor element number, crossbar switches for decoding a dimensional field in a processor element number having specific position and length depending upon the number of lattice points of a particular dimension and for performing the switching operation with regard to the dimension, interconnection of n.sub.k processor elements having processor element numbers, which are different only in the k-th dimensional coordinate for arbitrary k, i.e., having processor element numbers ##EQU1## by using one of the crossbar switches, each of the crossbar switches having n.sub.k inputs and n.sub.k outputs, and the interconnection performed with respect to all (L/n.sub.k sets) of coordinates (i.sub.1, i.sub.2, - - - , i.sub.k-1, i.sub.k+1, - - - , i.sub.N) of N-1 dimensional subspace excluding the k-th dimension, the interconnection being further performed for all values of k (1.ltoreq.k.ltoreq.N).
摘要翻译：在包括L = n1xn2x - - - xnN处理器元件或以外的设备（以下由处理器元件表示）的并行计算机中，使用Lx（1 / n1 + 1 / n2 + - - + 1 / nN）交叉开关的处理器元件的互连网络总共包括N维网格坐标（i1，i2，...，iN），0

3. 发明授权

US5867679A Parallel processor system with asynchronous data transmission by a data producing processor to a data using processor employing controlled execution of a program by the data using processor for processing the data 失效
标题翻译：并行处理器系统，其通过数据产生处理器将异步数据传输到使用处理器的数据的数据采用由数据使用处理器处理数据的数据的受控执行程序
公开(公告)号：US5867679A
公开(公告)日：1999-02-02
申请号：US647773
申请日：1991-01-30
申请人： Teruo Tanaka , Naoki Hamanaka , Koichiro Omoda , Shigeo Nagashima , Akira Muramatsu , Ikuo Yoshihara , Kazuo Nakao , Junji Nakagoshi , Kazuo Ojima
发明人： Teruo Tanaka , Naoki Hamanaka , Koichiro Omoda , Shigeo Nagashima , Akira Muramatsu , Ikuo Yoshihara , Kazuo Nakao , Junji Nakagoshi , Kazuo Ojima
IPC分类号： G06F9/44 , G06F15/17 , G06F15/80 , G06F15/82
CPC分类号： G06F15/8015 , G06F9/4494 , G06F15/17
摘要： A parallel computer system includes a plurality of processors, each of which is placed in data communication with an interconnecting network. Pairs of a data signal and a data identification code, predetermined for the data signal, are received by each processor and stored in a memory. Structure is provided for reading a data signal belonging to one of the pairs having a data identification code designated by a data readout instruction.
摘要翻译：并行计算机系统包括多个处理器，每个处理器与互连网络进行数据通信。数据信号对和数据信号预定的数据识别码由每个处理器接收并存储在存储器中。提供结构用于读取属于其中一对的数据信号，该数据信号具有由数据读出指令指定的数据识别码。

4. 发明授权

US5043873A Method of parallel processing for avoiding competition control problems and data up dating problems common in shared memory systems 失效
标题翻译：并行处理方法，用于避免共享内存系统中常见的竞争控制问题和数据上传问题
公开(公告)号：US5043873A
公开(公告)日：1991-08-27
申请号：US395444
申请日：1989-08-17
申请人： Akira Muramatsu , Kousuke Sakoda , Ikuo Yoshihara , Kazuo Nakao , Makoto Nohmi , Naoki Hamanaka , Shigeo Nagashima , Teruo Tanaka
发明人： Akira Muramatsu , Kousuke Sakoda , Ikuo Yoshihara , Kazuo Nakao , Makoto Nohmi , Naoki Hamanaka , Shigeo Nagashima , Teruo Tanaka
IPC分类号： G06F9/45 , G06F9/50
CPC分类号： G06F9/5016 , G06F8/451 , G06F2209/484
摘要： A plurality of elemental processors each include a local memory for storing data and task programs and an execution section for executing the task programs. A communications section transfers data among the processors. In a method of parallel processing with these elemental processors, a task program is executed in one of the processors. A detection operation is conducted to determine whether the data from the task program is to be copied to the local memories of other processors. The detection is based on predetermined information which is stored in the local memory of the processor which performs the task program and indicates which of the other processors will need the data. The detection also determines which of the other processors that will require access to the data are ready to receive the data. Concurrently and in parallel with the execution of the task program, the data is transmitted to each of the elemental processors that are awaiting the data with only a write instruction and without any communications instruction.

5. 发明授权

US4951193A Parallel computer with distributed shared memories and distributed task activating circuits 失效
标题翻译：具有分布式共享存储器和分布式任务激活电路的并行计算机
公开(公告)号：US4951193A
公开(公告)日：1990-08-21
申请号：US85646
申请日：1987-08-14
申请人： Akira Muramatsu , Kousuke Sakoda , Ikuo Yoshihara , Kazuo Nakao , Makoto Nohmi , Naoki Hamanaka , Shigeo Nagashima , Teruo Tanaka
发明人： Akira Muramatsu , Kousuke Sakoda , Ikuo Yoshihara , Kazuo Nakao , Makoto Nohmi , Naoki Hamanaka , Shigeo Nagashima , Teruo Tanaka
IPC分类号： G06F9/45 , G06F9/50
CPC分类号： G06F9/5016 , G06F8/451 , G06F2209/484
摘要： In accessing a memory, each element processor executes a program constructed so as to designate an address belonging to a predetermined local address area for each element processor. When a memory write instruction is executed by an element processor, it is detected if the memory address designated by the instruction coincides with a predetermined address. If detected, a predetermined address belonging to a local address space of another element processor and assigned to the first-mentioned predetermined address, and the data written in response to the write instruction, are sent to the other element processor to instruct the data to be written therein as a copy data. A next task to be executed is decided independently for each element processor.
摘要翻译：在访问存储器时，每个元件处理器执行构造成为每个元件处理器指定属于预定本地地址区域的地址的程序。当由元件处理器执行存储器写入指令时，检测由指令指定的存储器地址是否与预定地址一致。如果检测到，则属于另一元件处理器的本地地址空间并分配给首先提到的预定地址的预定地址以及响应写指令写入的数据被发送到另一元件处理器以指示数据为在其中写入作为复制数据。对于每个元件处理器独立地确定要执行的下一个任务。

6. 发明授权

US5129093A Method and apparatus for executing an operation request signal in a loosely coupled parallel computer having processor elements capable of updating memory contents and minimizing exclusive control of sharable distributed memories 失效
标题翻译：用于在松散耦合的并行计算机中执行操作请求信号的方法和装置，其具有能够更新存储器内容并且最小化可共享分布式存储器的排他控制的处理器元件
公开(公告)号：US5129093A
公开(公告)日：1992-07-07
申请号：US272550
申请日：1988-11-17
申请人： Akira Muramatsu , Ikuo Yoshihara , Kazuo Nakao
发明人： Akira Muramatsu , Ikuo Yoshihara , Kazuo Nakao
IPC分类号： G06F15/17
CPC分类号： G06F15/17
摘要： A parallel computer has an operation request function and a plurality of processor elements. Each processor element has a sharable distributed memory for holding data, and is interconnected to a network to permit communication. Each processor element comprises a request sent unit for sending an operation request message for causing another processor element connected to a memory module to execute a recursive defining operation. The memory module stores data to be recursively defined. Each processor element further comprises an operation request execution element for accepting a message from another processor, temporarily stopping any other operation of the processor element in accordance with the content of the message, and executing the requested operation. Registers are also used for executing the operation requested by the other processor in addition to the general purpose registers and floating point registers.
摘要翻译：并行计算机具有操作请求功能和多个处理器元件。每个处理器元件具有可共享的分布式存储器，用于保存数据，并且互连到网络以允许通信。每个处理器元件包括用于发送操作请求消息的请求发送单元，用于使连接到存储器模块的另一处理器元件执行递归定义操作。存储器模块存储要递归定义的数据。每个处理器元件还包括用于从另一个处理器接收消息的操作请求执行元件，根据消息的内容临时停止处理器元件的任何其它操作，并执行所请求的操作。除了通用寄存器和浮点寄存器之外，寄存器还用于执行另一个处理器所请求的操作。

7. 发明授权

US4644480A Reliability analyzing system for manufacturing processes 失效
标题翻译：制造工艺可靠性分析系统
公开(公告)号：US4644480A
公开(公告)日：1987-02-17
申请号：US672210
申请日：1984-11-16
申请人： Koichi Haruna , Kazuo Nakao , Tamotsu Nishiyama , Tsutomu Tashiro , Kuniaki Matsumoto , Nobuyuki Saida
发明人： Koichi Haruna , Kazuo Nakao , Tamotsu Nishiyama , Tsutomu Tashiro , Kuniaki Matsumoto , Nobuyuki Saida
IPC分类号： G05B19/418 , G06F19/00 , G06Q50/00 , G06Q50/04 , G07C3/14 , G06F15/46
CPC分类号： G06Q10/06 , G05B19/41875 , G07C3/14 , Y02P90/14 , Y02P90/22
摘要： A reliability analyzing system for manufacturing processes is disclosed, which comprises a computer system provided with a data memory device, a central processing device and input/output devices, terminals which input/output information into/from said computer system, and output devices for manufacturing sites; whereby said data memory device stores required specifications for each product, works for manufacturing and controlling processes, information relating to items, such as required specifications, works, control items, etc. and information mutually relating different items, and on the basis of the stored information, reliability analysis for each process is effected for all the processes and reliability analysis for each required specification is performed for all the required specifications.
摘要翻译：公开了一种用于制造过程的可靠性分析系统，其包括具有数据存储装置，中央处理装置和输入/输出装置的计算机系统，输入/输出信息到所述计算机系统中的终端和用于制造的输出装置网站由此所述数据存储装置存储每个产品所需的规格，制造和控制过程的工作，与所要求的规格，作品，控制项目等项目有关的信息以及相互不相关的物品的信息，以及存储的对所有过程进行每个过程的信息，可靠性分析，并针对所有要求的规格执行每个所需规格的可靠性分析。

8. 发明授权

US4943968A Method of displaying execution trace in a logic programming language processing system 失效
标题翻译：在逻辑编程语言处理系统中显示执行跟踪的方法
公开(公告)号：US4943968A
公开(公告)日：1990-07-24
申请号：US156459
申请日：1988-02-16
申请人： Tadashi Hirose , Kazuo Nakao , Keiko Shinada
发明人： Tadashi Hirose , Kazuo Nakao , Keiko Shinada
IPC分类号： G06F11/32 , G06F11/36
CPC分类号： G06F11/3664 , G06F11/323 , G06F11/3612 , G06F11/36
摘要： A sequence of calling clauses and all clauses in a procedure that includes the selected clauses are displayed simultaneously, and the present point of execution is displayed being overlapped on the above displays. In particular, the program source list of a procedure being processed is displayed, and the latest execution statuses of the executed terms are graphically displayed around the terms on the displayed program source list.
摘要翻译：包含所选择的子句的过程中的调用子句和所有子句的顺序同时显示，并且显示当前的执行点在上述显示器上重叠。特别地，显示正在处理的程序的程序源列表，并且所显示的程序源列表上的术语的图形地显示所执行的术语的最新执行状态。

9. 发明授权

US4794529A Method for displaying operation range of logical language 失效
标题翻译：显示逻辑语言操作范围的方法
公开(公告)号：US4794529A
公开(公告)日：1988-12-27
申请号：US895954
申请日：1986-08-13
申请人： Tadashi Hirose , Kazuo Nakao , Yoichi Takeuchi , Keiko Shinada
发明人： Tadashi Hirose , Kazuo Nakao , Yoichi Takeuchi , Keiko Shinada
IPC分类号： G06F9/44 , G06F11/28 , G06F11/32 , G06F11/36 , G06F1/00
CPC分类号： G06F11/3664 , G06F11/321 , G06F11/323 , G06F8/313
摘要： In order to improve the efficiency of test and debug procedure based on delarative program understanding of a program described by a logical language, the operation which has been executed for each procedure is grasped. On the basis of information relating to the grasped operation, the operation range of each procedure is expressed clearly by making thick only sides which have actually operated among four sides of a box-shaped figure surrounding each head term and end body term of each clause included in each procedure.
摘要翻译：为了提高基于对由逻辑语言描述的程序的描述性程序理解的测试和调试过程的效率，掌握了针对每个过程执行的操作。根据与抓握操作有关的信息，通过在每个条款的每个头项和结束体项围绕的四周内实际操作的厚实侧面，清楚地表示每个过程的操作范围在每个过程中。

10. 发明授权

US4794528A Pattern matching method for tree structured data 失效
标题翻译：树结构数据的模式匹配方法
公开(公告)号：US4794528A
公开(公告)日：1988-12-27
申请号：US15111
申请日：1987-02-17
申请人： Tadashi Hirose , Kazuo Nakao , Kousuke Sakoda , Youichi Takeuchi
发明人： Tadashi Hirose , Kazuo Nakao , Kousuke Sakoda , Youichi Takeuchi
IPC分类号： G06F9/44 , G06F17/30 , G06F1/00
CPC分类号： G06F8/3135 , G06F17/30985 , Y10S707/99936 , Y10S707/99942
摘要： In order to highly speed up the pattern matching of tree structured data in a logic programming language, the priority order is set when the data owned by the individual nodes of a tree structure are to be transversely sought, and the tree structured data are expressed in a vector type, in which they are arranged in that priority order, so that they are compared consecutively from the head for each element of the vector.
摘要翻译：为了以逻辑编程语言高度加速树结构化数据的模式匹配，当要横向寻求树结构的各个节点所拥有的数据时，设置优先顺序，并将树结构化数据表示为一种向量类型，它们按照该优先级顺序排列，从而从矢量的每个元素的头部连续进行比较。

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