专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US5742766A Parallel computing system for synchronizing processors by using partial switch circuits for broadcasting messages after receiving synchronization signals and judging synchronization thereof 失效
标题翻译：并行计算系统，用于通过使用部分开关电路来同步处理器，用于在接收同步信号之后广播消息并且判断其同步
公开(公告)号：US5742766A
公开(公告)日：1998-04-21
申请号：US34805
申请日：1993-03-19
申请人： Shigeo Takeuchi , Hideo Wada , Naoki Hamanaka , Junji Nakagoshi , Teruo Tanaka , Yasuhiro Ogata , Taturu Toba , Mitsuyoshi Igai
发明人： Shigeo Takeuchi , Hideo Wada , Naoki Hamanaka , Junji Nakagoshi , Teruo Tanaka , Yasuhiro Ogata , Taturu Toba , Mitsuyoshi Igai
IPC分类号： G06F9/52 , G06F15/173 , G06F15/80 , G06F13/12
CPC分类号： G06F15/17343 , G06F15/17381
摘要： An operation complete signal and a convergence result signal from each processor are transferred to the X-direction interconnection switches, AND of these signals is obtained in switch units in each interconnection switch, the signal is sent out to all the Y-direction interconnection switches through a synchronizing signal relay switch and the like in each relay switch, AND of these signals is obtained in each switch unit in the interconnection switches, and the result thereof is transferred to each processor through each synchronizing signal relay switch. With this, a logical product of an operation complete signal and a logical product of a convergence result signal from all the processors are sent in parallel to all the processors.
摘要翻译：来自每个处理器的操作完成信号和收敛结果信号被传送到X方向互连开关，并且这些信号的AND在每个互连开关中以开关单元获得，该信号被发送到所有Y方向互连开关，通过每个继电器开关中的同步信号继电器开关等，在互连开关中的每个开关单元中获得这些信号的AND，并且其结果通过每个同步信号继电器开关传送到每个处理器。由此，来自所有处理器的操作完成信号和收敛结果信号的逻辑积的逻辑积并行发送到所有处理器。

2. 发明授权

US5465380A Data transfer method of transferring data between programs of a same program group in different processors using unique identifiers of the programs 失效
标题翻译：使用程序的唯一标识符在不同处理器中的相同程序组的程序之间传送数据的数据传输方法
公开(公告)号：US5465380A
公开(公告)日：1995-11-07
申请号：US222949
申请日：1994-04-04
申请人： Naoki Hamanaka , Teruo Tanaka , Koichiro Omoda , Shigeo Nagashima
发明人： Naoki Hamanaka , Teruo Tanaka , Koichiro Omoda , Shigeo Nagashima
IPC分类号： G06F9/46 , G06F15/16 , G06F9/00
CPC分类号： G06F9/54 , G06F15/161
摘要： A parallel processor system which includes a plurality of processors each for executing at least one of a plurality of mutually associated programs and a transfer circuit. The transfer circuit is connected to the processors, and is provided for transferring the data outputted from any one of the programs during execution of one program by any one of the processors to other processors to which a receiving program is allotted. The transfer operation is performed in response to a program identification code outputted during execution of the one program by one processor to identify the receiving program.
摘要翻译：一种并行处理器系统，其包括多个处理器，每个处理器用于执行多个相互关联的程序和传送电路中的至少一个。传送电路连接到处理器，并且被提供用于将由任何一个处理器执行一个程序期间的任何一个程序输出的数据传送到分配了接收程序的其他处理器。响应于由一个处理器执行一个程序期间输出的节目识别码来执行传送操作以识别接收节目。

3. 发明授权

US5043873A Method of parallel processing for avoiding competition control problems and data up dating problems common in shared memory systems 失效
标题翻译：并行处理方法，用于避免共享内存系统中常见的竞争控制问题和数据上传问题
公开(公告)号：US5043873A
公开(公告)日：1991-08-27
申请号：US395444
申请日：1989-08-17
申请人： Akira Muramatsu , Kousuke Sakoda , Ikuo Yoshihara , Kazuo Nakao , Makoto Nohmi , Naoki Hamanaka , Shigeo Nagashima , Teruo Tanaka
发明人： Akira Muramatsu , Kousuke Sakoda , Ikuo Yoshihara , Kazuo Nakao , Makoto Nohmi , Naoki Hamanaka , Shigeo Nagashima , Teruo Tanaka
IPC分类号： G06F9/45 , G06F9/50
CPC分类号： G06F9/5016 , G06F8/451 , G06F2209/484
摘要： A plurality of elemental processors each include a local memory for storing data and task programs and an execution section for executing the task programs. A communications section transfers data among the processors. In a method of parallel processing with these elemental processors, a task program is executed in one of the processors. A detection operation is conducted to determine whether the data from the task program is to be copied to the local memories of other processors. The detection is based on predetermined information which is stored in the local memory of the processor which performs the task program and indicates which of the other processors will need the data. The detection also determines which of the other processors that will require access to the data are ready to receive the data. Concurrently and in parallel with the execution of the task program, the data is transmitted to each of the elemental processors that are awaiting the data with only a write instruction and without any communications instruction.

4. 发明授权

US4951193A Parallel computer with distributed shared memories and distributed task activating circuits 失效
标题翻译：具有分布式共享存储器和分布式任务激活电路的并行计算机
公开(公告)号：US4951193A
公开(公告)日：1990-08-21
申请号：US85646
申请日：1987-08-14
申请人： Akira Muramatsu , Kousuke Sakoda , Ikuo Yoshihara , Kazuo Nakao , Makoto Nohmi , Naoki Hamanaka , Shigeo Nagashima , Teruo Tanaka
发明人： Akira Muramatsu , Kousuke Sakoda , Ikuo Yoshihara , Kazuo Nakao , Makoto Nohmi , Naoki Hamanaka , Shigeo Nagashima , Teruo Tanaka
IPC分类号： G06F9/45 , G06F9/50
CPC分类号： G06F9/5016 , G06F8/451 , G06F2209/484
摘要： In accessing a memory, each element processor executes a program constructed so as to designate an address belonging to a predetermined local address area for each element processor. When a memory write instruction is executed by an element processor, it is detected if the memory address designated by the instruction coincides with a predetermined address. If detected, a predetermined address belonging to a local address space of another element processor and assigned to the first-mentioned predetermined address, and the data written in response to the write instruction, are sent to the other element processor to instruct the data to be written therein as a copy data. A next task to be executed is decided independently for each element processor.
摘要翻译：在访问存储器时，每个元件处理器执行构造成为每个元件处理器指定属于预定本地地址区域的地址的程序。当由元件处理器执行存储器写入指令时，检测由指令指定的存储器地址是否与预定地址一致。如果检测到，则属于另一元件处理器的本地地址空间并分配给首先提到的预定地址的预定地址以及响应写指令写入的数据被发送到另一元件处理器以指示数据为在其中写入作为复制数据。对于每个元件处理器独立地确定要执行的下一个任务。

5. 发明授权

US5301322A System for converting job/process identifiers into processor/process identifiers in transferring data between processes in a multiprocessor system 失效
标题翻译：用于将作业/过程标识符转换为处理器/进程标识符的系统，用于在多处理器系统中的进程之间传送数据
公开(公告)号：US5301322A
公开(公告)日：1994-04-05
申请号：US912215
申请日：1992-07-10
申请人： Naoki Hamanaka , Teruo Tanaka , Koichiro Omoda , Shigeo Nagashima
发明人： Naoki Hamanaka , Teruo Tanaka , Koichiro Omoda , Shigeo Nagashima
IPC分类号： G06F9/46 , G06F15/16 , G06F9/00
CPC分类号： G06F9/54 , G06F15/161
摘要： A parallel processor system includes a transfer circuit and a plurality of processors each of which executes at least one of a plurality of mutually associated programs. The transfer circuit transfers data from a sending program allotted to one processor to a receiving program allotted to another processor by identifying the other processor and the receiving program based on a job number and within-job process number outputted by the sending program.
摘要翻译：并行处理器系统包括传送电路和多个处理器，每个处理器执行多个相互关联的程序中的至少一个。传送电路根据发送程序输出的作业号和作业内编号，通过识别其他处理器和接收程序，将数据从分配给一个处理器的发送程序传送到分配给另一个处理器的接收程序。

6. 发明授权

US5010477A Method and apparatus for transferring vector data between parallel processing system with registers & logic for inter-processor data communication independents of processing operations 失效
标题翻译：用于在并行处理系统与用于处理器间数据通信的寄存器和逻辑之间传送矢量数据的方法和装置独立于处理操作
公开(公告)号：US5010477A
公开(公告)日：1991-04-23
申请号：US109293
申请日：1987-10-15
申请人： Koichiro Omoda , Teruo Tanaka , Junji Nakagoshi , Naoki Hamanaka , Shigeo Nagashima
发明人： Koichiro Omoda , Teruo Tanaka , Junji Nakagoshi , Naoki Hamanaka , Shigeo Nagashima
IPC分类号： G06F15/80
CPC分类号： G06F15/8092 , G06F15/8015
摘要： A parallel processor system having a plurality of processor elements includes transfer information generation circuit for generating transfer information by adding to vector data a data identifier for the vector data and a destination processor element number, transmission circuit for sending the transfer information to a data communication path, receive circuit for holding the transfer information sent from the data communication path, and vector register for continuously reading related element data from the receive circuit based on the data identifiers generated by the transfer information generation circuit.
摘要翻译：具有多个处理器单元的并行处理器系统包括：传送信息生成电路，用于通过向矢量数据添加用于矢量数据的数据标识符和目的处理器单元号来生成传送信息，发送电路，用于将传送信息发送到数据通信路径，用于保持从数据通信路径发送的传送信息的接收电路，以及用于基于由传送信息生成电路产生的数据标识符从接收电路连续读取相关元素数据的向量寄存器。

7. 发明授权

US5710932A Parallel computer comprised of processor elements having a local memory and an enhanced data transfer mechanism 失效
标题翻译：由具有本地存储器和增强型数据传输机构的处理器元件组成的并行计算机
公开(公告)号：US5710932A
公开(公告)日：1998-01-20
申请号：US215262
申请日：1994-03-21
申请人： Naoki Hamanaka , Teruo Tanaka
发明人： Naoki Hamanaka , Teruo Tanaka
IPC分类号： G06F15/17 , G06F13/00
CPC分类号： G06F15/17
摘要： A parallel computer includes a plurality of processor elements (1-1 to 1-n) connected by a network (2); each processor element includes a local memory (6) for holding a program and related data, a processor (3) for performing an instruction in said program, a circuit (5) for transferring data to other processor elements, and a circuit (4) for receiving data sent from another processor element; a memory area (92,8) includes of a plurality of reception data areas for temporarily storing data received by said receiving circuit, and memory (92,8) constructed of a plurality of tag areas, provided for each reception data area, for storing a data tag indicating validity of data in the corresponding reception data area; a transmitting circuit (5) for transmitting data with an attached data identifier predetermined by said data; a circuit for writing the data into one of the plurality of reception data areas in response to data received from the network, and writing valid data tag into one of said plurality of reception data areas, the receiving circuit being parallelly-operated with the processor; and, an access circuit (38) for reading both data and tag from one of the reception data areas determined by the data identifier and from the corresponding tag areas, in response to a data identifier designated by the instruction which is produced from said program for requiring data reception, and for repeatedly reading a tag and data from the tag reception data areas until a valid data tag is read therefrom.
摘要翻译：并行计算机包括由网络（2）连接的多个处理器元件（1-1至1-n）; 每个处理器元件包括用于保存程序和相关数据的本地存储器（6），用于执行所述程序中的指令的处理器（3），用于将数据传送到其他处理器元件的电路（5）用于接收从另一处理器元件发送的数据; 存储区域（92,8）包括用于临时存储由所述接收电路接收的数据的多个接收数据区域以及为每个接收数据区域提供的多个标签区域构成的存储器（92,8），用于存储指示对应的接收数据区域中的数据的有效性的数据标签; 发送电路（5），用于利用由所述数据预先确定的附加数据标识符发送数据; 用于响应于从网络接收到的数据将数据写入多个接收数据区之一并将有效数据标签写入所述多个接收数据区之一的电路，所述接收电路与所述处理器并行操作; 以及访问电路（38），用于响应于由所述程序产生的指令指定的数据标识符，用于从由数据标识符确定的接收数据区域中的一个和相应的标签区域读取数据和标签，需要数据接收，并且用于从标签接收数据区重复读取标签和数据，直到从其读取有效的数据标签。

8. 发明授权

US5113390A Data transfer network suitable for use in a parallel computer 失效
标题翻译：数据传输网络适用于并行计算机
公开(公告)号：US5113390A
公开(公告)日：1992-05-12
申请号：US508065
申请日：1990-04-10
申请人： Takehisa Hayashi , Koichiro Omoda , Teruo Tanaka , Naoki Hamanaka , Shigeo Nagashima
发明人： Takehisa Hayashi , Koichiro Omoda , Teruo Tanaka , Naoki Hamanaka , Shigeo Nagashima
IPC分类号： H04L12/935 , H04L12/937
CPC分类号： H04L49/3018 , H04L49/254 , H04L49/3027
摘要： A computer system having a plurality of processors assigned first and second address portions are connected to a plurality of switch circuits. A first group transfer networks are connected to a corresponding first group of the plurality of switch circuits. Each of the transfer networks concurrently transfer data among the switch circuits. The switch circuits are provided to processors of a first kind arranged in a plurality of processor groups. The processor groups of the first kind include processors with different values for first address portions and the same value for second address portions. Additional transfer networks, processors and switches functioning in a similar manner are provided to expand the above system. In another embodiment of the present invention a data transfer network is provided having a plurality of processors for data transfer. The network includes a plurality of multistage switches each belonging to one of plural stages and connected to the switches of a preceding stage and to switches of the succeeding stage. Each of the switches are arranged to receive packets from a preceding switch. A packet includes a target process address and data to be transferred. A path select device is connected to receive packets and is also connected to plural switches belonging to a next stage for the transfer of the received partial addresses and partial data. A control device is connected to receive the partial addresses and partial data and is responsive to a predetermined bit within the received partial addresses. The control means is responsive to the arrival of the first partial address of the packet.

9. 发明授权

US5088034A Compiling method for determining programs to be executed parallelly by respective processors in a parallel computer which transfer data with a data identifier to other processors 失效
标题翻译：用于确定由并行计算机中的各个处理器并行地执行程序的编译方法，该并行计算机将具有数据标识符的数据传送到其他处理器
公开(公告)号：US5088034A
公开(公告)日：1992-02-11
申请号：US301648
申请日：1989-01-25
申请人： Sigeo Ihara , Teruo Tanaka , Kyoko Iwasawa , Naoki Hamanaka
发明人： Sigeo Ihara , Teruo Tanaka , Kyoko Iwasawa , Naoki Hamanaka
IPC分类号： G06F15/16 , G06F9/44 , G06F9/45
CPC分类号： G06F8/45
摘要： A compiler for generating from a serially processed type source program described in a high level language the object codes to be executed in parallel by a parallel processor system which is composed of a plurality of processors marked with respective identification numbers and in which inter-processor data transfer system for identifying data for transfer by data identifiers is adopted. The serially executed source program is first translated to programs to be executed in parallel. The inter-processor data transfer processing is extracted from the flow of processings involved in executing the programs for parallel execution resulting from the above-mentioned translation, and all the interprocessor data transfer processings are attached with data identifiers such that no overlap takes place.
摘要翻译：一种编译器，用于从由高级语言描述的串行处理型源程序生成由并行处理器系统并行执行的目标代码，该并行处理器系统由标有相应标识号的多个处理器组成，并且其中处理器间数据采用用于识别用于由数据标识符传送的数据的传送系统。串行执行的源程序首先被翻译成要并行执行的程序。从执行由上述翻译产生的并行执行程序所涉及的处理流程中提取处理器间数据传送处理，并且所有处理器间数据传送处理都附加有不发生重叠的数据标识符。

10. 发明授权

US4985827A Computer for synchronized read and write of vector data 失效
标题翻译：用于同步读写矢量数据的计算机
公开(公告)号：US4985827A
公开(公告)日：1991-01-15
申请号：US226376
申请日：1988-07-29
申请人： Naoki Hamanaka , Teruo Tanaka , Koichiro Omoda , Shigeo Nagashima , Junji Nakagoshi , Kazuo Ojima
发明人： Naoki Hamanaka , Teruo Tanaka , Koichiro Omoda , Shigeo Nagashima , Junji Nakagoshi , Kazuo Ojima
IPC分类号： G06F17/16 , G06F15/78 , G06F15/80
CPC分类号： G06F15/8092 , G06F15/8084
摘要： A computer comprising a circuit for writing a group of ordered data elements onto the main storage; a circuit for reading said group of data from the main storage; and a circuit which is connected to the writing circuit and to the reading circuit, and which ensures the sequence of main storage references between said writing circuit and said reading circuit such that said reading circuit will not read the data elements that have not yet been written by said writing circuit among said group of data elements.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式