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11. 发明授权

US4782441A Vector processor capable of parallely executing instructions and reserving execution status order for restarting interrupted executions 失效
标题翻译：能够平行执行指令并保留执行状态顺序的矢量处理器重新启动中断的执行
公开(公告)号：US4782441A
公开(公告)日：1988-11-01
申请号：US872396
申请日：1986-06-10
申请人： Yasuhiro Inagami , Shigeo Nagashima , Koichiro Omoda , Takayuki Nakagawa , Teruo Tanaka
发明人： Yasuhiro Inagami , Shigeo Nagashima , Koichiro Omoda , Takayuki Nakagawa , Teruo Tanaka
IPC分类号： G06F9/46 , G06F9/38 , G06F9/48 , G06F15/78 , G06F17/16 , G06F9/28 , G06F7/00
CPC分类号： G06F15/8053
摘要： In a processor such as a vector processor in which a plurality of data are processed by one instruction and a plurality of instructions are parallely processed, apparatus is provided for storing, during an interruption of the program currently being executed, the instructions being executed in the conceptual order of appearance in the program of the instruction being executed, and the sequential count of the sets of data processed. The stored information is used to restart the execution of the interrupted program at the appropriate point.
摘要翻译：在其中通过一个指令处理多个数据并且多个指令并行处理的诸如矢量处理器的处理器中，提供装置，用于在当前执行的程序的中断期间存储在正在执行的指令的程序中出现的概念顺序，以及处理的数据组的顺序计数。存储的信息用于在适当的点重新启动中断的程序的执行。

12. 发明授权

US5754876A Data processor system for preloading/poststoring data arrays processed by plural processors in a sharing manner 失效
标题翻译：数据处理器系统，用于以共享方式预处理/后置由多个处理器处理的数据阵列
公开(公告)号：US5754876A
公开(公告)日：1998-05-19
申请号：US576131
申请日：1995-12-21
申请人： Yoshiko Tamaki , Teruo Tanaka , Tadayuki Sakakibaraa
发明人： Yoshiko Tamaki , Teruo Tanaka , Tadayuki Sakakibaraa
IPC分类号： G06F15/167 , G06F9/30 , G06F9/312 , G06F9/38 , G06F12/02 , G06F12/06 , G06F15/80 , G06F13/38
CPC分类号： G06F9/30043 , G06F15/8092 , G06F9/30101 , G06F9/3455 , G06F9/383
摘要： Preload register groups are respectively provided for the plurality of scalar processors which execute iterative processing in distributed manner. Each group consists of preload registers corresponding to a plurality of data arrays that appear in the iterative processing. According to address information about the plurality of arrays to be preloaded specified by any of the processors, a preload control unit reads partial data groups of one of the arrays to be first processed by all of the processors from the main storage in parallel. Then, the same operation is performed on another array. Subsequently, in the above-mentioned manner, remaining elements of the arrays are read from one array to another. A partial element group thus read sequentially is stored in the plurality of preload register groups in distributed manner. According to a load request issued from each processor, the array elements preloaded in the preload register groups corresponding to that processor are read in the order the array elements were preloaded.
摘要翻译：分别为分散执行迭代处理的多个标量处理器提供预加载寄存器组。每个组由对应于迭代处理中出现的多个数据阵列的预加载寄存器组成。根据关于由任何处理器指定的预先加载的多个阵列的地址信息，预加载控制单元并行地从主存储器读取所有处理器首先处理的阵列之一的部分数据组。然后，对另一个阵列执行相同的操作。随后，以上述方式，阵列的剩余元件从一个阵列读取到另一个阵列。这样按顺序读取的部分元素组以分布的方式存储在多个预加载寄存器组中。根据从每个处理器发出的加载请求，预先加载到与该处理器对应的预加载寄存器组中的阵列元素按照阵列元素被预加载的顺序被读取。

13. 发明授权

US06298355B1 Computer system 失效
标题翻译：电脑系统
公开(公告)号：US06298355B1
公开(公告)日：2001-10-02
申请号：US09269023
申请日：1999-03-18
申请人： Teruo Tanaka , Tadayuki Sakakibara , Hiromitsu Maeda
发明人： Teruo Tanaka , Tadayuki Sakakibara , Hiromitsu Maeda
IPC分类号： G06F1700
CPC分类号： G06F13/1668
摘要： A storage control unit of a computer system in which main storage is shared between one through a plurality of processors, is provided with transfer control means for holding therein address information in a first area of the main storage, in which desired data specified by an arbitrary processor is stored, address information in a second area of the main storage device, to which the desired data is to be transferred, and information about the length of the desired data, and transfer means for reading the data stored in the first area and storing the data in the second area under the control of the transfer control means. Owing to these configurations, the storage control unit is capable of executing a copy of data from the first area to the second area separately from the processors according to instructions from each processor. Thus, the load on each processor can be reduced. Since a processor bus may be unused in data copying when the plurality of processors are connected to the processor bus, the load on the processor bus can be greatly reduced.
摘要翻译：在一个至多个处理器之间共享主存储器的计算机系统的存储控制单元设置有传送控制装置，用于在主存储器的第一区域中保存地址信息，其中由任意的处理器被存储在主存储装置的第二区域中，要传送期望数据的地址信息以及关于期望数据长度的信息，以及用于读取存储在第一区域中的数据并存储在传输控制装置的控制下的第二区域中的数据。由于这些配置，存储控制单元能够根据来自每个处理器的指令从处理器执行从第一区域到第二区域的数据副本。因此，可以减少每个处理器上的负载。由于当多个处理器连接到处理器总线时，在数据复制中可能未使用处理器总线，因此可以大大减少处理器总线上的负载。

14. 发明授权

US5822605A Parallel processor system with a broadcast message serializing circuit provided within a network 失效
标题翻译：具有在网络内提供的广播消息序列化电路的并行处理器系统
公开(公告)号：US5822605A
公开(公告)日：1998-10-13
申请号：US408561
申请日：1995-03-22
申请人： Tatsuo Higuchi , Tadaaki Isobe , Junji Nakagoshi , Shigeo Takeuchi , Tatsuru Toba , Yoshiko Yasuda , Teruo Tanaka , Takayuki Nakagawa , Yuji Saeki
发明人： Tatsuo Higuchi , Tadaaki Isobe , Junji Nakagoshi , Shigeo Takeuchi , Tatsuru Toba , Yoshiko Yasuda , Teruo Tanaka , Takayuki Nakagawa , Yuji Saeki
IPC分类号： G06F15/173 , H04L12/56 , G06F13/00 , H04L12/50
CPC分类号： H04L45/06 , G06F15/17381
摘要： In a parallel processor system comprising a plurality of processor elements constituting a network, a source processor element wishing to broadcast data to a plurality of destination processor elements sends a broadcast request message containing the target data to a broadcast exchanger. The broadcast exchanger converts the received message into a broadcast message and sends it over the network to the destinations. A plurality of broadcast request messages, if transmitted parallelly to the broadcast exchanger, are serialized thereby so that only one broadcast message will be transmitted at a time over the network. This prevents deadlock from occurring between different broadcast messages. The routes for transmitting broadcast request messages and those for transmitting broadcast messages are arranged so as not to overlap with one another. This suppresses deadlock between any broadcast request message and broadcast message. The broadcast exchanger is replaced alternatively with one of the partial networks. These schemes all apply where long messages are transmitted through worm-hole routing.
摘要翻译：在包括构成网络的多个处理器元件的并行处理器系统中，希望向多个目的地处理器元件广播数据的源处理器元件向广播交换机发送包含目标数据的广播请求消息。广播交换机将接收的消息转换成广播消息，并通过网络将其发送到目的地。如果与广播交换机并行发送的多个广播请求消息被序列化，从而在网络上一次只能发送一个广播消息。这可以防止不同广播消息之间发生死锁。用于发送广播请求消息的路由和用于发送广播消息的路由被布置为不彼此重叠。这抑制了任何广播请求消息和广播消息之间的死锁。广播交换机被替换为部分网络之一。这些方案都适用于通过蠕虫孔路由传输长消息的情况。

15. 发明授权

US5867679A Parallel processor system with asynchronous data transmission by a data producing processor to a data using processor employing controlled execution of a program by the data using processor for processing the data 失效
标题翻译：并行处理器系统，其通过数据产生处理器将异步数据传输到使用处理器的数据的数据采用由数据使用处理器处理数据的数据的受控执行程序
公开(公告)号：US5867679A
公开(公告)日：1999-02-02
申请号：US647773
申请日：1991-01-30
申请人： Teruo Tanaka , Naoki Hamanaka , Koichiro Omoda , Shigeo Nagashima , Akira Muramatsu , Ikuo Yoshihara , Kazuo Nakao , Junji Nakagoshi , Kazuo Ojima
发明人： Teruo Tanaka , Naoki Hamanaka , Koichiro Omoda , Shigeo Nagashima , Akira Muramatsu , Ikuo Yoshihara , Kazuo Nakao , Junji Nakagoshi , Kazuo Ojima
IPC分类号： G06F9/44 , G06F15/17 , G06F15/80 , G06F15/82
CPC分类号： G06F15/8015 , G06F9/4494 , G06F15/17
摘要： A parallel computer system includes a plurality of processors, each of which is placed in data communication with an interconnecting network. Pairs of a data signal and a data identification code, predetermined for the data signal, are received by each processor and stored in a memory. Structure is provided for reading a data signal belonging to one of the pairs having a data identification code designated by a data readout instruction.
摘要翻译：并行计算机系统包括多个处理器，每个处理器与互连网络进行数据通信。数据信号对和数据信号预定的数据识别码由每个处理器接收并存储在存储器中。提供结构用于读取属于其中一对的数据信号，该数据信号具有由数据读出指令指定的数据识别码。

16. 发明授权

US5475028A 2-aminoethanesulfonic acid zinc complex 失效
标题翻译： 2-氨基乙磺酸锌络合物
公开(公告)号：US5475028A
公开(公告)日：1995-12-12
申请号：US256446
申请日：1994-07-13
申请人： Hajime Fujimura , Takahiro Yabuuchi , Teruo Tanaka , Yoichi Nagamura
发明人： Hajime Fujimura , Takahiro Yabuuchi , Teruo Tanaka , Yoichi Nagamura
IPC分类号： A61K31/185 , A61K31/315 , A61K33/30 , A61P1/04 , A61P1/16 , C07F3/00 , C07F3/06
CPC分类号： A61K31/315 , C07F3/003 , C07F3/06 , Y10S514/894 , Y10S514/925
摘要： The present invention relates to a 2-aminoethanesulfonic acid zinc complex represented by the following formula: ##STR1## (wherein M is an alkali metal atom), to a process for producing the said complex from 2-aminoethanesulfonic acid and to use of the said complex as an anti-hepatitis agent, liver function improving agent and anti-ulcer agent. The said complex exhibits not only improved physiological activities such as anti-hepatitis activity, suppressory activity against liver-function disorder and anti-ulcer activity but also protective and restorative activity for the digestive tract.
摘要翻译： PCT No.PCT / JP93 / 00057 Sec。 371日期：1994年7月13日 102（e）日期1994年7月13日PCT提交1993年1月13日PCT公布。公开号WO93 / 14095 日期：1993年7月22日。本发明涉及由下列通式表示的2-氨基乙磺酸锌络合物：其中M为碱金属原子，其为2-氨基乙磺酸酸和使用所述复合物作为抗肝炎药，肝功能改善剂和抗溃疡剂。所述复合物不仅具有改善的生理活性，如抗肝炎活性，对肝功能障碍的抑制活性和抗溃疡活性，还包括消化道的保护和恢复活性。

17. 发明授权

US5297255A Parallel computer comprised of processor elements having a local memory and an enhanced data transfer mechanism 失效
标题翻译：由具有本地存储器和增强型数据传输机构的处理器元件组成的并行计算机
公开(公告)号：US5297255A
公开(公告)日：1994-03-22
申请号：US303626
申请日：1989-01-27
申请人： Naoko Hamanaka , Teruo Tanaka
发明人： Naoko Hamanaka , Teruo Tanaka
IPC分类号： G06F15/163 , G06F13/00
CPC分类号： G06F15/163
摘要： In a parallel computer, there are provided a plurality of processor elements 1-1 to 1-n) connected to each other by a network (2); each of said processor elements including a local memory (6) for holding a program and data related thereto, a processor (3) for performing an instruction in said program, a circuit (5) for transferring the data to the other processor elements, and a circuit (4) for receiving the data sent from the other processor element; a memory area (92:8) constructed of a plurality of reception data areas for temporarily storing data received by said receiving circuit, and a memory (92,8) constructed of a plurality of tag areas, provided for each of the reception data areas, for storing a valid data tag or an invalid data tag indicating that the data in the corresponding reception data area is valid or invalid; a transmitting circuit (5) for transmitting the data to be transmitted with attaching a data identifier predetermined by said data; a receiving circuit for writing the data into one of said plurality of reception data areas in response to the data received from said network, and writing the valid data tag into one of said plurality of reception data areas, said receiving circuit being parallel-operated with said processor; and, an access circuit (38) for reading both the data and tag from one of the reception data areas determined by said data identifier and from the corresponding tag areas in response to the data identifier designated by the instruction which is produced from said program for requiring the data reception, and for repeatedly reading the tag and data from the tag area and reception data area until the valid data tag is read out from the tag area in case that the read tag corresponds to the invalid data tag.
摘要翻译：在并行计算机中，提供了由网络（2）彼此连接的多个处理器元件1-1至1-n）。每个所述处理器元件包括用于保存程序的本地存储器（6）和与其相关的数据，用于在所述程序中执行指令的处理器（3），用于将数据传送到其他处理器元件的电路（5），以及用于接收从另一个处理器元件发送的数据的电路（4）; 由用于临时存储由所述接收电路接收的数据的多个接收数据区域构成的存储区域（92：8），以及为每个接收数据区域提供的多个标签区域构成的存储器（92,8）用于存储有效数据标签或指示相应接收数据区域中的数据有效或无效的无效数据标签; 发送电路（5），用于通过附加由所述数据预先确定的数据标识符发送要发送的数据; 接收电路，用于响应于从所述网络接收的数据将数据写入所述多个接收数据区域之一，并将有效数据标签写入所述多个接收数据区域之一，所述接收电路与说处理器以及访问电路（38），用于响应于由所述程序产生的指令指定的数据标识符，从由所述数据标识符确定的接收数据区域中的一个和相应的标签区域读取数据和标签，需要数据接收，并且用于从标签区域和接收数据区域反复读取标签和数据，直到在读取标签对应于无效数据标签的情况下，从标签区域读出有效数据标签。

18. 发明授权

US5198041A Shape memory stainless steel excellent in stress corrosion cracking resistance and method thereof 失效
标题翻译：形状记忆不锈钢在应力腐蚀开裂电阻及其应用中的优势
公开(公告)号：US5198041A
公开(公告)日：1993-03-30
申请号：US835433
申请日：1992-02-25
申请人： Toshihiko Takemoto , Masayuki Kinugasa , Teruo Tanaka , Takashi Igawa
发明人： Toshihiko Takemoto , Masayuki Kinugasa , Teruo Tanaka , Takashi Igawa
IPC分类号： C21D8/00 , C22C38/00 , C22C38/30 , C22C38/58
CPC分类号： C21D8/005 , C22C38/58
摘要： A shape memory stainless steel containing more than 10% by weight of Cr excellent in resistance to stress corrosion cracking and having sufficient function as a shape memory alloy, which comprises, by weight, up to 0.10% of C, 3.0 to 6.0% of Si, 6.0 to 25.0% of Mn, up to 7.0% of Ni, more than 10.0% and not more than 17.0% of Cr, 0.02 to 0.3% of N, 2.0 to 10.0% of Co and more than 0.2% and not more than 3.5% of Cu, and at least one selected from up to 2.0% of Mo, 0.05 to 0.8% of Nb, 0.05 to 0.8% of V, 0.05 to 0.8% of Zr, 0.05 or 0.8% of Ti, the balance being Fe and unavoidable impurities, the alloying components being adjusted so that a D value is not less than-26.0, wherein the D value is defined by the following equation:D=Ni+0.30.times.Mn+56.8.times.C+19.0.times.N+0.73.times.Co+Cu -1.85.times.[Cr+1.6.times.Si+Mo+1.5.times.(Nb+V+Zr+Ti)].
摘要翻译： PCT No.PCT / JP90 / 01001 Sec。 371日期：1992年2月25日 102（e）日期1992年2月25日PCT提交1990年8月4日PCT公布。出版物WO91 / 02827 1991年3月7日。一种形状记忆不锈钢，其含有超过10重量％的耐应力腐蚀开裂性优异的Cr，并具有作为形状记忆合金的足够功能，其含有至多0.10重量％的C ，3.0〜6.0％的Si，6.0〜25.0％的Mn，Ni：7.0％以下，Cr：10.0％以上，17.0％以下，N：0.02〜0.3％，Co：2.0〜10.0％超过0.2％且不超过3.5％的Cu，以及选自Mo最多为2.0％，Nb为0.05〜0.8％，V为0.05〜0.8％，Zr为0.05〜0.8％，0.05〜0.8％的Ti，余量为Fe和不可避免的杂质，调整合金成分使得D值不小于-26.0，其中D值由下式定义：D = Ni + 0.30×Mn + 56.8×C + 19.0 xN + 0.73×Co + Cu -1.85×[Cr + 1.6×Si + Mo + 1.5×（Nb + V + Zr + Ti）]。

19. 发明授权

US5104867A 2-(heterocyclylthio)carbapenem derivatives, their preparation and their use as antibiotics 失效
标题翻译： 2-（间苯二酚）碳水化合物衍生物，其制备及其作为抗生素的用途
公开(公告)号：US5104867A
公开(公告)日：1992-04-14
申请号：US540878
申请日：1990-06-20
申请人： Isao Kawamoto , Teruo Tanaka , Rokuro Endo , Masayuki Iwata , Masao Miyauchi
发明人： Isao Kawamoto , Teruo Tanaka , Rokuro Endo , Masayuki Iwata , Masao Miyauchi
IPC分类号： C07D477/20
CPC分类号： C07D477/20
摘要： Compounds of formula (I): ##STR1## in which R.sup.a is a group of formula (II): ##STR2## or a group of formula (III): ##STR3## (where one of R' is a bond to the remainder of the compound, one more of R' is R.sup.2 and the others of R' are all hydrogen), R.sup.1 is hydrogen or methyl, R.sup.2 is hydrogen, optionally substiuted alkyl, halogen, hydroxy, alkoxy, amino, alkanoylamino, alkanoyloxy, alkanoyl, carboxy, alkoxycarbonyl, cyano, --S(O).sub.j R.sup.9 (where j is 0, 1 or 2 and R.sup.9 is alkyl), or --CONR.sup.6 R.sup.7 (which is optionally substituted carbamoyl or heterocyclyl-carbonyl), R.sup.2a is hydrogen, alkyl or alkanoyl, --NR.sup.3 R.sup.4 is optionally substituted amino or heterocyclic, and --COOR.sup.5 is carboxy, --COO.sup.-, --COOM.sub.x (where M is a cation and x is the reciprocal of the valence of the cation M) or protected carboxy and, where --COOR.sup.5 is carboxy, --COOM.sub.x or protected carboxy, the compound of formula (I) also contains an anion; l, m and n are independently 0, 1, 2 or 3, provided that (m+n) is an integer from 2 to 6; p is 0, 1 or 2; Y is a single bond, oxygen, sulfur or R.sup.8 N

20. 发明授权

US5086498A Parallel computer with asynchronous communication facility 失效
标题翻译：具有异步通信设备的并行计算机
公开(公告)号：US5086498A
公开(公告)日：1992-02-04
申请号：US145614
申请日：1988-01-10
申请人： Teruo Tanaka , Naoki Hamanaka , Junji Nakagoshi , Koichiro Omoda , Shigeo Nagashima
发明人： Teruo Tanaka , Naoki Hamanaka , Junji Nakagoshi , Koichiro Omoda , Shigeo Nagashima
IPC分类号： G06F15/17 , G06F15/173 , G06F15/80 , G06F17/16
CPC分类号： G06F15/8092 , G06F15/17 , G06F15/173
摘要： In a multiprocessor digital computer system ID data, coupled with data for which inter-processor communication is desired, is communicated from one processor and held temporarily with data in a receiver buffer (associative memory) in a receiving processor. This ID is divided into main ID data MK and sub ID data SK. Main ID data MK is used for searching data from a receive buffer. The sub ID data SK are used as an ID of the data in the receive processor.
摘要翻译：在多处理器数字计算机系统ID数据中，与期望的处理器间通信的数据相耦合，从一个处理器传送并暂时保存在接收处理器中的接收缓冲器（关联存储器）中的数据。该ID被划分为主ID数据MK和子ID数据SK。主ID数据MK用于从接收缓冲器搜索数据。子ID数据SK用作接收处理器中的数据的ID。

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