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11. 发明授权

US08183879B2 Measuring arrangement, semiconductor arrangement and method for operating a semiconductor component as a reference source 失效
标题翻译：用于操作半导体部件作为参考源的测量布置，半导体布置和方法
公开(公告)号：US08183879B2
公开(公告)日：2012-05-22
申请号：US12399581
申请日：2009-03-06
申请人： Ralf Brederlow , Roland Thewes
发明人： Ralf Brederlow , Roland Thewes
IPC分类号： G01R31/02 , G01R31/26
CPC分类号： H01L29/78 , G01R35/007
摘要： The invention relates to a measuring arrangement, a semiconductor arrangement and a method for operating a reference source, wherein at least one semiconductor component and a voltage source are connected to a measuring unit and the measuring unit provides a measured value that is proportional to the number of defects.
摘要翻译：本发明涉及一种用于操作参考源的测量装置，半导体装置和方法，其中至少一个半导体部件和电压源连接到测量单元，并且测量单元提供与数字成比例的测量值的缺陷。

12. 发明授权

US07820505B2 Integrated circuit arrangement with capacitor and fabrication method 有权
标题翻译：具有电容器的集成电路布置及其制造方法
公开(公告)号：US07820505B2
公开(公告)日：2010-10-26
申请号：US11862640
申请日：2007-09-27
申请人： Ralf Brederlow , Jessica Hartwich , Christian Pacha , Wolfgang Rösner , Thomas Schulz
发明人： Ralf Brederlow , Jessica Hartwich , Christian Pacha , Wolfgang Rösner , Thomas Schulz
IPC分类号： H01L21/8242
CPC分类号： H01L29/785 , H01L21/845 , H01L27/0629 , H01L27/108 , H01L27/10805 , H01L27/10823 , H01L27/10826 , H01L27/1085 , H01L27/10873 , H01L27/10876 , H01L27/10879 , H01L27/1211 , H01L27/13 , H01L28/60 , H01L29/66795
摘要： An integrated circuit arrangement contains an insulating region, which is part of a planar insulating layer, and a capacitor which contains: near and far electrode regions near and remote from the insulating region and a dielectric region. The capacitor and an active component are on the same side of the insulating layer, and the near electrode region and an active region of the component are planar and parallel to the insulating layer. The near electrode region is monocrystalline and contains multiple webs. Alternately, a FET is present in which: a channel region is the active region, the FET contains a web with opposing control electrodes connected by a connecting region that is isolated from the channel region by a thick insulating region. The thick insulating region is thicker than control electrode insulation regions. The control electrodes contain the same material as the far electrode region.
摘要翻译：集成电路装置包括作为平面绝缘层的一部分的绝缘区域和包含：靠近和远离绝缘区域的近远电极区域和电介质区域的电容器。电容器和有源部件位于绝缘层的同一侧，并且组件的近电极区域和有源区域是平面的并且平行于绝缘层。近电极区域是单晶体并且包含多个网状物。或者，存在FET，其中沟道区域是有源区域，FET包含具有相对的控制电极的幅材，该栅极通过由沟道区域与厚绝缘区域隔离的连接区域连接。厚的绝缘区域比控制电极绝缘区域厚。控制电极含有与远电极区域相同的材料。

13. 发明授权

US07733157B2 Noise-reducing transistor arrangement 有权
标题翻译：降噪晶体管布置
公开(公告)号：US07733157B2
公开(公告)日：2010-06-08
申请号：US10583538
申请日：2004-12-03
申请人： Ralf Brederlow , Jeongwook Koh , Christian Pacha , Roland Thewes
发明人： Ralf Brederlow , Jeongwook Koh , Christian Pacha , Roland Thewes
IPC分类号： H03K17/687
CPC分类号： H03K17/162 , H01L2924/0002 , H01L2924/00
摘要： Noise-reducing transistor arrangement having first and second field effect transistors (FETs) having source terminals coupled together, drain terminals coupled together, and control terminals for application of a first or second signal. A clock generator unit is configured to provide the first and second signals alternately to the FETs with an alternating frequency which is at least as great as the cut-off frequency of the noise characteristic of the FETs, or with a reciprocal alternating frequency which is less than a mean lifetime of an occupation state of a defect in the boundary region between channel region and gate insulating layer of the FETs. The first signal is applied to the control terminal of the first FET and, simultaneously, the second signal to the control terminal of the second FET. The second signal is applied to the control terminal of the first FET and, simultaneously, the first signal to the control terminal of the second FET.
摘要翻译：具有第一和第二场效应晶体管（FET）的降噪晶体管装置，其具有耦合在一起的源极端子，耦合在一起的漏极端子和用于施加第一或第二信号的控制端子。时钟发生器单元被配置为以至少与FET的噪声特性的截止频率一样大的交变频率或者具有较小的互逆交变频率来向FET施加交替的第一和第二信号比FET的沟道区域和栅极绝缘层之间的边界区域的缺陷的占用状态的平均寿命长。第一信号被施加到第一FET的控制端子，并且同时将第二信号施加到第二FET的控制端子。第二信号被施加到第一FET的控制端，同时将第一信号施加到第二FET的控制端。

14. 发明授权

US07733156B2 Transistor arrangement, integrated circuit and method for operating field effect transistors 有权
标题翻译：晶体管布置，集成电路和操作场效应晶体管的方法
公开(公告)号：US07733156B2
公开(公告)日：2010-06-08
申请号：US10570924
申请日：2004-09-01
申请人： Ralf Brederlow , Jeongwook Koh , Roland Thewes
发明人： Ralf Brederlow , Jeongwook Koh , Roland Thewes
IPC分类号： H03K17/16 , H03K17/687
CPC分类号： H03F3/211 , H01L2924/0002 , H03F1/26 , H03F3/72 , H03F2203/21178 , H03F2203/7215 , H01L2924/00
摘要： The transistor arrangement contains a first and a second field effect transistor comprising a first and a second source drain connection and a control connection for applying a first or a second signal. The two field effect transistors are of the same conductive type. The transistor arrangement is configured in such a manner that the first signal can be applied in an alternating manner to the control connection of the first field effect transistor and the second signal can be applied in a simultaneous manner to the control connection of the second field effect transistor, and/or the second signal can be applied to the control connection of the first field effect transistor and the first signal can be applied simultaneously to the control connection of the second field effect transistor.
摘要翻译：晶体管装置包括第一和第二场效应晶体管，其包括第一和第二源极漏极连接以及用于施加第一或第二信号的控制连接。两个场效应晶体管具有相同的导电类型。晶体管布置被配置为使得第一信号可以以交替方式施加到第一场效应晶体管的控制连接，并且第二信号可以以与第二场效应的控制连接同时的方式施加晶体管和/或第二信号可以被施加到第一场效应晶体管的控制连接，并且第一信号可以同时施加到第二场效应晶体管的控制连接。

15. 发明申请

US20090066345A1 SENSOR HAVING ORGANIC FIELD EFFECT TRANSISTORS 审中-公开
标题翻译：传感器有机场效应晶体管
公开(公告)号：US20090066345A1
公开(公告)日：2009-03-12
申请号：US10599470
申请日：2005-03-30
申请人： Hagen Klauk , Marcus Halik , Ute Zschieschang , Guenter Schmid , Grzegorz Darlinski , Rainer Waser , Ralf Brederlow
发明人： Hagen Klauk , Marcus Halik , Ute Zschieschang , Guenter Schmid , Grzegorz Darlinski , Rainer Waser , Ralf Brederlow
IPC分类号： G01R27/26 , H01L51/05
CPC分类号： G06K9/00053
摘要： A force sensor based on an organic field effect transistor applied on a substrate is disclosed. In one embodiment, a mechanical force acting on the transistor causes a change in its source-drain voltage or its source-drain current which corresponds to said force and which can in each case be detected as measurement quantity for the acting force, a diaphragm-based pressure sensor that uses a force sensor of this type, a one- or two-dimensional position sensor that uses a multiplicity of force sensors of this type, and a fingerprint sensor that uses a multiplicity of such force sensors.
摘要翻译：公开了一种基于施加在衬底上的有机场效应晶体管的力传感器。在一个实施例中，作用在晶体管上的机械力引起其源极 - 漏极电压或其源极 - 漏极电流的变化，其对应于所述力，并且在每种情况下都可以被检测为作用力的测量量，使用这种力传感器的基于压力的传感器，使用这种类型的多个力传感器的一维或二维位置传感器，以及使用多个这样的力传感器的指纹传感器。

16. 发明申请

US20080038888A1 INTEGRATED CIRCUIT ARRANGEMENT WITH CAPACITOR AND FABRICATION METHOD 有权
标题翻译：集成电路与电容器和制造方法的布置
公开(公告)号：US20080038888A1
公开(公告)日：2008-02-14
申请号：US11862640
申请日：2007-09-27
申请人： Ralf Brederlow , Jessica Hartwich , Christian Pacha , Wolfgang Rosner , Thomas Schulz
发明人： Ralf Brederlow , Jessica Hartwich , Christian Pacha , Wolfgang Rosner , Thomas Schulz
IPC分类号： H01L21/8242
CPC分类号： H01L29/785 , H01L21/845 , H01L27/0629 , H01L27/108 , H01L27/10805 , H01L27/10823 , H01L27/10826 , H01L27/1085 , H01L27/10873 , H01L27/10876 , H01L27/10879 , H01L27/1211 , H01L27/13 , H01L28/60 , H01L29/66795
摘要： An integrated circuit arrangement contains an insulating region, which is part of a planar insulating layer, and a capacitor which contains: near and far electrode regions near and remote from the insulating region and a dielectric region. The capacitor and an active component are on the same side of the insulating layer, and the near electrode region and an active region of the component are planar and parallel to the insulating layer. The near electrode region is monocrystalline and contains multiple webs. Alternately, a FET is present in which: a channel region is the active region, the FET contains a web with opposing control electrodes connected by a connecting region that is isolated from the channel region by a thick insulating region. The thick insulating region is thicker than control electrode insulation regions. The control electrodes contain the same material as the far electrode region.
摘要翻译：集成电路装置包括作为平面绝缘层的一部分的绝缘区域和包含：靠近和远离绝缘区域的近远电极区域和电介质区域的电容器。电容器和有源部件位于绝缘层的同一侧，并且组件的近电极区域和有源区域是平面的并且平行于绝缘层。近电极区域是单晶体并且包含多个网状物。或者，存在FET，其中沟道区域是有源区域，FET包含具有相对的控制电极的幅材，该栅极通过由沟道区域与厚绝缘区域隔离的连接区域连接。厚的绝缘区域比控制电极绝缘区域厚。控制电极含有与远电极区域相同的材料。

17. 发明授权

US07173302B2 Integrated circuit arrangement having capacitors and having planar transistors and fabrication method 有权
标题翻译：具有电容器并具有平面晶体管和制造方法的集成电路装置
公开(公告)号：US07173302B2
公开(公告)日：2007-02-06
申请号：US10531493
申请日：2003-10-10
申请人： Ralf Brederlow , Jessica Hartwich , Christian Pacha , Wolfgang Rösner , Thomas Schulz
发明人： Ralf Brederlow , Jessica Hartwich , Christian Pacha , Wolfgang Rösner , Thomas Schulz
IPC分类号： H01L27/108 , H01L21/8242
CPC分类号： H01L27/1085 , H01L21/84 , H01L27/10805 , H01L27/1203
摘要： An integrated circuit arrangement and method of fabricating the integrated circuit arrangement is described. The integrated circuit arrangement contains an insulating region and a sequence of regions which forms a capacitor. The sequence contains a near electrode region near the insulating region, a dielectric region, and a remote electrode region remote from the insulating region. The insulating region is part of an insulating layer arranged in a plane. The capacitor and an active component are arranged on the same side of the insulating layer and form a memory cell. The near electrode region and an active region of the component are arranged in a plane which lies parallel to the plane in which the insulating layer is arranged. A processor is also contained in the integrated circuit arrangement.
摘要翻译：描述了一种集成电路装置及其制造方法。集成电路装置包含形成电容器的绝缘区域和一系列区域。该序列包含靠近绝缘区域的近电极区域，电介质区域和远离绝缘区域的远程电极区域。绝缘区域是布置在平面中的绝缘层的一部分。电容器和有源部件布置在绝缘层的同一侧上并形成存储单元。组件的近电极区域和有源区域被布置在与布置绝缘层的平面平行的平面中。处理器也包含在集成电路装置中。

18. 发明申请

US20050125471A1 Random number generator and method for generating a random number 有权
标题翻译：随机数发生器和产生随机数的方法
公开(公告)号：US20050125471A1
公开(公告)日：2005-06-09
申请号：US10948627
申请日：2004-09-23
申请人： Thomas Sturm , Guido Stromberg , Ralf Brederlow , Werner Weber
发明人： Thomas Sturm , Guido Stromberg , Ralf Brederlow , Werner Weber
IPC分类号： G06F1/02 , G06F7/58
CPC分类号： G06F7/588
摘要： Random number generator having a transistor that generates an analog random telegraph signal (RTS) having a first or second signal state, a RTS detection unit for detecting the RTS generated by the transistor, a RTS sampling unit that supersamples the RTS detected by the RTS detection unit and thus generates a digitized RTS, a signal state duration detection unit that determines, from the digitized RTS, a first time variable representing the time duration of at least one first signal state of the generated RTS and a second time variable representing the time duration of at least one second signal state of the generated RTS, and a random number conversion unit, which is coupled to the signal state duration detection unit, and that generates a random number from the first time variable and the second time variable.
摘要翻译：具有产生具有第一或第二信号状态的模拟随机电报信号（RTS）的晶体管的随机数发生器，用于检测由晶体管产生的RTS的RTS检测单元，对由RTS检测检测到的RTS进行超采样的RTS采样单元并且因此产生数字化的RTS，信号状态持续时间检测单元，其从数字化的RTS确定表示所生成的RTS的至少一个第一信号状态的持续时间的第一时间变量和表示持续时间的第二时间变量所产生的RTS的至少一个第二信号状态，以及随机数转换单元，其耦合到所述信号状态持续时间检测单元，并且从所述第一时间变量和所述第二时间变量生成随机数。

19. 发明授权

US07622789B2 Polymer transistor arrangement, integrated circuit arrangement and method for producing a polymer transistor arrangement 失效
标题翻译：聚合物晶体管布置，集成电路布置和用于制造聚合物晶体管布置的方法
公开(公告)号：US07622789B2
公开(公告)日：2009-11-24
申请号：US10714536
申请日：2003-11-13
申请人： Ralf Brederlow
发明人： Ralf Brederlow
IPC分类号： H01L35/24
CPC分类号： B82Y10/00 , G05F1/575 , H01L51/0036 , H01L51/0046 , H01L51/0052 , H01L51/0508
摘要： The invention relates to a polymer transistor arrangement, an integrated circuit arrangement and a method for producing a polymer transistor arrangement. The polymer transistor arrangement contains a polymer transistor formed in and/or on a substrate. The polymer transistor contains a first source/drain region, a second source/drain region, a channel region between the first and second source/drain regions, a gate region and a gate-insulating layer between channel region and gate region. A drive circuit of the polymer transistor arrangement is set up in such a way that it provides the source/drain regions and the gate region with electrical potentials such that the junction between at least one of the source/drain regions and the channel region can be operated as a diode.
摘要翻译：本发明涉及一种聚合物晶体管装置，集成电路装置和一种用于制造聚合物晶体管装置的方法。聚合物晶体管装置包含在衬底中和/或衬底上形成的聚合物晶体管。聚合物晶体管包含第一源极/漏极区域，第二源极/漏极区域，第一和第二源极/漏极区域之间的沟道区域，沟道区域和栅极区域之间的栅极区域和栅极绝缘层。聚合物晶体管布置的驱动电路被设置成使得源极/漏极区域和栅极区域具有电势，使得源极/漏极区域和沟道区域中的至少一个之间的结可以是作为二极管工作。

20. 发明授权

US07426527B2 Random number generator and method for generating a random number 有权
标题翻译：随机数发生器和产生随机数的方法
公开(公告)号：US07426527B2
公开(公告)日：2008-09-16
申请号：US10948627
申请日：2004-09-23
申请人： Thomas Strum , Guido Stromberg , Ralf Brederlow , Werner Weber
发明人： Thomas Strum , Guido Stromberg , Ralf Brederlow , Werner Weber
IPC分类号： G06J1/00 , G06F7/38
CPC分类号： G06F7/588
摘要： Random number generator having a transistor that generates an analog random telegraph signal (RTS) having a first or second signal state, a RTS detection unit for detecting the RTS generated by the transistor, a RTS sampling unit that supersamples the RTS detected by the RTS detection unit and thus generates a digitized RTS, a signal state duration detection unit that determines, from the digitized RTS, a first time variable representing the time duration of at least one first signal state of the generated RTS and a second time variable representing the time duration of at least one second signal state of the generated RTS, and a random number conversion unit, which is coupled to the signal state duration detection unit, and that generates a random number from the first time variable and the second time variable.
摘要翻译：具有产生具有第一或第二信号状态的模拟随机电报信号（RTS）的晶体管的随机数发生器，用于检测由晶体管产生的RTS的RTS检测单元，对由RTS检测检测到的RTS进行超采样的RTS采样单元并且因此产生数字化的RTS，信号状态持续时间检测单元，其从数字化的RTS确定表示所生成的RTS的至少一个第一信号状态的持续时间的第一时间变量和表示持续时间的第二时间变量所产生的RTS的至少一个第二信号状态，以及随机数转换单元，其耦合到所述信号状态持续时间检测单元，并且从所述第一时间变量和所述第二时间变量生成随机数。

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