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1. 发明授权

US07733157B2 Noise-reducing transistor arrangement 有权
标题翻译：降噪晶体管布置
公开(公告)号：US07733157B2
公开(公告)日：2010-06-08
申请号：US10583538
申请日：2004-12-03
申请人： Ralf Brederlow , Jeongwook Koh , Christian Pacha , Roland Thewes
发明人： Ralf Brederlow , Jeongwook Koh , Christian Pacha , Roland Thewes
IPC分类号： H03K17/687
CPC分类号： H03K17/162 , H01L2924/0002 , H01L2924/00
摘要： Noise-reducing transistor arrangement having first and second field effect transistors (FETs) having source terminals coupled together, drain terminals coupled together, and control terminals for application of a first or second signal. A clock generator unit is configured to provide the first and second signals alternately to the FETs with an alternating frequency which is at least as great as the cut-off frequency of the noise characteristic of the FETs, or with a reciprocal alternating frequency which is less than a mean lifetime of an occupation state of a defect in the boundary region between channel region and gate insulating layer of the FETs. The first signal is applied to the control terminal of the first FET and, simultaneously, the second signal to the control terminal of the second FET. The second signal is applied to the control terminal of the first FET and, simultaneously, the first signal to the control terminal of the second FET.
摘要翻译：具有第一和第二场效应晶体管（FET）的降噪晶体管装置，其具有耦合在一起的源极端子，耦合在一起的漏极端子和用于施加第一或第二信号的控制端子。时钟发生器单元被配置为以至少与FET的噪声特性的截止频率一样大的交变频率或者具有较小的互逆交变频率来向FET施加交替的第一和第二信号比FET的沟道区域和栅极绝缘层之间的边界区域的缺陷的占用状态的平均寿命长。第一信号被施加到第一FET的控制端子，并且同时将第二信号施加到第二FET的控制端子。第二信号被施加到第一FET的控制端，同时将第一信号施加到第二FET的控制端。

2. 发明授权

US07733156B2 Transistor arrangement, integrated circuit and method for operating field effect transistors 有权
标题翻译：晶体管布置，集成电路和操作场效应晶体管的方法
公开(公告)号：US07733156B2
公开(公告)日：2010-06-08
申请号：US10570924
申请日：2004-09-01
申请人： Ralf Brederlow , Jeongwook Koh , Roland Thewes
发明人： Ralf Brederlow , Jeongwook Koh , Roland Thewes
IPC分类号： H03K17/16 , H03K17/687
CPC分类号： H03F3/211 , H01L2924/0002 , H03F1/26 , H03F3/72 , H03F2203/21178 , H03F2203/7215 , H01L2924/00
摘要： The transistor arrangement contains a first and a second field effect transistor comprising a first and a second source drain connection and a control connection for applying a first or a second signal. The two field effect transistors are of the same conductive type. The transistor arrangement is configured in such a manner that the first signal can be applied in an alternating manner to the control connection of the first field effect transistor and the second signal can be applied in a simultaneous manner to the control connection of the second field effect transistor, and/or the second signal can be applied to the control connection of the first field effect transistor and the first signal can be applied simultaneously to the control connection of the second field effect transistor.
摘要翻译：晶体管装置包括第一和第二场效应晶体管，其包括第一和第二源极漏极连接以及用于施加第一或第二信号的控制连接。两个场效应晶体管具有相同的导电类型。晶体管布置被配置为使得第一信号可以以交替方式施加到第一场效应晶体管的控制连接，并且第二信号可以以与第二场效应的控制连接同时的方式施加晶体管和/或第二信号可以被施加到第一场效应晶体管的控制连接，并且第一信号可以同时施加到第二场效应晶体管的控制连接。

3. 发明申请

US20070279120A1 Noise-Reducing Transistor Arrangement, Integrated Circuit, and Method for Reducing the Noise of Field Effect Transistors 有权
标题翻译：降噪晶体管布置，集成电路和降低场效应晶体管噪声的方法
公开(公告)号：US20070279120A1
公开(公告)日：2007-12-06
申请号：US10583538
申请日：2004-12-03
申请人： Ralf Brederlow , Jeongwook Koh , Christian Pacha , Roland Thewes
发明人： Ralf Brederlow , Jeongwook Koh , Christian Pacha , Roland Thewes
IPC分类号： H03K17/16
CPC分类号： H03K17/162 , H01L2924/0002 , H01L2924/00
摘要： Noise-reducing transistor arrangement having first and second field effect transistors (FETs) having source terminals coupled together, drain terminals coupled together, and control terminals for application of a first or second signal. A clock generator unit is configured to provide the first and second signals alternately to the FETs with an alternating frequency which is at least as great as the cut-off frequency of the noise characteristic of the FETs, or with a reciprocal alternating frequency which is less than a mean lifetime of an occupation state of a defect in the boundary region between channel region and gate insulating layer of the FETs. The first signal is applied to the control terminal of the first FET and, simultaneously, the second signal to the control terminal of the second FET. The second signal is applied to the control terminal of the first FET and, simultaneously, the first signal to the control terminal of the second FET.
摘要翻译：具有第一和第二场效应晶体管（FET）的降噪晶体管装置，其具有耦合在一起的源极端子，耦合在一起的漏极端子和用于施加第一或第二信号的控制端子。时钟发生器单元被配置为以至少与FET的噪声特性的截止频率一样大的交变频率或者具有较小的互逆交变频率来向FET施加交替的第一和第二信号比FET的沟道区域和栅极绝缘层之间的边界区域的缺陷的占用状态的平均寿命长。第一信号被施加到第一FET的控制端子，并且同时将第二信号施加到第二FET的控制端子。第二信号被施加到第一FET的控制端，同时将第一信号施加到第二FET的控制端。

4. 发明申请

US20070176634A1 Transistor arrangement, integrated circuit and method for operating field effect transistors 有权
标题翻译：晶体管布置，集成电路和操作场效应晶体管的方法
公开(公告)号：US20070176634A1
公开(公告)日：2007-08-02
申请号：US10570924
申请日：2004-09-01
申请人： Ralf Brederlow , Jeongwook Koh , Roland Thewes
发明人： Ralf Brederlow , Jeongwook Koh , Roland Thewes
IPC分类号： H03K19/094
CPC分类号： H03F3/211 , H01L2924/0002 , H03F1/26 , H03F3/72 , H03F2203/21178 , H03F2203/7215 , H01L2924/00
摘要： The transistor arrangement contains a first and a second field effect transistor comprising a first and a second source drain connection and a control connection for applying a first or a second signal. The two field effect transistors are of the same conductive type. The transistor arrangement is configured in such a manner that the first signal can be applied in an alternating manner to the control connection of the first field effect transistor and the second signal can be applied in a simultaneous manner to the control connection of the second field effect transistor, and/or the second signal can be applied to the control connection of the first field effect transistor and the first signal can be applied simultaneously to the control connection of the second field effect transistor.
摘要翻译：晶体管装置包括第一和第二场效应晶体管，其包括第一和第二源极漏极连接以及用于施加第一或第二信号的控制连接。两个场效应晶体管具有相同的导电类型。晶体管布置被配置为使得第一信号可以以交替方式施加到第一场效应晶体管的控制连接，并且第二信号可以以与第二场效应的控制连接同时的方式施加晶体管和/或第二信号可以被施加到第一场效应晶体管的控制连接，并且第一信号可以同时施加到第二场效应晶体管的控制连接。

5. 发明授权

US07817037B2 Electronic component with ID tags 有权
标题翻译：具有ID标签的电子元件
公开(公告)号：US07817037B2
公开(公告)日：2010-10-19
申请号：US10562458
申请日：2004-06-30
申请人： Ralf Brederlow , Sylvain Briole , Christian Pacha , Roland Thewes , Werner Weber
发明人： Ralf Brederlow , Sylvain Briole , Christian Pacha , Roland Thewes , Werner Weber
IPC分类号： G08B13/14 , H03K7/08
CPC分类号： G06K19/0723
摘要： The invention relates to an electronic component that can be operated by means of an alternating voltage. Said component includes at least one input, at least one output and a pair of electronic sub-components with an identical function. The input(s) of the electronic component is/are coupled to a respective input of the electronic sub-components with an identical function and the output(s) of the electronic component is/are coupled to a respective output of said electronic sub-components. In addition, the electronic component is configured in such a way that at least one output only one output signal of the first sub-component of the pair of functionally identical electronic components can be picked up during a first half-wave of an alternating voltage, whereas only one output signal of the second sub-component of the pair of functionally identical electronic can be picked up during the second half-wave of the alternating voltage.
摘要翻译：本发明涉及可以通过交流电压操作的电子部件。所述组件包括具有相同功能的至少一个输入，至少一个输出和一对电子子部件。电子部件的输入端以相同的功能耦合到电子子部件的相应输入端，并且电子部件的输出耦合到所述电子部件的相应输出端，组件。此外，电子部件被配置为使得在交流电压的第一半波期间可以拾取一对功能相同的电子部件中的第一子部件的至少一个输出信号的一个输出信号，而一对功能相同的电子对的第二子分量的一个输出信号可以在交流电压的第二个半波期间被拾取。

6. 发明授权

US07688625B2 Circuit arrangement and method for operating a circuit arrangement 有权
标题翻译：用于操作电路装置的电路布置和方法
公开(公告)号：US07688625B2
公开(公告)日：2010-03-30
申请号：US12032202
申请日：2008-02-15
申请人： Ralf Brederlow , Roland Thewes
发明人： Ralf Brederlow , Roland Thewes
IPC分类号： G11C16/04 , G11C5/14
CPC分类号： G11C16/10 , G11C16/22 , G11C16/30
摘要： A circuit arrangement includes a nonvolatile memory cell having a continuously variable characteristic that can be read out. A programming unit is coupled to the memory cell and designed to apply an analog signal to the memory cell in order to vary the characteristic, if the characteristic lies within a predetermined range of values, in such a way that the characteristic lies outside the predetermined range of values. A supply voltage unit is provided for providing a supply voltage. A changeover unit is coupled to the supply voltage unit and to the programming unit and designed to trigger the application of the analog signal to the memory cell if the supply voltage is interrupted.
摘要翻译：电路装置包括具有可读出的连续可变特性的非易失性存储单元。编程单元耦合到存储器单元并且被设计为将模拟信号施加到存储器单元，以便如果特性位于预定值范围内，则改变特性，使得特性位于预定范围之外的价值观。提供电源电压单元以提供电源电压。转换单元耦合到电源电压单元和编程单元，并且被设计成如果电源电压被中断则触发模拟信号施加到存储单元。

7. 发明申请

US20080198653A1 CIRCUIT ARRANGEMENT AND METHOD FOR OPERATING A CIRCUIT ARRANGEMENT 有权
标题翻译：电路布置和操作电路布置的方法
公开(公告)号：US20080198653A1
公开(公告)日：2008-08-21
申请号：US12032202
申请日：2008-02-15
申请人： Ralf Brederlow , Roland Thewes
发明人： Ralf Brederlow , Roland Thewes
IPC分类号： G11C11/34
CPC分类号： G11C16/10 , G11C16/22 , G11C16/30
摘要： A circuit arrangement includes a nonvolatile memory cell having a continuously variable characteristic that can be read out. A programming unit is coupled to the memory cell and designed to apply an analog signal to the memory cell in order to vary the characteristic, if the characteristic lies within a predetermined range of values, in such a way that the characteristic lies outside the predetermined range of values. A supply voltage unit is provided for providing a supply voltage. A changeover unit is coupled to the supply voltage unit and to the programming unit and designed to trigger the application of the analog signal to the memory cell if the supply voltage is interrupted.
摘要翻译：电路装置包括具有可读出的连续可变特性的非易失性存储单元。编程单元耦合到存储器单元并且被设计为将模拟信号施加到存储器单元，以便如果特性位于预定值范围内，则改变特性，使得特性位于预定范围之外的价值观。提供电源电压单元以提供电源电压。转换单元耦合到电源电压单元和编程单元，并且被设计成如果电源电压被中断则触发模拟信号施加到存储单元。

8. 发明申请

US20080197430A1 Biochemical Semiconductor Chip Laboratory Comprising A Coupled Address And Control Chip And Method For Producing The Same 审中-公开
标题翻译：生物化学半导体芯片实验室，包括耦合地址和控制芯片及其生产方法
公开(公告)号：US20080197430A1
公开(公告)日：2008-08-21
申请号：US11791963
申请日：2005-11-29
申请人： Robert Aigner , Ralf Brederlow , Lude Elbrecht , Heinrich Heiss , Stephan Marksteiner , Werner Simburger , Roland Thewes , Hans-Jorg Timme
发明人： Robert Aigner , Ralf Brederlow , Lude Elbrecht , Heinrich Heiss , Stephan Marksteiner , Werner Simburger , Roland Thewes , Hans-Jorg Timme
IPC分类号： H01L27/00 , H01L21/00 , G01N29/00
CPC分类号： G01N29/036 , B01L3/5085 , B01L2300/0645 , B01L2300/0663 , B01L2300/0819 , G01N33/02 , G01N33/15 , G01N33/48707 , G01N2291/0256 , H01L2224/81801 , H01L2924/01068 , H01L2924/13091 , H01L2924/00
摘要： A biochemical semiconductor chip laboratory is disclosed including a coupled address and control chip for biochemical analyses and a method for producing the same. In at least one embodiment the semiconductor chip laboratory has a semiconductor sensor chip, which provides numerous analytical positions for biochemical samples in a matrix. The sensor chip is located on the address and control chip and the analytical positions are in electric contact with a printed contact structure on the upper face of the address and control chip via low-resistance through-platings through the semiconductor substrate of the semiconductor chip.
摘要翻译：公开了一种生物化学半导体芯片实验室，其包括用于生化分析的耦合地址和控制芯片及其制造方法。在至少一个实施例中，半导体芯片实验室具有半导体传感器芯片，其为矩阵中的生物化学样品提供许多分析位置。传感器芯片位于地址和控制芯片上，并且分析位置通过半导体芯片的半导体衬底的低电阻穿透与地址和控制芯片的上表面上的印刷接触结构电接触。

9. 发明申请

US20090322404A1 Arrangement, Use of an Arrangement, Reference Voltage Source and Method for Generating a Voltage Value Linearly Proportional to the Temperature 有权
标题翻译：布置，使用布置，参考电压源和生成与温度成线性比例的电压值的方法
公开(公告)号：US20090322404A1
公开(公告)日：2009-12-31
申请号：US12403837
申请日：2009-03-13
申请人： Roland Thewes , Ralf Brederlow
发明人： Roland Thewes , Ralf Brederlow
IPC分类号： G06F7/556
CPC分类号： G01K7/01
摘要： The invention relates to an arrangement comprising a logarithmizing unit and a subtracting unit, wherein the subtracting unit has an output at which a voltage value linearly proportional to the temperature can be tapped off.
摘要翻译：本发明涉及一种包括对数单元和减法单元的装置，其中减法单元具有与温度成线性比例的电压值可以被分接的输出。

10. 发明授权

US07429001B2 Label identification system and coding method suited therefor 失效
标题翻译：标签识别系统及其编码方法
公开(公告)号：US07429001B2
公开(公告)日：2008-09-30
申请号：US10504376
申请日：2003-02-12
申请人： Ralf Brederlow , Christian Pacha , Roland Thewes , Werner Weber
发明人： Ralf Brederlow , Christian Pacha , Roland Thewes , Werner Weber
IPC分类号： G06K19/06 , G06K7/08 , H04Q5/22
CPC分类号： G06K7/10336 , G06K7/086 , G06K19/067
摘要： The invention relates to a label identification system comprised of a transmitting-receiving unit and of identification labels on which the identification information is stored in the form of a digital identification information word. The provision of a circuit on the identification label in the form of a circuit arrangement, which is prefabricated using a polymer technique and on which the identification information is subsequently placed by the offset printing of conductor tracks, enables the provision of an identification label involving a minimal consumption of energy during inexpensive mass production. The bulk of the identification information processing is transferred to the transmitting-receiving unit.
摘要翻译：本发明涉及一种标签识别系统，包括发送接收单元和识别标签，识别信息以数字识别信息字的形式存储在其上。使用聚合物技术预制的电路装置形式的识别标签上的电路的提供，并且随后通过导体迹线的胶印印刷识别信息，能够提供涉及在廉价大规模生产中能量消耗最小化。识别信息处理的大部分被传送到发送 - 接收单元。

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