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    • 6. 发明申请
    • ELECTRONIC DEVICE AND METHOD FOR DISCRETE LOAD ADAPTIVE VOLTAGE REGULATION
    • 用于离散负载自适应电压调节的电子设备和方法
    • US20120062197A1
    • 2012-03-15
    • US13180367
    • 2011-07-11
    • Michael LüdersRalf BrederlowRüdiger Kuhn
    • Michael LüdersRalf BrederlowRüdiger Kuhn
    • G05F1/10
    • G05F1/565G05F1/563
    • The invention relates to an electronic device which comprises a voltage regulator for providing a regulated output voltage to an electronic circuit and a control stage coupled to control the voltage regulator. The control stage is further configured to detect a request for a change of a system configuration of the electronic circuit coupled to receive the output voltage of the voltage regulator, to determine an activity factor of the electronic circuit for the requested system configuration, to determine a system clock frequency of a system clock of the electronic circuit, to determine a required current drive level of the voltage regulator based on the activity factor, the system clock frequency or the product of both, and to adjust the current drive level of the voltage regulator to the requested current drive level.
    • 本发明涉及一种电子设备,其包括用于向电子电路提供调节的输出电压的电压调节器和耦合以控制电压调节器的控制级。 控制级进一步被配置为检测耦合以接收电压调节器的输出电压的电子电路的系统配置的改变的请求,以确定所请求的系统配置的电子电路的活动因子,以确定 系统时钟频率的电子电路的系统时钟,基于活动因子,系统时钟频率或两者的乘积来确定电压调节器所需的电流驱动电平,并调整电压调节器的当前驱动电平 到所请求的当前驱动器级别。
    • 9. 发明申请
    • Noise-Reducing Transistor Arrangement, Integrated Circuit, and Method for Reducing the Noise of Field Effect Transistors
    • 降噪晶体管布置,集成电路和降低场效应晶体管噪声的方法
    • US20070279120A1
    • 2007-12-06
    • US10583538
    • 2004-12-03
    • Ralf BrederlowJeongwook KohChristian PachaRoland Thewes
    • Ralf BrederlowJeongwook KohChristian PachaRoland Thewes
    • H03K17/16
    • H03K17/162H01L2924/0002H01L2924/00
    • Noise-reducing transistor arrangement having first and second field effect transistors (FETs) having source terminals coupled together, drain terminals coupled together, and control terminals for application of a first or second signal. A clock generator unit is configured to provide the first and second signals alternately to the FETs with an alternating frequency which is at least as great as the cut-off frequency of the noise characteristic of the FETs, or with a reciprocal alternating frequency which is less than a mean lifetime of an occupation state of a defect in the boundary region between channel region and gate insulating layer of the FETs. The first signal is applied to the control terminal of the first FET and, simultaneously, the second signal to the control terminal of the second FET. The second signal is applied to the control terminal of the first FET and, simultaneously, the first signal to the control terminal of the second FET.
    • 具有第一和第二场效应晶体管(FET)的降噪晶体管装置,其具有耦合在一起的源极端子,耦合在一起的漏极端子和用于施加第一或第二信号的控制端子。 时钟发生器单元被配置为以至少与FET的噪声特性的截止频率一样大的交变频率或者具有较小的互逆交变频率来向FET施加交替的第一和第二信号 比FET的沟道区域和栅极绝缘层之间的边界区域的缺陷的占用状态的平均寿命长。 第一信号被施加到第一FET的控制端子,并且同时将第二信号施加到第二FET的控制端子。 第二信号被施加到第一FET的控制端,同时将第一信号施加到第二FET的控制端。