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1. 发明授权

US08736354B2 Electronic device and method providing a voltage reference 有权
标题翻译：提供电压参考的电子设备和方法
公开(公告)号：US08736354B2
公开(公告)日：2014-05-27
申请号：US12955046
申请日：2010-11-29
申请人： Vadim V. Ivanov , Johannes Gerber , Ralf Brederlow
发明人： Vadim V. Ivanov , Johannes Gerber , Ralf Brederlow
IPC分类号： G05F1/10
CPC分类号： G05F3/205 , G05F3/20 , G05F3/30
摘要： An electronic device includes a bandgap reference voltage generation stage. The bandgap reference voltage generation stage comprises a device with a PN-junction, a current source feeding a first current during a first period of time and a second higher current during a second period of time through the PN-junction. The bandgap reference voltage is generated from a combination of a first voltage drop across the PN-junction during the first period of time and a second voltage drop across the PN-junction during the second period of time. This bandgap reference voltage is formed using switched capacitors.
摘要翻译：电子装置包括带隙参考电压产生级。带隙参考电压产生级包括具有PN结的器件，在第一时间段期间馈送第一电流的电流源和在第二时间段期间通过PN结的第二较高电流。带隙参考电压是从第一时间段内的PN结上的第一电压降与第二时间段内的PN结上的第二压降的组合产生的。该带隙参考电压使用开关电容器形成。

2. 发明申请

US20130293289A1 Electronic Device and Method Providing a Voltage Reference 有权
标题翻译：提供电压参考的电子设备和方法
公开(公告)号：US20130293289A1
公开(公告)日：2013-11-07
申请号：US12955046
申请日：2010-11-29
申请人： Vadim V. Ivanov , Johannes Gerber , Ralf Brederlow
发明人： Vadim V. Ivanov , Johannes Gerber , Ralf Brederlow
IPC分类号： G05F3/20
CPC分类号： G05F3/205 , G05F3/20 , G05F3/30
摘要： An electronic device includes a bandgap reference voltage generation stage. The bandgap reference voltage generation stage comprises a device with a PN-junction, a current source feeding a first current during a first period of time and a second higher current during a second period of time through the PN-junction. The bandgap reference voltage is generated from a combination of a first voltage drop across the PN-junction during the first period of time and a second voltage drop across the PN-junction during the second period of time. This bandgap reference voltage is formed using switched capacitors.
摘要翻译：电子装置包括带隙参考电压产生级。带隙参考电压产生级包括具有PN结的器件，在第一时间段期间馈送第一电流的电流源和在第二时间段期间通过PN结的第二较高电流。带隙参考电压是从第一时间段内的PN结上的第一电压降与第二时间段内的PN结上的第二压降的组合产生的。该带隙参考电压使用开关电容器形成。

3. 发明授权

US08183906B2 Arrangement, use of an arrangement, reference voltage source and method for generating a voltage value linearly proportional to the temperature 有权
标题翻译：布置，使用布置，参考电压源和用于产生与温度成线性比例的电压值的方法
公开(公告)号：US08183906B2
公开(公告)日：2012-05-22
申请号：US12403837
申请日：2009-03-13
申请人： Roland Thewes , Ralf Brederlow
发明人： Roland Thewes , Ralf Brederlow
IPC分类号： G06G7/24
CPC分类号： G01K7/01
摘要： The invention relates to an arrangement comprising a logarithmizing unit and a subtracting unit, wherein the subtracting unit has an output at which a voltage value linearly proportional to the temperature can be tapped off.
摘要翻译：本发明涉及一种包括对数单元和减法单元的装置，其中减法单元具有与温度成线性比例的电压值可以被分接的输出。

4. 发明申请

US20120062197A1 ELECTRONIC DEVICE AND METHOD FOR DISCRETE LOAD ADAPTIVE VOLTAGE REGULATION 审中-公开
标题翻译：用于离散负载自适应电压调节的电子设备和方法
公开(公告)号：US20120062197A1
公开(公告)日：2012-03-15
申请号：US13180367
申请日：2011-07-11
申请人： Michael Lüders , Ralf Brederlow , Rüdiger Kuhn
发明人： Michael Lüders , Ralf Brederlow , Rüdiger Kuhn
IPC分类号： G05F1/10
CPC分类号： G05F1/565 , G05F1/563
摘要： The invention relates to an electronic device which comprises a voltage regulator for providing a regulated output voltage to an electronic circuit and a control stage coupled to control the voltage regulator. The control stage is further configured to detect a request for a change of a system configuration of the electronic circuit coupled to receive the output voltage of the voltage regulator, to determine an activity factor of the electronic circuit for the requested system configuration, to determine a system clock frequency of a system clock of the electronic circuit, to determine a required current drive level of the voltage regulator based on the activity factor, the system clock frequency or the product of both, and to adjust the current drive level of the voltage regulator to the requested current drive level.
摘要翻译：本发明涉及一种电子设备，其包括用于向电子电路提供调节的输出电压的电压调节器和耦合以控制电压调节器的控制级。控制级进一步被配置为检测耦合以接收电压调节器的输出电压的电子电路的系统配置的改变的请求，以确定所请求的系统配置的电子电路的活动因子，以确定系统时钟频率的电子电路的系统时钟，基于活动因子，系统时钟频率或两者的乘积来确定电压调节器所需的电流驱动电平，并调整电压调节器的当前驱动电平到所请求的当前驱动器级别。

5. 发明申请

US20090322371A1 Measuring Arrangement, Semiconductor Arrangement and Method for Operating a Semiconductor Component as a Reference Source 失效
标题翻译：测量布置，半导体布置和操作半导体部件作为参考源的方法
公开(公告)号：US20090322371A1
公开(公告)日：2009-12-31
申请号：US12399581
申请日：2009-03-06
申请人： Ralf Brederlow , Roland Thewes
发明人： Ralf Brederlow , Roland Thewes
IPC分类号： G01R31/26
CPC分类号： H01L29/78 , G01R35/007
摘要： The invention relates to a measuring arrangement, a semiconductor arrangement and a method for operating a reference source, wherein at least one semiconductor component and a voltage source are connected to a measuring unit and the measuring unit provides a measured value that is proportional to the number of defects.
摘要翻译：本发明涉及一种用于操作参考源的测量装置，半导体装置和方法，其中至少一个半导体部件和电压源连接到测量单元，并且测量单元提供与数字成比例的测量值的缺陷。

6. 发明申请

US20080259665A1 Rectifier Circuit, Circuit Arrangement and Method for Manufactiring a Rectifier Circuit 审中-公开
标题翻译：整流电路，电路布置及整流电路制造方法
公开(公告)号：US20080259665A1
公开(公告)日：2008-10-23
申请号：US11629941
申请日：2005-05-18
申请人： Ralf Brederlow , Christian Pacha , Roland Thewes , Werner Weber
发明人： Ralf Brederlow , Christian Pacha , Roland Thewes , Werner Weber
IPC分类号： H02M7/217
CPC分类号： H02M7/217 , G01S13/75 , H02M7/219
摘要： One aspect of the invention relates to a rectifier circuit for providing a rectified voltage, with a first AC voltage terminal to which an AC voltage can be applied, with a first DC voltage terminal to which a DC voltage can be provided, and with a control switching element between the first AC voltage terminal and the first DC voltage terminal. The control switching element only couples the first AC voltage terminal to the first DC voltage terminal if the electrical potential at the first AC voltage terminal has a predeterminable polarity compared with a reference potential and if the amount of the electrical potential at the first DC voltage terminal is less than or equal to the amount of the electrical potential at the first AC voltage terminal.
摘要翻译：本发明的一个方面涉及一种用于提供整流电压的整流器电路，其中可以施加有交流电压的第一交流电压端子与可以提供直流电压的第一直流电压端子和控制器第一交流电压端子和第一直流电压端子之间的开关元件。如果第一AC电压端子的电位与参考电位相比具有可预定的极性，并且如果第一直流电压端子处的电位量，则控制开关元件仅将第一AC电压端子耦合到第一DC电压端子小于或等于第一AC电压端子处的电位量。

7. 发明申请

US20070279120A1 Noise-Reducing Transistor Arrangement, Integrated Circuit, and Method for Reducing the Noise of Field Effect Transistors 有权
标题翻译：降噪晶体管布置，集成电路和降低场效应晶体管噪声的方法
公开(公告)号：US20070279120A1
公开(公告)日：2007-12-06
申请号：US10583538
申请日：2004-12-03
申请人： Ralf Brederlow , Jeongwook Koh , Christian Pacha , Roland Thewes
发明人： Ralf Brederlow , Jeongwook Koh , Christian Pacha , Roland Thewes
IPC分类号： H03K17/16
CPC分类号： H03K17/162 , H01L2924/0002 , H01L2924/00
摘要： Noise-reducing transistor arrangement having first and second field effect transistors (FETs) having source terminals coupled together, drain terminals coupled together, and control terminals for application of a first or second signal. A clock generator unit is configured to provide the first and second signals alternately to the FETs with an alternating frequency which is at least as great as the cut-off frequency of the noise characteristic of the FETs, or with a reciprocal alternating frequency which is less than a mean lifetime of an occupation state of a defect in the boundary region between channel region and gate insulating layer of the FETs. The first signal is applied to the control terminal of the first FET and, simultaneously, the second signal to the control terminal of the second FET. The second signal is applied to the control terminal of the first FET and, simultaneously, the first signal to the control terminal of the second FET.
摘要翻译：具有第一和第二场效应晶体管（FET）的降噪晶体管装置，其具有耦合在一起的源极端子，耦合在一起的漏极端子和用于施加第一或第二信号的控制端子。时钟发生器单元被配置为以至少与FET的噪声特性的截止频率一样大的交变频率或者具有较小的互逆交变频率来向FET施加交替的第一和第二信号比FET的沟道区域和栅极绝缘层之间的边界区域的缺陷的占用状态的平均寿命长。第一信号被施加到第一FET的控制端子，并且同时将第二信号施加到第二FET的控制端子。第二信号被施加到第一FET的控制端，同时将第一信号施加到第二FET的控制端。

8. 发明授权

US08183879B2 Measuring arrangement, semiconductor arrangement and method for operating a semiconductor component as a reference source 失效
标题翻译：用于操作半导体部件作为参考源的测量布置，半导体布置和方法
公开(公告)号：US08183879B2
公开(公告)日：2012-05-22
申请号：US12399581
申请日：2009-03-06
申请人： Ralf Brederlow , Roland Thewes
发明人： Ralf Brederlow , Roland Thewes
IPC分类号： G01R31/02 , G01R31/26
CPC分类号： H01L29/78 , G01R35/007
摘要： The invention relates to a measuring arrangement, a semiconductor arrangement and a method for operating a reference source, wherein at least one semiconductor component and a voltage source are connected to a measuring unit and the measuring unit provides a measured value that is proportional to the number of defects.
摘要翻译：本发明涉及一种用于操作参考源的测量装置，半导体装置和方法，其中至少一个半导体部件和电压源连接到测量单元，并且测量单元提供与数字成比例的测量值的缺陷。

9. 发明授权

US07820505B2 Integrated circuit arrangement with capacitor and fabrication method 有权
标题翻译：具有电容器的集成电路布置及其制造方法
公开(公告)号：US07820505B2
公开(公告)日：2010-10-26
申请号：US11862640
申请日：2007-09-27
申请人： Ralf Brederlow , Jessica Hartwich , Christian Pacha , Wolfgang Rösner , Thomas Schulz
发明人： Ralf Brederlow , Jessica Hartwich , Christian Pacha , Wolfgang Rösner , Thomas Schulz
IPC分类号： H01L21/8242
CPC分类号： H01L29/785 , H01L21/845 , H01L27/0629 , H01L27/108 , H01L27/10805 , H01L27/10823 , H01L27/10826 , H01L27/1085 , H01L27/10873 , H01L27/10876 , H01L27/10879 , H01L27/1211 , H01L27/13 , H01L28/60 , H01L29/66795
摘要： An integrated circuit arrangement contains an insulating region, which is part of a planar insulating layer, and a capacitor which contains: near and far electrode regions near and remote from the insulating region and a dielectric region. The capacitor and an active component are on the same side of the insulating layer, and the near electrode region and an active region of the component are planar and parallel to the insulating layer. The near electrode region is monocrystalline and contains multiple webs. Alternately, a FET is present in which: a channel region is the active region, the FET contains a web with opposing control electrodes connected by a connecting region that is isolated from the channel region by a thick insulating region. The thick insulating region is thicker than control electrode insulation regions. The control electrodes contain the same material as the far electrode region.
摘要翻译：集成电路装置包括作为平面绝缘层的一部分的绝缘区域和包含：靠近和远离绝缘区域的近远电极区域和电介质区域的电容器。电容器和有源部件位于绝缘层的同一侧，并且组件的近电极区域和有源区域是平面的并且平行于绝缘层。近电极区域是单晶体并且包含多个网状物。或者，存在FET，其中沟道区域是有源区域，FET包含具有相对的控制电极的幅材，该栅极通过由沟道区域与厚绝缘区域隔离的连接区域连接。厚的绝缘区域比控制电极绝缘区域厚。控制电极含有与远电极区域相同的材料。

10. 发明授权

US07733157B2 Noise-reducing transistor arrangement 有权
标题翻译：降噪晶体管布置
公开(公告)号：US07733157B2
公开(公告)日：2010-06-08
申请号：US10583538
申请日：2004-12-03
申请人： Ralf Brederlow , Jeongwook Koh , Christian Pacha , Roland Thewes
发明人： Ralf Brederlow , Jeongwook Koh , Christian Pacha , Roland Thewes
IPC分类号： H03K17/687
CPC分类号： H03K17/162 , H01L2924/0002 , H01L2924/00
摘要： Noise-reducing transistor arrangement having first and second field effect transistors (FETs) having source terminals coupled together, drain terminals coupled together, and control terminals for application of a first or second signal. A clock generator unit is configured to provide the first and second signals alternately to the FETs with an alternating frequency which is at least as great as the cut-off frequency of the noise characteristic of the FETs, or with a reciprocal alternating frequency which is less than a mean lifetime of an occupation state of a defect in the boundary region between channel region and gate insulating layer of the FETs. The first signal is applied to the control terminal of the first FET and, simultaneously, the second signal to the control terminal of the second FET. The second signal is applied to the control terminal of the first FET and, simultaneously, the first signal to the control terminal of the second FET.
摘要翻译：具有第一和第二场效应晶体管（FET）的降噪晶体管装置，其具有耦合在一起的源极端子，耦合在一起的漏极端子和用于施加第一或第二信号的控制端子。时钟发生器单元被配置为以至少与FET的噪声特性的截止频率一样大的交变频率或者具有较小的互逆交变频率来向FET施加交替的第一和第二信号比FET的沟道区域和栅极绝缘层之间的边界区域的缺陷的占用状态的平均寿命长。第一信号被施加到第一FET的控制端子，并且同时将第二信号施加到第二FET的控制端子。第二信号被施加到第一FET的控制端，同时将第一信号施加到第二FET的控制端。

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