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1. 发明申请

US20080038888A1 INTEGRATED CIRCUIT ARRANGEMENT WITH CAPACITOR AND FABRICATION METHOD 有权
标题翻译：集成电路与电容器和制造方法的布置
公开(公告)号：US20080038888A1
公开(公告)日：2008-02-14
申请号：US11862640
申请日：2007-09-27
申请人： Ralf Brederlow , Jessica Hartwich , Christian Pacha , Wolfgang Rosner , Thomas Schulz
发明人： Ralf Brederlow , Jessica Hartwich , Christian Pacha , Wolfgang Rosner , Thomas Schulz
IPC分类号： H01L21/8242
CPC分类号： H01L29/785 , H01L21/845 , H01L27/0629 , H01L27/108 , H01L27/10805 , H01L27/10823 , H01L27/10826 , H01L27/1085 , H01L27/10873 , H01L27/10876 , H01L27/10879 , H01L27/1211 , H01L27/13 , H01L28/60 , H01L29/66795
摘要： An integrated circuit arrangement contains an insulating region, which is part of a planar insulating layer, and a capacitor which contains: near and far electrode regions near and remote from the insulating region and a dielectric region. The capacitor and an active component are on the same side of the insulating layer, and the near electrode region and an active region of the component are planar and parallel to the insulating layer. The near electrode region is monocrystalline and contains multiple webs. Alternately, a FET is present in which: a channel region is the active region, the FET contains a web with opposing control electrodes connected by a connecting region that is isolated from the channel region by a thick insulating region. The thick insulating region is thicker than control electrode insulation regions. The control electrodes contain the same material as the far electrode region.
摘要翻译：集成电路装置包括作为平面绝缘层的一部分的绝缘区域和包含：靠近和远离绝缘区域的近远电极区域和电介质区域的电容器。电容器和有源部件位于绝缘层的同一侧，并且组件的近电极区域和有源区域是平面的并且平行于绝缘层。近电极区域是单晶体并且包含多个网状物。或者，存在FET，其中沟道区域是有源区域，FET包含具有相对的控制电极的幅材，该栅极通过由沟道区域与厚绝缘区域隔离的连接区域连接。厚的绝缘区域比控制电极绝缘区域厚。控制电极含有与远电极区域相同的材料。

2. 发明申请

US20060003526A1 Integrated circuit arrangement comprising a capacitor, and production method 有权
标题翻译：包括电容器的集成电路装置和制造方法
公开(公告)号：US20060003526A1
公开(公告)日：2006-01-05
申请号：US10529990
申请日：2003-10-10
申请人： Ralf Brederlow , Jessica Hartwich , Christian Pacha , Wolfgang Rosner , Thomas Schulz
发明人： Ralf Brederlow , Jessica Hartwich , Christian Pacha , Wolfgang Rosner , Thomas Schulz
IPC分类号： H01L21/8242
CPC分类号： H01L29/785 , H01L21/845 , H01L27/0629 , H01L27/108 , H01L27/10805 , H01L27/10823 , H01L27/10826 , H01L27/1085 , H01L27/10873 , H01L27/10876 , H01L27/10879 , H01L27/1211 , H01L27/13 , H01L28/60 , H01L29/66795
摘要： An integrated circuit arrangement contains an insulating region, which is part of a planar insulating layer, and a capacitor which contains: near and far electrode regions near and remote from the insulating region and a dielectric region. The capacitor and an active component are on the same side of the insulating layer, and the near electrode region and an active region of the component are planar and parallel to the insulating layer. The near electrode region is monocrystalline and contains multiple webs. Alternately, a FET is present in which: a channel region is the active region, the FET contains a web with opposing control electrodes connected by a connecting region that is isolated from the channel region by a thick insulating region. The thick insulating region is thicker than control electrode insulation regions. The control electrodes contain the same material as the far electrode region.
摘要翻译：集成电路装置包括作为平面绝缘层的一部分的绝缘区域和包含：靠近和远离绝缘区域的近远电极区域和电介质区域的电容器。电容器和有源部件位于绝缘层的同一侧，并且组件的近电极区域和有源区域是平面的并且平行于绝缘层。近电极区域是单晶体并且包含多个网状物。或者，存在FET，其中沟道区域是有源区域，FET包含具有相对的控制电极的幅材，该栅极通过由沟道区域与厚绝缘区域隔离的连接区域连接。厚的绝缘区域比控制电极绝缘区域厚。控制电极含有与远电极区域相同的材料。

3. 发明申请

US20090184355A1 INTEGRATED CIRCUIT ARRANGEMENT WITH CAPACITOR AND FABRICATION METHOD 有权
标题翻译：集成电路与电容器和制造方法的布置
公开(公告)号：US20090184355A1
公开(公告)日：2009-07-23
申请号：US12414120
申请日：2009-03-30
申请人： Ralf Brederlow , Jessica Hartwich , Christian Pacha , Wolfgang Rosner , Thomas Schulz
发明人： Ralf Brederlow , Jessica Hartwich , Christian Pacha , Wolfgang Rosner , Thomas Schulz
IPC分类号： H01L29/68 , H01L21/02
CPC分类号： H01L29/785 , H01L21/845 , H01L27/0629 , H01L27/108 , H01L27/10805 , H01L27/10823 , H01L27/10826 , H01L27/1085 , H01L27/10873 , H01L27/10876 , H01L27/10879 , H01L27/1211 , H01L27/13 , H01L28/60 , H01L29/66795
摘要： An integrated circuit arrangement contains an insulating region, which is part of a planar insulating layer, and a capacitor which contains: near and far electrode regions near and remote from the insulating region and a dielectric region. The capacitor and an active component are on the same side of the insulating layer, and the near electrode region and an active region of the component are planar and parallel to the insulating layer. The near electrode region is monocrystalline and contains multiple webs.
摘要翻译：集成电路装置包括作为平面绝缘层的一部分的绝缘区域和包含：靠近和远离绝缘区域的近远电极区域和电介质区域的电容器。电容器和有源部件位于绝缘层的同一侧，并且组件的近电极区域和有源区域是平面的并且平行于绝缘层。近电极区域是单晶体并且包含多个网状物。

4. 发明申请

US20060022302A1 Integrated circuit arrangement comprising capacitors and preferably planar transistors, and production method 有权
标题翻译：集成电路装置，包括电容器和优选平面晶体管，以及制造方法
公开(公告)号：US20060022302A1
公开(公告)日：2006-02-02
申请号：US10531493
申请日：2003-10-10
申请人： Ralf Brederlow , Jessica Hartwich , Christian Pacha , Wolfgang Rosner , Thomas Schulz
发明人： Ralf Brederlow , Jessica Hartwich , Christian Pacha , Wolfgang Rosner , Thomas Schulz
IPC分类号： H01L29/00
CPC分类号： H01L27/1085 , H01L21/84 , H01L27/10805 , H01L27/1203
摘要： An integrated circuit arrangement and method of fabricating the integrated circuit arrangement is described. The integrated circuit arrangement contains an insulating region and a sequence of regions which forms a capacitor. The sequence contains a near electrode region near the insulating region, a dielectric region, and a remote electrode region remote from the insulating region. The insulating region is part of an insulating layer arranged in a plane. The capacitor and an active component are arranged on the same side of the insulating layer and form a memory cell. The near electrode region and an active region of the component are arranged in a plane which lies parallel to the plane in which the insulating layer is arranged. A processor is also contained in the integrated circuit arrangement.
摘要翻译：描述了一种集成电路装置及其制造方法。集成电路装置包含形成电容器的绝缘区域和一系列区域。该序列包含靠近绝缘区域的近电极区域，电介质区域和远离绝缘区域的远程电极区域。绝缘区域是布置在平面中的绝缘层的一部分。电容器和有源部件布置在绝缘层的同一侧上并形成存储单元。组件的近电极区域和有源区域被布置在与布置绝缘层的平面平行的平面中。处理器也包含在集成电路装置中。

5. 发明授权

US07820505B2 Integrated circuit arrangement with capacitor and fabrication method 有权
标题翻译：具有电容器的集成电路布置及其制造方法
公开(公告)号：US07820505B2
公开(公告)日：2010-10-26
申请号：US11862640
申请日：2007-09-27
申请人： Ralf Brederlow , Jessica Hartwich , Christian Pacha , Wolfgang Rösner , Thomas Schulz
发明人： Ralf Brederlow , Jessica Hartwich , Christian Pacha , Wolfgang Rösner , Thomas Schulz
IPC分类号： H01L21/8242
CPC分类号： H01L29/785 , H01L21/845 , H01L27/0629 , H01L27/108 , H01L27/10805 , H01L27/10823 , H01L27/10826 , H01L27/1085 , H01L27/10873 , H01L27/10876 , H01L27/10879 , H01L27/1211 , H01L27/13 , H01L28/60 , H01L29/66795
摘要： An integrated circuit arrangement contains an insulating region, which is part of a planar insulating layer, and a capacitor which contains: near and far electrode regions near and remote from the insulating region and a dielectric region. The capacitor and an active component are on the same side of the insulating layer, and the near electrode region and an active region of the component are planar and parallel to the insulating layer. The near electrode region is monocrystalline and contains multiple webs. Alternately, a FET is present in which: a channel region is the active region, the FET contains a web with opposing control electrodes connected by a connecting region that is isolated from the channel region by a thick insulating region. The thick insulating region is thicker than control electrode insulation regions. The control electrodes contain the same material as the far electrode region.
摘要翻译：集成电路装置包括作为平面绝缘层的一部分的绝缘区域和包含：靠近和远离绝缘区域的近远电极区域和电介质区域的电容器。电容器和有源部件位于绝缘层的同一侧，并且组件的近电极区域和有源区域是平面的并且平行于绝缘层。近电极区域是单晶体并且包含多个网状物。或者，存在FET，其中沟道区域是有源区域，FET包含具有相对的控制电极的幅材，该栅极通过由沟道区域与厚绝缘区域隔离的连接区域连接。厚的绝缘区域比控制电极绝缘区域厚。控制电极含有与远电极区域相同的材料。

6. 发明授权

US07173302B2 Integrated circuit arrangement having capacitors and having planar transistors and fabrication method 有权
标题翻译：具有电容器并具有平面晶体管和制造方法的集成电路装置
公开(公告)号：US07173302B2
公开(公告)日：2007-02-06
申请号：US10531493
申请日：2003-10-10
申请人： Ralf Brederlow , Jessica Hartwich , Christian Pacha , Wolfgang Rösner , Thomas Schulz
发明人： Ralf Brederlow , Jessica Hartwich , Christian Pacha , Wolfgang Rösner , Thomas Schulz
IPC分类号： H01L27/108 , H01L21/8242
CPC分类号： H01L27/1085 , H01L21/84 , H01L27/10805 , H01L27/1203
摘要： An integrated circuit arrangement and method of fabricating the integrated circuit arrangement is described. The integrated circuit arrangement contains an insulating region and a sequence of regions which forms a capacitor. The sequence contains a near electrode region near the insulating region, a dielectric region, and a remote electrode region remote from the insulating region. The insulating region is part of an insulating layer arranged in a plane. The capacitor and an active component are arranged on the same side of the insulating layer and form a memory cell. The near electrode region and an active region of the component are arranged in a plane which lies parallel to the plane in which the insulating layer is arranged. A processor is also contained in the integrated circuit arrangement.
摘要翻译：描述了一种集成电路装置及其制造方法。集成电路装置包含形成电容器的绝缘区域和一系列区域。该序列包含靠近绝缘区域的近电极区域，电介质区域和远离绝缘区域的远程电极区域。绝缘区域是布置在平面中的绝缘层的一部分。电容器和有源部件布置在绝缘层的同一侧上并形成存储单元。组件的近电极区域和有源区域被布置在与布置绝缘层的平面平行的平面中。处理器也包含在集成电路装置中。

7. 发明授权

US07291877B2 Integrated circuit arrangement with capacitor 有权
标题翻译：集成电路布置与电容器
公开(公告)号：US07291877B2
公开(公告)日：2007-11-06
申请号：US10529990
申请日：2003-10-10
申请人： Ralf Brederlow , Jessica Hartwich , Christian Pacha , Wolfgang Rösner , Thomas Schulz
发明人： Ralf Brederlow , Jessica Hartwich , Christian Pacha , Wolfgang Rösner , Thomas Schulz
IPC分类号： H01L29/76
CPC分类号： H01L29/785 , H01L21/845 , H01L27/0629 , H01L27/108 , H01L27/10805 , H01L27/10823 , H01L27/10826 , H01L27/1085 , H01L27/10873 , H01L27/10876 , H01L27/10879 , H01L27/1211 , H01L27/13 , H01L28/60 , H01L29/66795
摘要： An integrated circuit arrangement contains an insulating region, which is part of a planar insulating layer, and a capacitor which contains: near and far electrode regions near and remote from the insulating region and a dielectric region. The capacitor and an active component are on the same side of the insulating layer, and the near electrode region and an active region of the component are planar and parallel to the insulating layer. The near electrode region is monocrystalline and contains multiple webs. Alternately, a FET is present in which: a channel region is the active region, the FET contains a web with opposing control electrodes connected by a connecting region that is isolated from the channel region by a thick insulating region. The thick insulating region is thicker than control electrode insulation regions. The control electrodes contain the same material as the far electrode region.
摘要翻译：集成电路装置包括作为平面绝缘层的一部分的绝缘区域和包含：靠近和远离绝缘区域的近远电极区域和电介质区域的电容器。电容器和有源部件位于绝缘层的同一侧，并且组件的近电极区域和有源区域是平面的并且平行于绝缘层。近电极区域是单晶体并且包含多个网状物。或者，存在FET，其中沟道区域是有源区域，FET包含具有相对的控制电极的幅材，该栅极通过由沟道区域与厚绝缘区域隔离的连接区域连接。厚的绝缘区域比控制电极绝缘区域厚。控制电极含有与远电极区域相同的材料。

8. 发明授权

US08124475B2 Integrated circuit arrangement with capacitor and fabrication method 有权
标题翻译：具有电容器的集成电路布置及其制造方法
公开(公告)号：US08124475B2
公开(公告)日：2012-02-28
申请号：US12414120
申请日：2009-03-30
申请人： Ralf Brederlow , Jessica Hartwich , Christian Pacha , Wolfgang Rösner , Thomas Schulz
发明人： Ralf Brederlow , Jessica Hartwich , Christian Pacha , Wolfgang Rösner , Thomas Schulz
IPC分类号： H01L21/8242
CPC分类号： H01L29/785 , H01L21/845 , H01L27/0629 , H01L27/108 , H01L27/10805 , H01L27/10823 , H01L27/10826 , H01L27/1085 , H01L27/10873 , H01L27/10876 , H01L27/10879 , H01L27/1211 , H01L27/13 , H01L28/60 , H01L29/66795
摘要： An integrated circuit arrangement contains an insulating region, which is part of a planar insulating layer, and a capacitor which contains: near and far electrode regions near and remote from the insulating region and a dielectric region. The capacitor and an active component are on the same side of the insulating layer, and the near electrode region and an active region of the component are planar and parallel to the insulating layer. The near electrode region is monocrystalline and contains multiple webs.
摘要翻译：集成电路装置包括作为平面绝缘层的一部分的绝缘区域和包含：靠近和远离绝缘区域的近远电极区域和电介质区域的电容器。电容器和有源部件位于绝缘层的同一侧，并且组件的近电极区域和有源区域是平面的并且平行于绝缘层。近电极区域是单晶体并且包含多个网状物。

9. 发明授权

US07733157B2 Noise-reducing transistor arrangement 有权
标题翻译：降噪晶体管布置
公开(公告)号：US07733157B2
公开(公告)日：2010-06-08
申请号：US10583538
申请日：2004-12-03
申请人： Ralf Brederlow , Jeongwook Koh , Christian Pacha , Roland Thewes
发明人： Ralf Brederlow , Jeongwook Koh , Christian Pacha , Roland Thewes
IPC分类号： H03K17/687
CPC分类号： H03K17/162 , H01L2924/0002 , H01L2924/00
摘要： Noise-reducing transistor arrangement having first and second field effect transistors (FETs) having source terminals coupled together, drain terminals coupled together, and control terminals for application of a first or second signal. A clock generator unit is configured to provide the first and second signals alternately to the FETs with an alternating frequency which is at least as great as the cut-off frequency of the noise characteristic of the FETs, or with a reciprocal alternating frequency which is less than a mean lifetime of an occupation state of a defect in the boundary region between channel region and gate insulating layer of the FETs. The first signal is applied to the control terminal of the first FET and, simultaneously, the second signal to the control terminal of the second FET. The second signal is applied to the control terminal of the first FET and, simultaneously, the first signal to the control terminal of the second FET.
摘要翻译：具有第一和第二场效应晶体管（FET）的降噪晶体管装置，其具有耦合在一起的源极端子，耦合在一起的漏极端子和用于施加第一或第二信号的控制端子。时钟发生器单元被配置为以至少与FET的噪声特性的截止频率一样大的交变频率或者具有较小的互逆交变频率来向FET施加交替的第一和第二信号比FET的沟道区域和栅极绝缘层之间的边界区域的缺陷的占用状态的平均寿命长。第一信号被施加到第一FET的控制端子，并且同时将第二信号施加到第二FET的控制端子。第二信号被施加到第一FET的控制端，同时将第一信号施加到第二FET的控制端。

10. 发明申请

US20070052457A1 FREQUENCY-DIVIDER CIRCUIT ARRANGEMENT 审中-公开
标题翻译：频率分路器电路布置
公开(公告)号：US20070052457A1
公开(公告)日：2007-03-08
申请号：US11470470
申请日：2006-09-06
申请人： Roland Thewes , Christian Pacha , Ralf Brederlow
发明人： Roland Thewes , Christian Pacha , Ralf Brederlow
IPC分类号： H03K23/00
CPC分类号： H03K23/425
摘要： A frequency-divider circuit arrangement having a power supply, a first clock signal, a second clock signal, a first switch unit, a first capacitance which is connected downstream from the first switch unit is disclosed. A second switch unit is connected downstream from the first capacitance and is controlled by the second clock signal, a second capacitance is connected downstream from the second switch unit and is connected in parallel to the first capacitance, a clock-signal control unit, a capacitance discharge device and a capacitance discharge device control unit.
摘要翻译：公开了一种具有电源，第一时钟信号，第二时钟信号，第一开关单元，连接在第一开关单元下游的第一电容的分频器电路装置。第二开关单元连接在第一电容的下游并由第二时钟信号控制，第二电容连接到第二开关单元的下游并且并联连接到第一电容，时钟信号控制单元，电容放电装置和电容放电装置控制单元。

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