专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

11. 发明授权

US08626480B2 Compact model for device/circuit/chip leakage current (IDDQ) calculation including process induced uplift factors 失效
标题翻译：紧凑型器件/电路/芯片泄漏电流（IDDQ）计算，包括工艺引起的隆起因素
公开(公告)号：US08626480B2
公开(公告)日：2014-01-07
申请号：US12574440
申请日：2009-10-06
申请人： Paul Chang , Jie Deng , Terrence B. Hook , Sim Y. Loo , Anda C. Mocuta , Jae-Eun Park , Kern Rim , Xiaojun Yu
发明人： Paul Chang , Jie Deng , Terrence B. Hook , Sim Y. Loo , Anda C. Mocuta , Jae-Eun Park , Kern Rim , Xiaojun Yu
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G01R31/2848 , G01R31/3008 , G06F17/5009 , G06F17/5022 , G06F17/5036
摘要： A system, method and computer program product for implementing a quiescent current leakage specific model into semiconductor device design and circuit design flows. The leakage model covers all device geometries with wide temperature and voltage ranges and, without the need for stacking factor calculations nor spread sheet based IDDQ calculations. The leakage model for IDDQ calculation incorporates further parasitic and proximity effects. The leakage model implements leakage calculations at different levels of testing, e.g., from a single device to a full chip design, and are integrated within one single model. The leakage model implements leakage calculations at different levels of testing with the leverage of a single switch setting. The implementation is via a hardware definition language code or object oriented code that can be compiled and operated using a netlist of interest, e.g., for conducting a performance analysis.
摘要翻译：一种用于将静态电流泄漏特定模型实现为半导体器件设计和电路设计流程的系统，方法和计算机程序产品。泄漏模型涵盖宽温度和电压范围的所有器件几何，并且不需要堆叠因子计算，也不需要基于平板的IDDQ计算。 IDDQ计算的泄漏模型包含进一步的寄生和邻近效应。泄漏模型在不同的测试水平下实施泄漏计算，例如从单个设备到全芯片设计，并且集成在一个单一的模型中。泄漏模型通过单个开关设置的杠杆来实现不同测试级别的泄漏计算。该实现是通过硬件定义语言代码或面向对象的代码，其可以使用感兴趣的网表来编译和操作，例如用于进行性能分析。

12. 发明授权

US08239790B2 Methods and system for analysis and management of parametric yield 有权
标题翻译：参数收益分析与管理方法与系统
公开(公告)号：US08239790B2
公开(公告)日：2012-08-07
申请号：US13216362
申请日：2011-08-24
申请人： James A. Culp , Paul Chang , Dureseti Chidambarrao , Praveen Elakkumanan , Jason Hibbeler , Anda C. Mocuta
发明人： James A. Culp , Paul Chang , Dureseti Chidambarrao , Praveen Elakkumanan , Jason Hibbeler , Anda C. Mocuta
IPC分类号： G06F17/50
CPC分类号： G01R31/26 , G06F17/5045
摘要： Impact on parametric performance of physical design choices for transistors is scored for on-current and off-current of the transistors. The impact of the design parameters are incorporated into parameters that measure predicted shift in mean on-current and mean off-current and parameters that measure predicted increase in deviations in the distribution of on-current and the off-current. Statistics may be taken at a cell level, a block level, or a chip level to optimize a chip design in a design phase, or to predict changes in parametric yield during manufacturing or after a depressed parametric yield is observed. Further, parametric yield and current level may be predicted region by region and compared with observed thermal emission to pinpoint any anomaly region in a chip to facilitate detection and correction in any mistakes in chip design.
摘要翻译：对晶体管的导通电流和截止电流对晶体管的物理设计选择的参数性能的影响。设计参数的影响被纳入测量平均电流和平均截止电流的预测偏差的参数以及测量导通电流和截止电流分布的偏差预测增加的参数。可以在单元级别，块级或芯片级别进行统计，以在设计阶段优化芯片设计，或者在制造期间或在观察到抑制参数产量之后预测参数产量的变化。此外，可以逐区域地预测参数产量和电流水平，并与观察到的热发射进行比较，以确定芯片中的任何异常区域，以便在芯片设计中的任何错误中进行检测和校正。

13. 发明授权

US07723750B2 MOSFET with super-steep retrograded island 失效
标题翻译：具超级陡峭退火岛的MOSFET
公开(公告)号：US07723750B2
公开(公告)日：2010-05-25
申请号：US11774221
申请日：2007-07-06
申请人： Huilong Zhu , Effendi Leobandung , Anda C. Mocuta , Dan M. Mocuta
发明人： Huilong Zhu , Effendi Leobandung , Anda C. Mocuta , Dan M. Mocuta
IPC分类号： H01L29/737
CPC分类号： H01L29/7842 , H01L21/26586 , H01L21/823807 , H01L21/823814 , H01L29/105 , H01L29/1608 , H01L29/6656 , H01L29/6659 , H01L29/66636 , H01L29/7833 , H01L29/7848
摘要： The present invention comprises a method for forming a semiconducting device including the steps of providing a layered structure including a substrate, a low diffusivity layer of a first-conductivity dopant; and a channel layer; forming a gate stack atop a protected surface of the channel layer; etching the layered structure selective to the gate stack to expose a surface of the substrate, where a remaining portion of the low diffusivity layer provides a retrograded island substantially aligned to the gate stack having a first dopant concentration to reduce short-channel effects without increasing leakage; growing a Si-containing material atop the recessed surface of the substrate; and doping the Si-containing material with a second-conductivity dopant at a second dopant concentration. The low diffusivity layer may be Si1-x-yGexZy, where Z can be carbon (C), xenon (Xe), germanium (Ge), krypton (Kr), argon (Ar), nitrogen (N), or combinations thereof.
摘要翻译：本发明包括一种形成半导体器件的方法，包括以下步骤：提供包括衬底，第一导电掺杂剂的低扩散层的分层结构; 和通道层; 在沟道层的受保护表面上方形成栅极堆叠; 蚀刻对栅极堆叠选择性的层状结构以暴露衬底的表面，其中低扩散层的剩余部分提供基本上与具有第一掺杂剂浓度的栅极堆叠对准的退化岛，以减少短沟道效应而不增加泄漏 ; 在衬底的凹陷表面的顶部生长含Si材料; 并且以第二掺杂剂浓度用第二导电掺杂剂掺杂含Si材料。低扩散性层可以是Si1-x-yGexZy，其中Z可以是碳（C），氙（Xe），锗（Ge），氪（Kr），氩（Ar），氮（N）或它们的组合。

14. 发明授权

US07705345B2 High performance strained silicon FinFETs device and method for forming same 有权
标题翻译：高性能应变硅FinFET器件及其形成方法
公开(公告)号：US07705345B2
公开(公告)日：2010-04-27
申请号：US10751916
申请日：2004-01-07
申请人： Stephen W. Bedell , Kevin K. Chan , Dureseti Chidambarrao , Silke H. Christianson , Jack O. Chu , Anthony G. Domenicucci , Kam-Leung Lee , Anda C. Mocuta , John A. Ott , Qiqing C. Ouyang
发明人： Stephen W. Bedell , Kevin K. Chan , Dureseti Chidambarrao , Silke H. Christianson , Jack O. Chu , Anthony G. Domenicucci , Kam-Leung Lee , Anda C. Mocuta , John A. Ott , Qiqing C. Ouyang
IPC分类号： H01L29/06 , H01L31/072
CPC分类号： H01L29/785 , H01L21/845 , H01L27/1211 , H01L29/66795
摘要： A strained Fin Field Effect Transistor (FinFET) (and method for forming the same) includes a relaxed first material having a sidewall, and a strained second material formed on the sidewall of the first material. The relaxed first material and the strained second material form a fin of the FinFET.
摘要翻译：应变Fin场效应晶体管（FinFET）（及其形成方法）包括具有侧壁的松弛的第一材料和形成在第一材料的侧壁上的应变的第二材料。松弛的第一材料和应变的第二材料形成FinFET的鳍。

15. 发明申请

US20080179636A1 N-FETS WITH TENSILELY STRAINED SEMICONDUCTOR CHANNELS, AND METHOD FOR FABRICATING SAME USING BURIED PSEUDOMORPHIC LAYERS 审中-公开
标题翻译：具有拉伸半导体通道的N-FET以及使用BURIED PSEUDOMORPHIC层的相同方法
公开(公告)号：US20080179636A1
公开(公告)日：2008-07-31
申请号：US11307224
申请日：2007-01-27
申请人： Dureseti Chidambarrao , Effendi Leobandung , Anda C. Mocuta , Dan M. Mocuta , David M. Onsongo , Carl J. Radens
发明人： Dureseti Chidambarrao , Effendi Leobandung , Anda C. Mocuta , Dan M. Mocuta , David M. Onsongo , Carl J. Radens
IPC分类号： H01L29/04 , H01L21/335 , H01L21/8238
CPC分类号： H01L21/26513 , H01L21/26586 , H01L21/823807 , H01L21/823814 , H01L21/823878 , H01L29/1054 , H01L29/1083 , H01L29/165 , H01L29/6653 , H01L29/66628 , H01L29/66636 , H01L29/7849
摘要： The present invention relates to high performance n-channel field effect transistors (n-FETs) that each contains a strained semiconductor channel, and methods for forming such n-FETs by using buried pseudomorphic layers that contain pseudomorphically generated compressive strain.
摘要翻译：本发明涉及各自包含应变半导体通道的高性能n沟道场效应晶体管（n-FET），以及通过使用包含假象形成的压缩应变的掩埋伪晶层来形成这种n-FET的方法。

16. 发明申请

US20130168673A1 Intra Die Variation Monitor Using Through-Silicon Via 失效
标题翻译：使用硅片的内部晶片变化监视器
公开(公告)号：US20130168673A1
公开(公告)日：2013-07-04
申请号：US13342226
申请日：2012-01-03
申请人： Xiaojun Yu , Anda C. Mocuta , Toshiaki Kirihata
发明人： Xiaojun Yu , Anda C. Mocuta , Toshiaki Kirihata
IPC分类号： H01L23/58 , H01L21/66
CPC分类号： H01L22/34 , H01L23/481 , H01L25/0657 , H01L2924/0002 , H01L2924/00
摘要： An apparatus comprising connecting IDVMON monitors with through silicon vias (TSV) to allow the monitors to be connected to probe pads located on the backside of the wafer. Because the backside of the wafer have significantly more space than the front side, the probe pads for IDVMON can be accommodated without sacrificing the silicon area.
摘要翻译：一种设备，包括通过硅通孔（TSV）连接IDVMON监视器，以使监视器能够连接到位于晶片背面的探针焊盘。因为晶片的背面具有比前侧大得多的空间，所以可以容纳用于IDVMON的探针垫，而不牺牲硅面积。

17. 发明授权

US08168971B2 Pseudomorphic Si/SiGe/Si body device with embedded SiGe source/drain 失效
标题翻译：具有嵌入式SiGe源极/漏极的假晶Si / SiGe / Si体器件
公开(公告)号：US08168971B2
公开(公告)日：2012-05-01
申请号：US12054812
申请日：2008-03-25
申请人： Dureseti Chidambarrao , Anda C. Mocuta , Dan M. Mocuta , Carl Radens
发明人： Dureseti Chidambarrao , Anda C. Mocuta , Dan M. Mocuta , Carl Radens
IPC分类号： H01L29/04
CPC分类号： H01L21/84 , H01L21/823807 , H01L21/823814 , H01L21/823878 , H01L27/1203 , H01L29/165 , H01L29/665 , H01L29/66628 , H01L29/66636 , H01L29/7848
摘要： The invention relates to a semiconductor structure and method of manufacturing and more particularly to a CMOS device with at least one embedded SiGe layer in the source/drain region of the PFET, and at least one embedded SiGe layer in the channel region of the NFET. In one embodiment, the structure of the invention enhances the electron mobility in the NFET device, and further enhances the hole mobility in the PFET device. Additionally, by using the fabrication methods and hence achieving the final structure of the invention, it is also possible to construct a PFET and NFET each with embedded SiGe layers on the same substrate.
摘要翻译：本发明涉及半导体结构和制造方法，更具体地说涉及在PFET的源极/漏极区域中具有至少一个嵌入的SiGe层以及在NFET的沟道区域中至少一个嵌入的SiGe层的CMOS器件。在一个实施方案中，本发明的结构增强了NFET器件中的电子迁移率，并进一步提高了PFET器件中的空穴迁移率。此外，通过使用制造方法并因此实现本发明的最终结构，还可以在同一衬底上构造每个具有嵌入的SiGe层的PFET和NFET。

18. 发明申请

US20110169096A1 BALANCING NFET AND PFET PERFORMANCE USING STRAINING LAYERS 失效
标题翻译：使用应变层平衡NFET和PFET性能
公开(公告)号：US20110169096A1
公开(公告)日：2011-07-14
申请号：US12687374
申请日：2010-01-14
申请人： Xiangdong Chen , Weipeng Li , Anda C. Mocuta , Dae-Gyu Park , Melanie J. Sherony , Kenneth J. Stein , Haizhou Yin , Franck Arnaud , Jin-Ping Han , Laegu Kang , Yong Meng Lee , Young Way Teh , Voon-Yew Thean , Da Zhang
发明人： Xiangdong Chen , Weipeng Li , Anda C. Mocuta , Dae-Gyu Park , Melanie J. Sherony , Kenneth J. Stein , Haizhou Yin , Franck Arnaud , Jin-Ping Han , Laegu Kang , Yong Meng Lee , Young Way Teh , Voon-Yew Thean , Da Zhang
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L21/823807 , H01L29/7843
摘要： An integrated circuit structure includes a substrate and at least one pair of complementary transistors on or in the substrate. The pair of complementary transistors comprises a first transistor and a second transistor. The structure also includes a first stress-producing layer on the first transistor and the second transistor, and a second stress-producing layer on the first stress-producing layer over the first transistor and the second transistor. The first stress-producing layer applies tensile strain force on the first transistor and the second transistor. The second stress-producing layer applies compressive strain force on the first stress-producing layer, the first transistor, and the second transistor.
摘要翻译：集成电路结构包括衬底和衬底上或衬底中的至少一对互补晶体管。该对互补晶体管包括第一晶体管和第二晶体管。该结构还包括第一晶体管和第二晶体管上的第一应力产生层，以及在第一晶体管和第二晶体管上的第一应力产生层上的第二应力产生层。第一应力产生层在第一晶体管和第二晶体管上施加拉伸应变力。第二应力产生层对第一应力产生层，第一晶体管和第二晶体管施加压缩应变力。

19. 发明授权

US07879650B2 Method of providing protection against charging damage in hybrid orientation transistors 有权
标题翻译：在混合取向晶体管中提供防止充电损坏的方法
公开(公告)号：US07879650B2
公开(公告)日：2011-02-01
申请号：US12002807
申请日：2007-12-19
申请人： Terence B. Hook , Anda C. Mocuta , Jeffrey W. Sleight , Anthony K. Stamper
发明人： Terence B. Hook , Anda C. Mocuta , Jeffrey W. Sleight , Anthony K. Stamper
IPC分类号： H01L21/8238
CPC分类号： H01L21/84 , H01L21/823807 , H01L21/823878 , H01L27/0251 , H01L27/0629 , H01L27/1203 , H01L27/1207
摘要： In a method of fabricating a CMOS structure, a bulk device can be formed in a first region in conductive communication with an underlying bulk region of the substrate. A first gate conductor may overlie the first region. An SOI device can be formed which has a source drain conduction path in a SOI layer, i.e., a semiconductor layer that is separated from the bulk region by a buried dielectric region. The crystal orientations of the SOI layer and the bulk region can be different. A first diode can be formed in a second region of the substrate in conductive communication with the bulk region. The first diode may be connected in a reverse-biased orientation to a first gate conductor above the SOI layer, such that a voltage on the gate conductor that exceeds the breakdown voltage can be discharged through the first diode to the bulk region of the substrate. A second diode may be formed in a third region of the substrate in conductive communication with the bulk region. The second diode may be connected in a reverse-biased orientation to a source region or a drain region of an NFET.
摘要翻译：在制造CMOS结构的方法中，本体器件可以形成在与衬底的下面的主体区域导电连通的第一区域中。第一栅极导体可以覆盖在第一区域上。可以形成在SOI层中具有源极漏极传导路径的SOI器件，即通过掩埋电介质区域与本体区域分离的半导体层。 SOI层和体区的晶体取向可以不同。第一二极管可以形成在衬底的与体区导电连通的第二区域中。第一二极管可以以反向偏置的方式连接到SOI层上方的第一栅极导体，使得超过击穿电压的栅极导体上的电压可以通过第一二极管放电到衬底的主体区域。第二二极管可以形成在衬底的与体区导电连通的第三区域中。第二二极管可以以反向偏置的方式连接到NFET的源极区域或漏极区域。

20. 发明授权

US07268049B2 Structure and method for manufacturing MOSFET with super-steep retrograded island 失效
标题翻译：具有超陡退化岛的MOSFET的制造和制造方法
公开(公告)号：US07268049B2
公开(公告)日：2007-09-11
申请号：US10954838
申请日：2004-09-30
申请人： Huilong Zhu , Effendi Leobandung , Anda C. Mocuta , Dan M. Mocuta
发明人： Huilong Zhu , Effendi Leobandung , Anda C. Mocuta , Dan M. Mocuta
IPC分类号： H01L21/336
CPC分类号： H01L29/7842 , H01L21/26586 , H01L21/823807 , H01L21/823814 , H01L29/105 , H01L29/1608 , H01L29/6656 , H01L29/6659 , H01L29/66636 , H01L29/7833 , H01L29/7848
摘要： The present invention comprises a method for forming a semiconducting device including the steps of providing a layered structure including a substrate, a low diffusivity layer of a first-conductivity dopant; and a channel layer; forming a gate stack atop a protected surface of the channel layer; etching the layered structure selective to the gate stack to expose a surface of the substrate, where a remaining portion of the low diffusivity layer provides a retrograded island substantially aligned to the gate stack having a first dopant concentration to reduce short-channel effects without increasing leakage; growing a Si-containing material atop the recessed surface of the substrate; and doping the Si-containing material with a second-conductivity dopant at a second dopant concentration. The low diffusivity layer may be Si1-x-yGexZy, where Z can be carbon (C), xenon (Xe), germanium (Ge), krypton (Kr), argon (Ar), nitrogen (N), or combinations thereof.
摘要翻译：本发明包括一种形成半导体器件的方法，包括以下步骤：提供包括衬底，第一导电掺杂剂的低扩散层的分层结构; 和通道层; 在沟道层的受保护表面上方形成栅极堆叠; 蚀刻对栅极堆叠选择性的层状结构以暴露衬底的表面，其中低扩散层的剩余部分提供基本上与具有第一掺杂剂浓度的栅极堆叠对准的退化岛，以减少短沟道效应而不增加泄漏 ; 在衬底的凹陷表面的顶部生长含Si材料; 并且以第二掺杂剂浓度用第二导电掺杂剂掺杂含Si材料。低扩散性层可以是Si 1-xy X z Z z，其中Z可以是碳（C），氙（Xe），锗（Ge），氪（Kr），氩（Ar），氮（N）或其组合。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式