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1. 发明授权

US07705345B2 High performance strained silicon FinFETs device and method for forming same 有权
标题翻译：高性能应变硅FinFET器件及其形成方法
公开(公告)号：US07705345B2
公开(公告)日：2010-04-27
申请号：US10751916
申请日：2004-01-07
申请人： Stephen W. Bedell , Kevin K. Chan , Dureseti Chidambarrao , Silke H. Christianson , Jack O. Chu , Anthony G. Domenicucci , Kam-Leung Lee , Anda C. Mocuta , John A. Ott , Qiqing C. Ouyang
发明人： Stephen W. Bedell , Kevin K. Chan , Dureseti Chidambarrao , Silke H. Christianson , Jack O. Chu , Anthony G. Domenicucci , Kam-Leung Lee , Anda C. Mocuta , John A. Ott , Qiqing C. Ouyang
IPC分类号： H01L29/06 , H01L31/072
CPC分类号： H01L29/785 , H01L21/845 , H01L27/1211 , H01L29/66795
摘要： A strained Fin Field Effect Transistor (FinFET) (and method for forming the same) includes a relaxed first material having a sidewall, and a strained second material formed on the sidewall of the first material. The relaxed first material and the strained second material form a fin of the FinFET.
摘要翻译：应变Fin场效应晶体管（FinFET）（及其形成方法）包括具有侧壁的松弛的第一材料和形成在第一材料的侧壁上的应变的第二材料。松弛的第一材料和应变的第二材料形成FinFET的鳍。

2. 发明授权

US07679141B2 High-quality SGOI by annealing near the alloy melting point 失效
标题翻译：高品质SGOI通过在合金熔点附近退火
公开(公告)号：US07679141B2
公开(公告)日：2010-03-16
申请号：US12027561
申请日：2008-02-07
申请人： Stephen W. Bedell , Huajie Chen , Anthony G. Domenicucci , Keith E. Fogel , Richard J. Murphy , Devendra K. Sadana
发明人： Stephen W. Bedell , Huajie Chen , Anthony G. Domenicucci , Keith E. Fogel , Richard J. Murphy , Devendra K. Sadana
IPC分类号： H01L31/392
CPC分类号： H01L21/26506 , H01L21/324 , H01L21/7624 , H01L21/76254 , H01L29/1054
摘要： A method of forming a low-defect, substantially relaxed SiGe-on-insulator substrate material is provided. The method includes first forming a Ge-containing layer on a surface of a first single crystal Si layer which is present atop a barrier layer that is resistant to Ge diffusion. A heating step is then performed at a temperature that approaches the melting point of the final SiGe alloy and retards the formation of stacking fault defects while retaining Ge. The heating step permits interdiffusion of Ge throughout the first single crystal Si layer and the Ge-containing layer thereby forming a substantially relaxed, single crystal SiGe layer atop the barrier layer. Moreover, because the heating step is carried out at a temperature that approaches the melting point of the final SiGe alloy, defects that persist in the single crystal SiGe layer as a result of relaxation are efficiently annihilated therefrom. In one embodiment, the heating step includes an oxidation process that is performed at a temperature from about 1230° to about 1320° C. for a time period of less than about 2 hours. This embodiment provides SGOI substrate that have minimal surface pitting and reduced crosshatching.
摘要翻译：提供一种形成低缺陷，基本上松弛的绝缘体上硅衬底材料的方法。该方法包括首先在耐Ge扩散的阻挡层上存在的第一单晶Si层的表面上形成含Ge层。然后在接近最终SiGe合金的熔点的温度下进行加热步骤，并且在保留Ge的同时延缓层叠缺陷缺陷的形成。加热步骤允许Ge遍及第一单晶Si层和含Ge层的相互扩散，从而在阻挡层顶部形成基本松弛的单晶SiGe层。此外，由于加热步骤在接近最终SiGe合金的熔点的温度下进行，所以由于弛豫而在单晶SiGe层中持续存在的缺陷被有效地湮灭。在一个实施方案中，加热步骤包括氧化过程，其在约1230℃至约1320℃的温度下进行约少于约2小时的时间。该实施例提供具有最小表面点蚀和减少的交叉阴影的SGOI衬底。

3. 发明授权

US07507988B2 Semiconductor heterostructure including a substantially relaxed, low defect density SiGe layer 失效
标题翻译：包括基本上松弛的低缺陷密度SiGe层的半导体异质结构
公开(公告)号：US07507988B2
公开(公告)日：2009-03-24
申请号：US11619040
申请日：2007-01-02
申请人： Stephen W. Bedell , Huajie Chen , Anthony G. Domenicucci , Keith E. Fogel , Devendra K. Sadana
发明人： Stephen W. Bedell , Huajie Chen , Anthony G. Domenicucci , Keith E. Fogel , Devendra K. Sadana
IPC分类号： H01L29/06
CPC分类号： H01L21/7624 , Y10S438/933 , Y10T428/12674
摘要： A heterostructure is provided which includes a substantially relaxed SiGe layer present atop an insulating region that is located on a substrate. The substantially relaxed SiGe layer has a thickness of from about 2000 nm or less, a measured lattice relaxation of from about 50 to about 80% and a defect density of less than about 108 defects/cm2. A strained epitaxial Si layer is located atop the substantially relaxed SiGe layer and at least one alternating stack including a bottom relaxed SiGe layer and an top strained Si layer located on the strained epitaxial Si layer.
摘要翻译：提供了异质结构，其包括位于衬底上的绝缘区域上的基本上松弛的SiGe层。基本上松弛的SiGe层具有约2000nm或更小的厚度，约50至约80％的测量晶格弛豫和小于约108缺陷/ cm 2的缺陷密度。应变外延Si层位于基本上松弛的SiGe层之上，并且至少一个交替堆叠包括位于应变外延Si层上的底部松弛SiGe层和顶部应变Si层。

4. 发明授权

US07358166B2 Relaxed, low-defect SGOI for strained Si CMOS applications 有权
标题翻译：用于应变Si CMOS应用的轻松，低缺陷SGOI
公开(公告)号：US07358166B2
公开(公告)日：2008-04-15
申请号：US11208359
申请日：2005-08-19
申请人： Paul D. Agnello , Stephen W. Bedell , Robert H. Dennard , Anthony G. Domenicucci , Keith E. Fogel , Devendra K. Sadana
发明人： Paul D. Agnello , Stephen W. Bedell , Robert H. Dennard , Anthony G. Domenicucci , Keith E. Fogel , Devendra K. Sadana
IPC分类号： H01L21/205 , H01L21/477
CPC分类号： H01L21/324 , C30B25/02 , C30B29/52 , H01L21/02378 , H01L21/02381 , H01L21/02532 , H01L21/02664 , H01L21/7624 , H01L21/823807 , H01L21/823878 , H01L21/84 , H01L29/66893 , H01L29/78603
摘要： Thermal mixing methods of forming a substantially relaxed and low-defect SGOI substrate material are provided. The methods include a patterning step which is used to form a structure containing at least SiGe islands formed atop a Ge resistant diffusion barrier layer. Patterning of the SiGe layer into islands changes the local forces acting at each of the island edges in such a way so that the relaxation force is greater than the forces that oppose relaxation. The absence of restoring forces at the edges of the patterned layers allows the final SiGe film to relax further than it would if the film was continuous.
摘要翻译：提供形成基本上松弛和低缺陷的SGOI基底材料的热混合方法。所述方法包括图形化步骤，其用于形成至少包含形成在Ge抗蚀扩散阻挡层顶上的SiGe岛的结构。将SiGe层图案化成岛以这样的方式改变作用在每个岛边缘处的局部力，使得松弛力大于抵抗放松的力。在图案化层的边缘处没有恢复力允许最终的SiGe膜比如果膜是连续的那样进一步松弛。

5. 发明授权

US07348253B2 High-quality SGOI by annealing near the alloy melting point 有权
标题翻译：高品质SGOI通过在合金熔点附近退火
公开(公告)号：US07348253B2
公开(公告)日：2008-03-25
申请号：US10855915
申请日：2004-05-27
申请人： Stephen W. Bedell , Huajie Chen , Anthony G. Domenicucci , Keith E. Fogel , Richard J. Murphy , Devendra K. Sadana
发明人： Stephen W. Bedell , Huajie Chen , Anthony G. Domenicucci , Keith E. Fogel , Richard J. Murphy , Devendra K. Sadana
IPC分类号： H01L21/84
CPC分类号： H01L21/26506 , H01L21/324 , H01L21/7624 , H01L21/76254 , H01L29/1054
摘要： A method of forming a low-defect, substantially relaxed SiGe-on-insulator substrate material is provided. The method includes first forming a Ge-containing layer on a surface of a first single crystal Si layer which is present atop a barrier layer that is resistant to Ge diffusion. A heating step is then performed at a temperature that approaches the melting point of the final SiGe alloy and retards the formation of stacking fault defects while retaining Ge. The heating step permits interdiffusion of Ge throughout the first single crystal Si layer and the Ge-containing layer thereby forming a substantially relaxed, single crystal SiGe layer atop the barrier layer. Moreover, because the heating step is carried out at a temperature that approaches the melting point of the final SiGe alloy, defects that persist in the single crystal SiGe layer as a result of relaxation are efficiently annihilated therefrom. In one embodiment, the heating step includes an oxidation process that is performed at a temperature from about 1230° to about 1320° C. for a time period of less than about 2 hours. This embodiment provides SGOI substrate that have minimal surface pitting and reduced crosshatching.
摘要翻译：提供一种形成低缺陷，基本上松弛的绝缘体上硅衬底材料的方法。该方法包括首先在耐Ge扩散的阻挡层上存在的第一单晶Si层的表面上形成含Ge层。然后在接近最终SiGe合金的熔点的温度下进行加热步骤，并且在保留Ge的同时延缓层叠缺陷缺陷的形成。加热步骤允许Ge遍及第一单晶Si层和含Ge层的相互扩散，从而在阻挡层顶部形成基本松弛的单晶SiGe层。此外，由于加热步骤在接近最终SiGe合金的熔点的温度下进行，所以由于弛豫而在单晶SiGe层中持续存在的缺陷被有效地湮灭。在一个实施方案中，加热步骤包括氧化过程，其在约1230℃至约1320℃的温度下进行约少于约2小时的时间。该实施例提供具有最小表面点蚀和减少的交叉阴影的SGOI衬底。

6. 发明授权

US08227792B2 Relaxed low-defect SGOI for strained SI CMOS applications 有权
标题翻译：用于应变SI CMOS应用的轻松低缺陷SGOI
公开(公告)号：US08227792B2
公开(公告)日：2012-07-24
申请号：US12031530
申请日：2008-02-14
申请人： Paul D. Agnello , Stephen W. Bedell , Robert H. Dennard , Anthony G. Domenicucci , Keith E. Fogel , Devendra K. Sadana
发明人： Paul D. Agnello , Stephen W. Bedell , Robert H. Dennard , Anthony G. Domenicucci , Keith E. Fogel , Devendra K. Sadana
IPC分类号： H01L31/00
CPC分类号： H01L21/324 , C30B25/02 , C30B29/52 , H01L21/02378 , H01L21/02381 , H01L21/02532 , H01L21/02664 , H01L21/7624 , H01L21/823807 , H01L21/823878 , H01L21/84 , H01L29/66893 , H01L29/78603
摘要： Thermal mixing methods of forming a substantially relaxed and low-defect SGOI substrate material are provided. The methods include a patterning step which is used to form a structure containing at least SiGe islands formed atop a Ge resistant diffusion barrier layer. Patterning of the SiGe layer into islands changes the local forces acting at each of the island edges in such a way so that the relaxation force is greater than the forces that oppose relaxation. The absence of restoring forces at the edges of the patterned layers allows the final SiGe film to relax further than it would if the film was continuous.
摘要翻译：提供形成基本上松弛和低缺陷的SGOI基底材料的热混合方法。所述方法包括图形化步骤，其用于形成至少包含形成在Ge抗蚀扩散阻挡层顶上的SiGe岛的结构。将SiGe层图案化成岛以这样的方式改变作用在每个岛边缘处的局部力，使得松弛力大于抵抗放松的力。在图案化层的边缘处没有恢复力允许最终的SiGe膜比如果膜是连续的那样进一步松弛。

7. 发明授权

US07442993B2 Ultra-thin, high quality strained silicon-on-insulator formed by elastic strain transfer 有权
标题翻译：通过弹性应变转移形成的超薄，高品质应变绝缘体上的绝缘体
公开(公告)号：US07442993B2
公开(公告)日：2008-10-28
申请号：US11293774
申请日：2005-12-02
申请人： Stephen W. Bedell , Anthony G. Domenicucci , Keith E. Fogel , Effendi Leobandung , Devendra K. Sadana
发明人： Stephen W. Bedell , Anthony G. Domenicucci , Keith E. Fogel , Effendi Leobandung , Devendra K. Sadana
IPC分类号： H01L31/392
CPC分类号： H01L29/78696 , H01L21/0237 , H01L21/02439 , H01L21/02488 , H01L21/02502 , H01L21/02521 , H01L21/02667 , H01L21/02694 , H01L21/76251 , H01L29/7842
摘要： A method of forming a semiconductor structure comprising a first strained semiconductor layer over an insulating layer is provided in which the first strained semiconductor layer is relatively thin (less than about 500 Å) and has a low defect density (stacking faults and threading defects). The method of the present invention begins with forming a stress-providing layer, such a SiGe alloy layer over a structure comprising a first semiconductor layer that is located atop an insulating layer. The stress-providing layer and the first semiconductor layer are then patterned into at least one island and thereafter the structure containing the at least one island is heated to a temperature that causes strain transfer from the stress-providing layer to the first semiconductor layer. After strain transfer, the stress-providing layer is removed from the structure to form a first strained semiconductor island layer directly atop said insulating layer.
摘要翻译：提供了一种在绝缘层上形成包括第一应变半导体层的半导体结构的方法，其中第一应变半导体层相对较薄（小于约）并且具有低缺陷密度（堆垛层错和穿线缺陷）。本发明的方法开始于在包括位于绝缘层顶部的第一半导体层的结构上形成应力提供层，例如SiGe合金层。然后将应力提供层和第一半导体层图案化成至少一个岛，然后将含有至少一个岛的结构加热到使得应力转移从应力提供层到第一半导体层的温度。在应变转移之后，将应力提供层从结构上去除，以形成直接位于所述绝缘层顶部的第一应变半导体岛层。

8. 发明授权

US06946373B2 Relaxed, low-defect SGOI for strained Si CMOS applications 有权
标题翻译：用于应变Si CMOS应用的轻松，低缺陷SGOI
公开(公告)号：US06946373B2
公开(公告)日：2005-09-20
申请号：US10300189
申请日：2002-11-20
申请人： Paul D. Agnello , Stephen W. Bedell , Robert H. Dennard , Anthony G. Domenicucci , Keith E. Fogel , Devendra K. Sadana
发明人： Paul D. Agnello , Stephen W. Bedell , Robert H. Dennard , Anthony G. Domenicucci , Keith E. Fogel , Devendra K. Sadana
IPC分类号： C30B25/02 , C30B29/52 , H01L21/20 , H01L21/205 , H01L21/324 , H01L21/337 , H01L21/84 , H01L21/477
CPC分类号： H01L21/324 , C30B25/02 , C30B29/52 , H01L21/02378 , H01L21/02381 , H01L21/02532 , H01L21/02664 , H01L21/7624 , H01L21/823807 , H01L21/823878 , H01L21/84 , H01L29/66893 , H01L29/78603
摘要： Thermal mixing methods of forming a substantially relaxed and low-defect SGOI substrate material are provided. The methods include a patterning step which is used to form a structure containing at least SiGe islands formed atop a Ge resistant diffusion barrier layer. Patterning of the SiGe layer into islands changes the local forces acting at each of the island edges in such a way so that the relaxation force is greater than the forces that oppose relaxation. The absence of restoring forces at the edges of the patterned layers allows the final SiGe film to relax further than it would if the film was continuous.
摘要翻译：提供形成基本上松弛和低缺陷的SGOI基底材料的热混合方法。所述方法包括图形化步骤，其用于形成至少包含形成在Ge抗蚀扩散阻挡层顶上的SiGe岛的结构。将SiGe层图案化成岛以这样的方式改变作用在每个岛边缘处的局部力，使得松弛力大于抵抗放松的力。在图案化层的边缘处没有恢复力允许最终的SiGe膜比如果膜是连续的那样进一步松弛。

9. 发明授权

US06875982B2 Electron microscope magnification standard providing precise calibration in the magnification range 5000X-2000,000X 失效
标题翻译：电子显微镜放大标准提供5000X-2000,000X倍率范围内的精确校准
公开(公告)号：US06875982B2
公开(公告)日：2005-04-05
申请号：US10604989
申请日：2003-08-29
申请人： Stephen W. Bedell , John Bruley , Anthony G. Domenicucci , Devendra K. Sadana
发明人： Stephen W. Bedell , John Bruley , Anthony G. Domenicucci , Devendra K. Sadana
IPC分类号： G01N1/28 , G01N23/04 , H01J37/26
CPC分类号： G01N23/04 , G01N2001/2893 , H01J37/261 , H01J2237/2826
摘要： A method and calibration standard for fabricating on a single substrate a series of crystalline pairs such that the d-spacing difference between the pairs will generate Moire fringes of the correct spacings to optimally calibrate the magnification settings of an electron microscope over a variety of magnification settings in the range of 5000× to 200,000×. The invention enables the tailoring of Moire fringe spacings to a desired magnification setting for calibration purposes by fabricating a series of patterns on a single substrate whereby each magnification setting is easily calibrated using a specific SGOI structure that is selected by a simple x-y translation across the top plan surface of the SGOI structure, therein eliminating the need for removing calibration samples in and out of the electron microscope. The method and calibration standard may be used for calibrating electron microscopes, such as, scanning transmission electron microscopes and transmission electron microscopes.
摘要翻译：一种用于在单个基板上制造一系列晶体对的方法和校准标准，使得对之间的d间距差会产生正确间隔的莫尔条纹，以便通过各种放大设置最佳地校准电子显微镜的放大倍率设置在5000x到200,000x的范围内。通过在单个基板上制造一系列图案，本发明可以通过在单个基板上制造一系列图案来将莫尔条纹间距定制到所需的放大倍率设置，从而可以使用特定的SGOI结构轻松校准每个放大倍数设置，该SGOI结构通过顶部的简单xy平移 SGOI结构的平面表面，其中不需要将校准样品移入和移出电子显微镜。该方法和校准标准可用于校准电子显微镜，例如扫描透射电子显微镜和透射电子显微镜。

10. 发明授权

US07473587B2 High-quality SGOI by oxidation near the alloy melting temperature 有权
标题翻译：高品质的SGOI通过氧化在合金熔化温度附近
公开(公告)号：US07473587B2
公开(公告)日：2009-01-06
申请号：US11029921
申请日：2005-01-05
申请人： Stephen W. Bedell , Anthony G. Domenicucci , Keith E. Fogel , Devendra K. Sadana
发明人： Stephen W. Bedell , Anthony G. Domenicucci , Keith E. Fogel , Devendra K. Sadana
IPC分类号： H01L21/00 , H01L21/44
CPC分类号： H01L21/26506 , H01L21/324 , H01L21/7624 , H01L21/76254 , H01L29/1054
摘要： A method of forming a low-defect, substantially relaxed SiGe-on-insulator substrate material is provided. The method includes first forming a Ge-containing layer on a surface of a first single crystal Si layer which is present atop a barrier layer that is resistant to Ge diffusion. A heating step is then performed at a temperature that approaches the melting point of the final SiGe alloy and retards the formation of stacking fault defects while retaining Ge. The heating step permits interdiffusion of Ge throughout the first single crystal Si layer and the Ge-containing layer thereby forming a substantially relaxed, single crystal SiGe layer atop the barrier layer. Moreover, because the heating step is carried out at a temperature that approaches the melting point of the final SiGe alloy, defects that persist in the single crystal SiGe layer as a result of relaxation are efficiently annihilated therefrom.
摘要翻译：提供一种形成低缺陷，基本上松弛的绝缘体上硅衬底材料的方法。该方法包括首先在耐Ge扩散的阻挡层上存在的第一单晶Si层的表面上形成含Ge层。然后在接近最终SiGe合金的熔点的温度下进行加热步骤，并且在保留Ge的同时延缓层叠缺陷缺陷的形成。加热步骤允许Ge遍及第一单晶Si层和含Ge层的相互扩散，从而在阻挡层顶部形成基本松弛的单晶SiGe层。此外，由于加热步骤在接近最终SiGe合金的熔点的温度下进行，所以由于弛豫而在单晶SiGe层中持续存在的缺陷被有效地湮灭。

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