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11. 发明授权

US6084446A Power on reset circuit 失效
标题翻译：上电复位电路
公开(公告)号：US6084446A
公开(公告)日：2000-07-04
申请号：US101679
申请日：1998-06-12
申请人： Han-Sung Chen , Tzeng-Huei Shiau , Ray-Lin Wan
发明人： Han-Sung Chen , Tzeng-Huei Shiau , Ray-Lin Wan
IPC分类号： H03K3/356 , H03K17/22
CPC分类号： H03K17/223 , H03K3/356008
摘要： A circuit generates a power on reset signal in response to the changing of a supply potential across a supply node and a reference node from a power down level to a power on level. The circuit comprises a capacitor having a first terminal coupled to the supply node and a second terminal. An output driver, such as an inverter, is coupled between the supply node and the reference node. The output driver has an output coupled to the second terminal of the capacitor. An input driver comprises a circuit which drives the input of the output driver to a level which tracks changes in the supply potential. A clamp transistor, such as a n-channel MOS transistor having a lower threshold than normal transistors in the circuit, is coupled between the input of the output driver and the supply potential. The clamp transistor clamps the input of the output driver to a driver ready level which is below the trip point of the output driver when the supply potential is at a power down level. In addition, a feedback transistor is included, which has a gate coupled to the output of the output driver, a drain coupled to the input of the output driver, and a source coupled to the supply node. The feedback transistor pulls the input of the output driver to a driver off level above the trip point of the output driver.
摘要翻译： PCT No.PCT / US98 / 06255 Sec。 371日期：1998年6月12日 102（e）1998年6月12日PCT 1998年3月30日PCT PCT。公开号WO99 / 50962 日期1999年10月7日电路响应于供电节点和参考节点从断电电平变为上电电平的电源电位而产生上电复位信号。电路包括具有耦合到电源节点的第一端子和第二端子的电容器。诸如逆变器的输出驱动器耦合在供电节点和参考节点之间。输出驱动器具有耦合到电容器的第二端子的输出。输入驱动器包括将输出驱动器的输入驱动到跟踪电源电位变化的电平的电路。钳位晶体管，例如具有比电路中的正常晶体管低的阈值的n沟道MOS晶体管，耦合在输出驱动器的输入端和电源电位之间。当供电电位处于断电电平时，钳位晶体管将输出驱动器的输入钳位到驱动器就绪电平，该电平低于输出驱动器的跳变点。此外，包括反馈晶体管，其具有耦合到输出驱动器的输出的栅极，耦合到输出驱动器的输入的漏极和耦合到电源节点的源极。反馈晶体管将输出驱动器的输入端拉至高于输出驱动器跳变点的驱动器。

12. 发明授权

US5805501A Flash memory device with multiple checkpoint erase suspend logic 失效
标题翻译：闪存设备具有多个检查点清除挂起逻辑
公开(公告)号：US5805501A
公开(公告)日：1998-09-08
申请号：US718341
申请日：1996-10-03
申请人： Tzeng-Huei Shiau , Ray-Lin Wan , Weitong Chuang , Yu-Sui Lee , Kong Mou Liou
发明人： Tzeng-Huei Shiau , Ray-Lin Wan , Weitong Chuang , Yu-Sui Lee , Kong Mou Liou
IPC分类号： G11C16/16 , G11C16/04
CPC分类号： G11C16/16 , G11C2216/20
摘要： A flash memory device includes a multiple checkpoint erase suspend algorithm. A user may issue an erase suspend command at anytime during an erase process. The erase procedure is suspended as fast as possible by allowing the erase procedure to be suspended at the first to occur of a plurality of checkpoints in the process. The block erase procedure includes a precondition phase (also called a pre-programming phase), in which a selected block is pre-programmed by applying a program potential, and then the pre-programming of the block is verified on a byte-by-byte basis. After the precondition phase, an erase phase is executed in which the selected block is erased by applying an erase potential to the block, and then verifying the erasing of the block. Erase suspend logic is coupled to the erase logic and executes an erase suspend procedure which interrupts the block erase procedure after receiving the erase suspend command during the first to occur of a set of checkpoints in the block erase procedure. The set of checkpoints comprises a first checkpoint enabling the interrupting during the precondition phase, a second checkpoint enabling the interrupting during the application of the erase potential, a third checkpoint enabling the interrupting during the verifying of the erasing step, a fourth checkpoint between the precondition phase and the erase phase, and a fifth checkpoint after the erase pulse and before verifying the erase of the block. After interrupting the block erase procedure, the erase suspend procedure includes returning to the block erase procedure to complete the block erase.
摘要翻译： PCT No.PCT / US96 / 07491 Sec。 371日期：1996年10月3日 102（e）日期1996年10月3日PCT 1996年5月22日PCT公布。 WO97 / 44792 PCT出版物日期1997年11月27日闪存器件包括多重检查点擦除挂起算法。用户可以在擦除过程中随时发出擦除挂起命令。擦除过程通过允许在该过程中首先发生多个检查点的第一次暂停，尽可能快地暂停该擦除过程。块擦除过程包括预处理阶段（也称为预编程阶段），其中通过应用程序电位对所选择的块进行预编程，然后对块的预编程在逐字节校验上进行验证，字节基础。在预处理阶段之后，执行擦除阶段，通过向块施加擦除电位，然后验证块的擦除，擦除所选择的块。擦除暂停逻辑被耦合到擦除逻辑，并且执行擦除暂停过程，该擦除暂停过程在块擦除过程中的一组检查点的第一次发生之后接收到擦除暂停命令之后中断块擦除过程。所述检查点集合包括能够在预处理阶段期间进行中断的第一检查点，在施加擦除电位期间能够中断的第二检查点，在擦除步骤的验证期间能够中断的第三检查点，前提条件之间的第四检查点相位和擦除相位，以及擦除脉冲后的第五个检查点，并且在验证块的擦除之前。在中断块擦除过程之后，擦除暂停过程包括返回到块擦除过程以完成块擦除。

13. 发明授权

US5745410A Method and system for soft programming algorithm 失效
标题翻译：软编程算法的方法与系统
公开(公告)号：US5745410A
公开(公告)日：1998-04-28
申请号：US619485
申请日：1996-03-21
申请人： Tom Dang-Hsing Yiu , Fuchia Shone , I-Long Lee , Chia-Shing Chen , Hun-Song Chen , Yuan-Chang Liu , Tzeng-Huei Shiau , Kuen-Long Chang , Ray-Lin Wan
发明人： Tom Dang-Hsing Yiu , Fuchia Shone , I-Long Lee , Chia-Shing Chen , Hun-Song Chen , Yuan-Chang Liu , Tzeng-Huei Shiau , Kuen-Long Chang , Ray-Lin Wan
IPC分类号： G11C11/40
CPC分类号： G11C11/40
摘要： A floating gate memory device which includes control circuits to generate a repair pulse to repair over-erased cells so they may be repaired block-by-block. This invention includes repairing the cells by applying a repair pulse to the cell's bit line while maintaining the word line voltage above ground. In a different embodiment, the word line voltage is maintained at two different voltage levels above ground. In the first stage, the word line voltage is maintained between approximately 0.1 volts and 0.2 volts for approximately 100 ms while the repair pulse is applied. In the second stage, the word line voltage is maintained between approximately 0.4 volts and 0.5 volts for approximately 100 ms while the repair pulse is applied.
摘要翻译： PCT No.PCT / US95 / 15051 Sec。 371日期1996年3月21日 102（e）1996年3月21日PCT 1995年11月17日PCT PCT。第WO97 / 19452号公报日期1997年5月29日一种浮动栅极存储器件，其包括产生修复脉冲以修复过擦除的单元的控制电路，使得它们可以逐块修复。本发明包括通过在维持字线电压高于地面的同时将修复脉冲施加到单元的位线来修复单元。在不同的实施例中，字线电压保持在地面以上两个不同的电压电平。在第一阶段，当施加修复脉冲时，字线电压保持在大约0.1伏和0.2伏之间大约100毫秒。在第二阶段，当施加修复脉冲时，字线电压保持在大约0.4伏和0.5伏之间大约100毫秒。

14. 发明授权

US06219290B1 Memory cell sense amplifier 有权
标题翻译：存储单元读出放大器
公开(公告)号：US06219290B1
公开(公告)日：2001-04-17
申请号：US09172274
申请日：1998-10-14
申请人： Kuen-Long Chang , Chun-Hsiung Hung , Ken-Hui Chen , I-Long Lee , Yin-Shang Liu , Ray-Lin Wan
发明人： Kuen-Long Chang , Chun-Hsiung Hung , Ken-Hui Chen , I-Long Lee , Yin-Shang Liu , Ray-Lin Wan
IPC分类号： G11C702
CPC分类号： G11C7/062 , G11C7/067 , G11C7/12 , G11C16/28
摘要： A sensing circuit for sensing the logic state of a memory cell which minimizes read times is described which includes a first circuit branch corresponding to an array circuit path and a second circuit branch corresponding to a reference cell circuit path. In operation during the pre-decode interval, additional load and current generation circuitry are enabled in the first circuit path so that the voltage as seen by the sensing input of a sensing circuit comparator is driven to be essentially equivalent to that of the reference signal as established by the reference cell circuit path on the reference input of the sensing circuit comparator. Once the address has been decoded, the additional load circuitry is disabled so as to allow the sensing input of the comparator to transition to a voltage representative of the logic state stored in the memory cell.
摘要翻译：描述了用于感测最小化读取时间的存储单元的逻辑状态的感测电路，其包括对应于阵列电路路径的第一电路支路和对应于参考单元电路路径的第二电路支路。在预解码间隔期间的操作中，在第一电路路径中启用额外的负载和电流产生电路，使得感测电路比较器的感测输入所看到的电压被驱动为基本上等于参考信号的电压，如由参考单元电路路径建立在感测电路比较器的参考输入端上。一旦解码了地址，则禁用附加负载电路，以便允许比较器的感测输入转换到代表存储在存储单元中的逻辑状态的电压。

15. 发明授权

US06255900B1 Rapid on chip voltage generation for low power integrated circuits 有权
标题翻译：用于低功率集成电路的快速片上电压产生
公开(公告)号：US06255900B1
公开(公告)日：2001-07-03
申请号：US09284435
申请日：1999-04-12
申请人： Kuen-Long Chang , Chun-Hsiung Hung , Ken-Hui Chen , Tien-Shin Ho , I-Long Lee , Tzeng-Hei Shiau , Ray-Lin Wan
发明人： Kuen-Long Chang , Chun-Hsiung Hung , Ken-Hui Chen , Tien-Shin Ho , I-Long Lee , Tzeng-Hei Shiau , Ray-Lin Wan
IPC分类号： G05F110
CPC分类号： G11C16/30 , G05F3/242 , G11C5/145 , G11C16/08 , H02M3/07
摘要： An on chip voltage generation circuit is provided suitable for use on integrated circuits such as flash memory devices with a low power supply voltage (e.g., 2.7 to 3.6 volts). A voltage boost circuit is coupled to the supply voltage input and to a boost signal, which boosts the on-chip voltage at a node on the integrated circuit in response to a transition of the boost signal. The voltage boost circuit has a first mode which in response to the transition boosts the on-chip voltage at a first rate of boosting until a first threshold, and a second mode which in response to the transition boosts the on-chip voltage at a second rate of boosting until a second threshold. The second rate of boosting in the preferred system is slower than the first rate of boosting. A detection circuit is coupled to the node on the integrated circuit which receives the on-chip voltage, and to the voltage boost circuit. The detection circuit signals the voltage boost circuit when the node reaches the first threshold, and signals the voltage boost circuit when the node reaches the second threshold. According to one aspect of the invention, the first threshold is reached within less than 5 nanoseconds, and more preferably about 2 nanoseconds, or less, of the transition in the boost signal.
摘要翻译：提供了适用于具有低电源电压（例如，2.7至3.6伏特）的闪存器件的集成电路的片上电压产生电路。电压升压电路耦合到电源电压输入和升压信号，该升压信号响应于升压信号的转变而升高集成电路上的节点上的片内电压。升压电路具有第一模式，其响应于转换而以第一升压速率提升片上电压直到第一阈值，并且响应于转换的第二模式将片上电压提升到第二阈值升压速率直到第二个阈值。优选系统中的第二次升压速度比第一次升压速率慢。检测电路耦合到接收片上电压的集成电路上的节点和电压升压电路。当节点达到第一阈值时，检测电路向升压电路发信号，当节点达到第二阈值时，信号通知升压电路。根据本发明的一个方面，在升压信号中的转变的小于5纳秒，更优选约2纳秒或更小的范围内达到第一阈值。

16. 发明授权

US6021069A Bit latch scheme for parallel program verify in floating gate memory device 有权
标题翻译：用于在浮动栅极存储器件中并行程序验证的位锁存方案
公开(公告)号：US6021069A
公开(公告)日：2000-02-01
申请号：US160637
申请日：1998-09-24
申请人： Chun-Hsiung Hung , Ray-Lin Wan
发明人： Chun-Hsiung Hung , Ray-Lin Wan
IPC分类号： G11C16/06
CPC分类号： G11C16/3454
摘要： A method for determining successful programming of a set of memory cells in an array of floating gate memory cells including bit lines coupled with corresponding columns of cells in the array, word lines coupled with corresponding rows of cells in the array, and bit latches coupled to the respective bit lines. The method includes applying a word line voltage to a word line across which memory cells in the set of memory cells are accessible. A potential applied to memory cells in the set of memory cells is raised. A current load is caused from the bit line. Changes in respective voltage levels of bit lines in the set of bit lines are responded to in parallel to store a constant in bit latches in the set of bit latches coupled to bit lines on which the respective voltage levels pass a determinate threshold during the step of applying a word line voltage. An integrated circuit memory is described. The memory includes a device, connected to a bit line and ground, for selectively causing a current flow from the bit line at least before loading a constant into the memory element.
摘要翻译：一种用于确定浮动栅极存储器单元阵列中的一组存储器单元的成功编程的方法，包括与阵列中的相应列的单元阵列耦合的位线，与阵列中的相应的单元行耦合的字线以及耦合到相应的位线。该方法包括将字线电压施加到存储器单元集合中的存储器单元可访问的字线。提高了应用于该组存储器单元中的存储器单元的电位。从位线引起电流负载。位线组中的位线的各个电压电平的变化被并行地响应以存储耦合到位线的位锁存器中的位锁存器中的常数，其中相应的电压电平在其中的各个电压电平通过了确定的阈值应用字线电压。描述集成电路存储器。存储器包括连接到位线和地的器件，用于至少在将常数加载到存储器元件之前选择性地引起来自位线的电流。

17. 发明授权

US06573780B2 Four-phase charge pump with lower peak current 有权
标题翻译：具有较低峰值电流的四相电荷泵
公开(公告)号：US06573780B2
公开(公告)日：2003-06-03
申请号：US09355654
申请日：1999-08-02
申请人： Yu Shen Lin , Chun-Hsiung Hung , Ray-Lin Wan
发明人： Yu Shen Lin , Chun-Hsiung Hung , Ray-Lin Wan
IPC分类号： G05F110
CPC分类号： H02M3/073 , H02M2003/075
摘要： A four-phase charge pump circuit suitable for use on integrated circuits, such as flash memory devices, includes circuitry that drives charge pump nodes in two components separated by a time delay. The two components can be triggered by edges from the clocks that control the timing of the charge pump. Driving the charge pump nodes in two components separated by a delay decreases the peak current of the charge pump and improves noise characteristics of a voltage supply or ground line connected to the charge pump.
摘要翻译：适用于集成电路（例如闪存器件）的四相电荷泵电路包括驱动由时间延迟分开的两个部件中的电荷泵节点的电路。这两个组件可以由控制电荷泵定时的时钟边沿触发。驱动由延迟分开的两个部件中的电荷泵节点会降低电荷泵的峰值电流，并改善连接到电荷泵的电源或接地线的噪声特性。

18. 发明授权

US6100557A Triple well charge pump 失效
标题翻译：三重充电泵
公开(公告)号：US6100557A
公开(公告)日：2000-08-08
申请号：US849561
申请日：1997-05-12
申请人： Chun-Hsiung Hung , Ray-Lin Wan , Yao-Wu Cheng
发明人： Chun-Hsiung Hung , Ray-Lin Wan , Yao-Wu Cheng
IPC分类号： H01L27/02 , H02M3/07 , H01L29/72
CPC分类号： H01L27/0222 , H02M3/073
摘要： An improved charge pump design is disclosed. This charge pump comprises at least one pumping transistor having a triple well arrangement. This triple pump transistor has a source and a drain region of a first conductive type formed on a first well having an opposite conductive type. A second well having the first conductive type is formed outside of the first well. The source region, first well and second well are set to substantially the same potential. One aspect of this configuration is that the first well forms a semiconductor diode with the drain region. Another aspect of this arrangement is that the body effect of the transistor is reduced. The reduction in body effect reduces the threshold voltage of the transistor. It is found that the above mentioned diode and threshold voltage reduction, singly and in combination, allow the charge pump to operate more efficiently.
摘要翻译： PCT No.PCT / US96 / 16317 Sec。 371日期：1997年5月12日 102（e）日期1997年5月12日PCT提交1996年10月10日PCT公布。公开号WO98 / 16010 PCT 日期：1998年4月16日公开了改进的电荷泵设计。该电荷泵包括具有三阱布置的至少一个泵浦晶体管。该三重泵晶体管具有形成在具有相反导电类型的第一阱上的第一导电类型的源区和漏区。具有第一导电类型的第二阱形成在第一阱的外部。源区，第一阱和第二阱被设定为基本上相同的电位。该结构的一个方面是第一阱与漏极区形成半导体二极管。这种布置的另一方面是晶体管的体效减小。身体效应的降低降低了晶体管的阈值电压。发现上述二极管和阈值电压降低，单独并且组合地允许电荷泵更有效地操作。

19. 发明授权

US5875152A Address transition detection circuit for a semiconductor memory capable of detecting narrowly spaced address changes 失效
标题翻译：用于能够检测窄间隔地址变化的半导体存储器的地址转换检测电路
公开(公告)号：US5875152A
公开(公告)日：1999-02-23
申请号：US751513
申请日：1996-11-15
申请人： Yin-Shang Liu , Kuen-Long Chang , Chun-Hsiung Hung , Weitong Chuang , Ray-Lin Wan
发明人： Yin-Shang Liu , Kuen-Long Chang , Chun-Hsiung Hung , Weitong Chuang , Ray-Lin Wan
IPC分类号： G11C11/41 , G11C7/22 , G11C8/18 , H03K5/1534 , G11C8/00 , H03K5/22
CPC分类号： H03K5/1534 , G11C7/22 , G11C8/18
摘要： The present invention provides a new (ATD) address transition detection circuit for use on an address bus having any number of address lines. An ATD circuit is disclosed which comprises a first and second circuit and an interval timer. The first circuit has a first and second input and an output. The first circuit receives, at the first input, a change signal corresponding to transitions in one or more addresses of an address bus. In response, the output of the first circuit transitions from an initial first state to a second state. The first circuit is also responsive to a reset command at the second input to return the output to the first state. The interval timer has an output coupled to the second input of the first circuit and an input. The interval timer responsive to an initialize command at the input initiates a timed interval and after the timed interval generates the reset command at the output. The second circuit has an output coupled to the input of the interval timer and an input. The second circuit responsive to the change signal at the input generates an initialize command at the output. The circuit provides a second state at the output of the first circuit, for all including the last received in a series of change signals. This assures that all address transitions have been detected before a memory access is allowed.
摘要翻译：本发明提供一种新的（ATD）地址转换检测电路，用于具有任意数量的地址线的地址总线。公开了一种包括第一和第二电路和间隔定时器的ATD电路。第一电路具有第一和第二输入和输出。第一电路在第一输入端接收对应于地址总线的一个或多个地址中的转变的改变信号。作为响应，第一电路的输出从初始第一状态转变到第二状态。第一电路还响应于第二输入端的复位命令将输出返回到第一状态。间隔定时器具有耦合到第一电路的第二输入和输入的输出。响应于输入的初始化命令的间隔定时器启动定时间隔，并且在定时间隔之后在输出端产生复位命令。第二电路具有耦合到间隔定时器和输入的输入的输出。响应于输入端的变化信号的第二电路在输出端产生初始化命令。该电路在第一电路的输出处提供第二状态，包括在一系列变化信号中最后接收的信号。这确保在允许存储器访问之前已经检测到所有地址转换。

20. 发明授权

US06493276B2 Word line boost circuit 有权
标题翻译：字线升压电路
公开(公告)号：US06493276B2
公开(公告)日：2002-12-10
申请号：US09355653
申请日：1999-08-02
申请人： Yu Shen Lin , Chun-Hsiung Hung , Ray-Lin Wan
发明人： Yu Shen Lin , Chun-Hsiung Hung , Ray-Lin Wan
IPC分类号： G11C700
CPC分类号： G11C8/08 , G11C5/145
摘要： An improved word line boost circuit suitable for use on integrated circuits such as flash memory devices includes a two step boosting circuit with a floating circuit node. A first circuit provides an initial boost of the output voltage from a precharged voltage. Part of the first circuit is floated, lessening a load on a second circuit. Then, the second circuit provides a second boost of the output voltage with increased power efficiency. A time delay separates the onset of the second boosting operation from the onset of the first boosting operation so as to define a two-step boost.
摘要翻译：适用于诸如闪存器件的集成电路的改进的字线升压电路包括具有浮动电路节点的两级升压电路。第一电路从预充电电压提供输出电压的初始升压。第一个电路的一部分浮起来，减轻了第二个电路的负载。然后，第二电路以提高的功率效率提供输出电压的第二升压。时间延迟将第二升压操作的开始与第一升压操作的开始分开，以便定义两步升压。

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