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11. 发明授权

US06605536B2 Treatment of low-k dielectric films to enable patterning of deep submicron features 有权
公开(公告)号：US06605536B2
公开(公告)日：2003-08-12
申请号：US10143314
申请日：2002-05-10
申请人： Mona Eissa , Guoqiang Xing , Kenneth D. Brennan , Hyesook Hong
发明人： Mona Eissa , Guoqiang Xing , Kenneth D. Brennan , Hyesook Hong
IPC分类号： H01L2144
CPC分类号： H01L21/76826 , H01L21/31058 , H01L21/31116 , H01L21/31133 , H01L21/31138 , H01L21/76808 , H01L21/76835
摘要： Treating a low-k dielectric layer (104) using a highly oxidizing wet solution (e.g., H2SO4) to improve patterning. Resist poisoning occurs due to an interaction between low-k films (104), such as OSG, and DUV resist (130,132). The wet treatment is performed to either pre-treat a low-k dielectric (104) before forming the pattern (130,132) or during a rework of the pattern (130,132) to reduce resist poisoning.

12. 发明授权

US08637918B2 Method and device employing polysilicon scaling 有权
标题翻译：采用多晶硅结垢的方法和装置
公开(公告)号：US08637918B2
公开(公告)日：2014-01-28
申请号：US13294098
申请日：2011-11-10
申请人： Shenqing Fang , Chun Chen , Wenmei Li , Inkuk Kang , Gang Xue , Hyesook Hong
发明人： Shenqing Fang , Chun Chen , Wenmei Li , Inkuk Kang , Gang Xue , Hyesook Hong
IPC分类号： H01L29/792
CPC分类号： H01L27/11573 , H01L21/28282 , H01L27/105 , H01L27/11565 , H01L29/6659 , H01L29/66833 , H01L29/792
摘要： A memory and method of manufacture employing word line scaling. A layered stack, including a charge trapping component and a core polysilicon layer, is formed on a core section and a peripheral section of a substrate. A portion of the layered stack, including the core polysilicon layer is then removed from the peripheral section. A peripheral polysilicon layer, which is thicker than the core polysilicon layer of the layered stack, is next formed on the layered stack and the peripheral section. The layered stack is then isolated from the peripheral polysilicon layer by removing a portion of the peripheral polysilicon layer from the core section, and polysilicon lines are patterned in the isolated layered stack.
摘要翻译：使用字线缩放的存储器和制造方法。在基板的芯部分和周边部分上形成包括电荷俘获部件和芯多晶硅层的分层堆叠。然后从周边部分去除包括核心多晶硅层的层叠堆叠的一部分。在分层堆叠和外围部分上形成比叠层堆叠的核心多晶硅层厚的外围多晶硅层。然后通过从核心部分去除外围多晶硅层的一部分，并且在分离的层叠堆叠中对多晶硅线进行图案化，从而从外围多晶硅层隔离层叠堆叠。

13. 发明授权

US08076199B2 Method and device employing polysilicon scaling 有权
标题翻译：采用多晶硅结垢的方法和装置
公开(公告)号：US08076199B2
公开(公告)日：2011-12-13
申请号：US12370950
申请日：2009-02-13
申请人： Shenqing Fang , Chun Chen , Wenmei Li , Inkuk Kang , Gang Xue , Hyesook Hong
发明人： Shenqing Fang , Chun Chen , Wenmei Li , Inkuk Kang , Gang Xue , Hyesook Hong
IPC分类号： H01L21/336
CPC分类号： H01L27/11573 , H01L21/28282 , H01L27/105 , H01L27/11565 , H01L29/6659 , H01L29/66833 , H01L29/792
摘要： A memory and method of manufacture employing word line scaling. A layered stack, including a charge trapping component and a core polysilicon layer, is formed on a core section and a peripheral section of a substrate. A portion of the layered stack, including the core polysilicon layer is then removed from the peripheral section. A peripheral polysilicon layer, which is thicker than the core polysilicon layer of the layered stack, is next formed on the layered stack and the peripheral section. The layered stack is then isolated from the peripheral polysilicon layer by removing a portion of the peripheral polysilicon layer from the core section, and polysilicon lines are patterned in the isolated layered stack.
摘要翻译：使用字线缩放的存储器和制造方法。在基板的芯部分和周边部分上形成包括电荷俘获部件和芯多晶硅层的分层堆叠。然后从周边部分去除包括核心多晶硅层的层叠堆叠的一部分。在分层堆叠和外围部分上形成比叠层堆叠的核心多晶硅层厚的外围多晶硅层。然后通过从核心部分去除外围多晶硅层的一部分，并且在分离的层叠堆叠中对多晶硅线进行图案化，从而从外围多晶硅层隔离层叠堆叠。

14. 发明申请

US20080242072A1 PLASMA DRY ETCH PROCESS FOR METAL-CONTAINING GATES 审中-公开
标题翻译：用于含金属盖的等离子体干蚀刻工艺
公开(公告)号：US20080242072A1
公开(公告)日：2008-10-02
申请号：US11691114
申请日：2007-03-26
申请人： Jinhan Choi , Hyesook Hong , Donald S. Miles
发明人： Jinhan Choi , Hyesook Hong , Donald S. Miles
IPC分类号： H01L21/3205 , H01L21/4763 , H01L21/461
CPC分类号： H01L21/32136 , H01L21/28079 , H01L21/28088 , H01L21/32137 , H01L29/495 , H01L29/4966
摘要： A method of manufacturing a semiconductor device. The method comprises forming a gate stack layer. The gate stack has an insulating layer on a substrate, a metal-containing layer on the insulating layer, a metal nitride barrier layer on the metal-containing layer, and a silicon-containing layer on the metal nitride barrier layer. The method also comprises patterning the gate stack layer. Pattering includes a plasma etch of the metal nitride barrier layer. The plasma etch has a chloride-containing feed gas and a physical etch component. The physical etch component includes a high-mass species having a molecular weight of greater than about 71 gm/mol.
摘要翻译：一种制造半导体器件的方法。该方法包括形成栅堆叠层。栅堆叠在衬底上具有绝缘层，绝缘层上的含金属层，金属含有层上的金属氮化物阻挡层和金属氮化物阻挡层上的含硅层。该方法还包括图案化栅极堆叠层。溅射包括金属氮化物阻挡层的等离子体蚀刻。等离子体蚀刻具有含氯化物的进料气体和物理蚀刻部件。物理蚀刻组分包括分子量大于约71gm / mol的高质量物质。

15. 发明申请

US20070066007A1 Method to obtain fully silicided gate electrodes 有权
标题翻译：获得完全硅化栅电极的方法
公开(公告)号：US20070066007A1
公开(公告)日：2007-03-22
申请号：US11228902
申请日：2005-09-16
申请人： Steven Vitale , Hyesook Hong , Freidoon Mehrad
发明人： Steven Vitale , Hyesook Hong , Freidoon Mehrad
IPC分类号： H01L21/8238
CPC分类号： H01L21/823425 , H01L21/823443 , H01L21/823835
摘要： The present invention provides a method of fabricating a microelectronics device. In one aspect, the method comprises depositing a protective layer (510) over a spacer material (415) located over gate electrodes (250) and a doped region (255) located between the gate electrodes (250), removing a portion of the spacer material (415) and the protective layer (510) located over the gate electrodes (250). A remaining portion of the spacer material (415) remains over the top surface of the gate electrodes (250) and over the doped region (255), and a portion of the protective layer (510) remains over the doped region (255). The method further comprises removing the remaining portion of the spacer material (415) to form spacer sidewalls on the gate electrodes (250), expose the top surface of the gate electrodes (250), and leave a remnant of the spacer material (415) over the doped region (255). Source/drains are formed adjacent the gate electrodes 250 and through the remnant of the spacer material (415), and a metal is incorporated into the gate electrodes (250).
摘要翻译：本发明提供一种制造微电子器件的方法。在一个方面，该方法包括在位于栅电极（250）之间的间隔材料（415）和位于栅电极（250）之间的掺杂区域（255）之间沉积保护层（510），去除间隔物的一部分材料（415）和位于栅电极（250）上方的保护层（510）。间隔材料（415）的剩余部分保留在栅电极（250）的顶表面上方并且在掺杂区域（255）之上，并且保护层（510）的一部分保留在掺杂区域（255）上方。该方法还包括去除间隔物材料（415）的剩余部分以在栅电极（250）上形成间隔壁侧壁，露出栅电极（250）的顶表面，并留下间隔物材料（415）的残留物在掺杂区域（255）上。源极/漏极形成在栅电极250附近并且通过间隔物材料（415）的残留物，并且金属被结合到栅电极（250）中。

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