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11. 发明申请

US20050054332A1 Information gathering robot 有权
标题翻译：信息采集机器人
公开(公告)号：US20050054332A1
公开(公告)日：2005-03-10
申请号：US10915535
申请日：2004-08-11
申请人： Yoshiaki Sakagami , Yoko Saito , Koji Kawabe , Takamichi Shimada , Nobuo Higaki
发明人： Yoshiaki Sakagami , Yoko Saito , Koji Kawabe , Takamichi Shimada , Nobuo Higaki
IPC分类号： G06F19/00 , G05D1/02 , G06F1/00 , H04L29/08 , H04W4/02 , H04Q7/20
CPC分类号： H04W4/02 , G05D1/0246 , G05D1/0274 , G05D2201/0207 , H04L67/12
摘要： In an event site or the like, a visitor may waste time and effort trying to find a spot where an event of interest may be taking place because the visitor is unable to look through the entire site from any particular spot. An information gathering robot roams in such an event site typically along a prescribed route, and notes spots of interest to transmit this information to a data server. The visitor can access the data server to find a spot of interest of his or her choice substantially on a real time basis.
摘要翻译：在事件现场等中，访客可能会浪费时间和精力去尝试寻找可能发生的兴趣事件的地点，因为访问者无法从任何特定的地点查看整个站点。信息收集机器人通常沿着规定的路线在这样的事件站点中漫游，并且记录将该信息发送到数据服务器的感兴趣点。访问者可以访问数据服务器，实质上基于实时地查找他或她选择的兴趣点。

12. 发明授权

US06397319B1 Process for executing highly efficient VLIW 有权
标题翻译：执行高效率VLIW的过程
公开(公告)号：US06397319B1
公开(公告)日：2002-05-28
申请号：US09598397
申请日：2000-06-20
申请人： Shuichi Takayama , Nobuo Higaki
发明人： Shuichi Takayama , Nobuo Higaki
IPC分类号： G06F930
CPC分类号： G06F9/3822 , G06F9/30145 , G06F9/30149 , G06F9/30163 , G06F9/30167 , G06F9/30181 , G06F9/383 , G06F9/3853
摘要： A 32-bit instruction 50 is composed of a 4-bit format field 51, a 4-bit operation field 52, and two 12-bit operation fields 59 and 60. The 4-bit operation field 52 can only include (1) an operation code “cc” that indicates a branch operation which uses a stored value of the implicitly indicated constant register 36 as the branch address, or (2) a constant “const”. The content of the 4-bit operation field 52 is specified by a format code provided in the format field 51.
摘要翻译： 32位指令50由4位格式字段51，4位操作字段52和2位12位操作字段59和60组成.4位操作字段52只能包括（1）指示使用隐含指示的常数寄存器36的存储值作为分支地址的分支操作的操作代码“cc”，或者（2）常数“const”。 4位操作字段52的内容由格式字段51中提供的格式代码指定。

13. 发明授权

US6161171A Apparatus for pipelining sequential instructions in synchronism with an operation clock 失效
标题翻译：用于与操作时钟同步地进行顺序指令的装置
公开(公告)号：US6161171A
公开(公告)日：2000-12-12
申请号：US105212
申请日：1998-06-26
申请人： Toru Morikawa , Nobuo Higaki , Shinji Ozaki , Keisuke Kaneko , Satoshi Ogura , Masato Suzuki
发明人： Toru Morikawa , Nobuo Higaki , Shinji Ozaki , Keisuke Kaneko , Satoshi Ogura , Masato Suzuki
IPC分类号： G06F9/38 , G06F12/08 , G06F13/00
CPC分类号： G06F9/3867 , G06F12/0855
摘要： A first instruction requiring that a data word should be read out from a data memory and be stored in a certain register in a register set, and then a second instruction requiring that two operands, respectively read out from the register and another register in the register set, should be added are pipeline-processed. In a high-speed mode in which an operation clock having a higher frequency is supplied, a data cache intervened between an instruction execution circuit and the data memory is controlled to supply a data word to a WB (write back) stage of the instruction execution circuit within two cycles with respect to an input address associated with the first instruction. In order to execute the second instruction, the data word is supplied from the WB stage to an EX (operation execution) stage of the instruction execution circuit. In a low-speed mode in which an operation clock having a lower frequency is supplied, the data cache is controlled to supply a data word to an MEM (memory access) stage of the instruction execution circuit within one cycle with respect to an input address associated with the first instruction. In order to execute the second instruction, the data word is bypassed from the MEM stage to the EX stage.
摘要翻译：需要从数据存储器中读取数据字并将其存储在寄存器组中的特定寄存器中的第一条指令，然后需要分别从寄存器读出的两个操作数和寄存器中的另一个寄存器的第二条指令设置，应加入管道处理。在提供具有较高频率的操作时钟的高速模式中，控制指令执行电路和数据存储器之间的数据高速缓冲存储器，以将数据字提供给指令执行的WB（回写）级电路相对于与第一指令相关联的输入地址在两个周期内。为了执行第二指令，数据字从WB级提供给指令执行电路的EX（操作执行）级。在提供具有较低频率的操作时钟的低速模式中，控制数据高速缓冲存储器以相对于输入地址的一个周期内将数据字提供给指令执行电路的MEM（存储器访问）级与第一条指令相关联。为了执行第二条指令，将数据字从MEM级旁路到EX级。

14. 发明授权

US5928358A Information processing apparatus which accurately predicts whether a branch is taken for a conditional branch instruction, using small-scale hardware 失效
标题翻译：使用小规模硬件来准确地预测分支是否用于条件分支指令的信息处理装置
公开(公告)号：US5928358A
公开(公告)日：1999-07-27
申请号：US987260
申请日：1997-12-09
申请人： Shuichi Takayama , Nobuo Higaki
发明人： Shuichi Takayama , Nobuo Higaki
IPC分类号： G06F9/38 , G06F9/40
CPC分类号： G06F9/3844
摘要： A branch instruction includes a set of branch prediction information 13b and a set of branch history information 13c. The set of branch prediction information 13b is made up of 1 bit which predicts whether a branch will be performed during the next execution of the instruction. The set of branch history information 13c is made up of 2 bits showing a frequency, with which the branch has been taken, is "very high", "high", "low" or "very low". An instruction fetching unit 12 prefetches an instruction from a cache memory 11a in accordance with the set of branch prediction information 13b. After an instruction executing unit 15 completes an execution of the branch instruction, a branch history information generating unit 16 generates a new set of branch history information and a branch prediction information generating unit 17 generates a new set of branch prediction information, in accordance with the execution result and the preceding branch history information 13c. A branch instruction updating unit 18 overwrites the generated set of branch history information and the generated set of branch prediction information on the corresponding branch instruction stored in the main memory 11a.
摘要翻译：分支指令包括一组分支预测信息13b和一组分支历史信息13c。分支预测信息组13b由1比特组成，该比特预测在下一次执行指令期间是否执行分支。分支历史信息13c由2比特构成，分支被采用的频率为“非常高”，“高”，“低”或“非常低”。指令取出单元12根据分支预测信息组13b预取来自高速缓存存储器11a的指令。在指令执行单元15完成分支指令的执行之后，分支历史信息生成单元16生成一组新的分支历史信息，并且分支预测信息生成单元17根据该分支预测信息生成单元17生成一组新的分支预测信息执行结果和前一分支历史信息13c。分支指令更新单元18对存储在主存储器11a中的相应分支指令重写所生成的分支历史信息和所生成的分支预测信息组。

15. 发明授权

US5481679A Data processing apparatus having bus switches for selectively connecting buses to improve data throughput 失效
标题翻译：具有用于选择性地连接总线以提高数据吞吐量的总线开关的数据处理装置
公开(公告)号：US5481679A
公开(公告)日：1996-01-02
申请号：US121799
申请日：1993-09-15
申请人： Nobuo Higaki , Toshimichi Matsuzaki
发明人： Nobuo Higaki , Toshimichi Matsuzaki
IPC分类号： G06F13/36 , G06F13/28 , G06F13/40 , G06F15/78 , G06F13/00 , G06F13/42
CPC分类号： G06F13/4027 , G06F13/28 , G06F15/7817
摘要： A data processing apparatus is described, including a first bus connecting an instruction storage unit and an instruction preparation unit, a second bus connecting an instruction execution unit and a data storage unit, a bus switch selectively connecting and disconnecting the first and second buses electrically, and a control unit controlling the operation of the bus switch responding to the operations of the instruction preparation unit and the instruction execution unit. When the first and second buses are connected by the bus switch, access from the instruction preparation unit to the data storage unit and access from the instruction execution unit to the instruction storage unit can be performed. On the other hand when the buses are not connected, instruction fetch from the instruction preparation unit and data access from the instruction execution unit can be concurrently performed. Hence, data throughput on the buses can be improved and the load capacity can be reduced, which leads to heightening of the clock frequency.
摘要翻译：描述了一种数据处理装置，包括连接指令存储单元和指令准备单元的第一总线，连接指令执行单元和数据存储单元的第二总线，总线选择性地电连接和断开第一和第二总线，以及控制单元，其响应于指令准备单元和指令执行单元的操作来控制总线开关的操作。当通过总线开关连接第一和第二总线时，可以执行从指令准备单元到数据存储单元的访问以及从指令执行单元到指令存储单元的访问。另一方面，当总线未连接时，可以同时执行从指令准备单元的指令和来自指令执行单元的数据访问。因此，可以提高总线上的数据吞吐量，并且可以减小负载能力，从而导致时钟频率的提高。

16. 再颁专利

USRE43729E1 Processor which can favorably execute a rounding process composed of positive conversion and saturated calculation processing 有权
标题翻译：可以有利地执行由正转换和饱和计算处理组成的舍入处理的处理器
公开(公告)号：USRE43729E1
公开(公告)日：2012-10-09
申请号：US13092453
申请日：2011-04-22
申请人： Toru Morikawa , Nobuo Higaki , Akira Miyoshi , Keizo Sumida
发明人： Toru Morikawa , Nobuo Higaki , Akira Miyoshi , Keizo Sumida
IPC分类号： G06F9/302
摘要： A processor which executes positive conversion processing, which converts coded data into uncoded data, and saturation calculation processing, which rounds a value to an appropriate number of bits, at high speed. When a positive conversion saturation calculation instruction “MCSST D1” is decoded, the sum-product result register 6 outputs its held value to the path P1. The comparator 22 compares the magnitude of the held value of the sum-product result register 6 with the coded 32-bit integer “0x0000_00FF”. The polarity judging unit 23 judges whether the eighth bit of the value held by the sum-product result register 6 is “ON”. The multiplexer 24 outputs one of the maximum value “0x0000_00FF” generated by the constant generator 21, the zero value “0x0000_0000” generated by the zero generator 25, and the held value of the sum-product result register 6 to the data bus 18.
摘要翻译：执行正转换处理的处理器，其将编码数据转换为未编码数据，以及饱和度计算处理，其以高速将值舍入到适当位数。当正转换饱和度计算指令MCSST D1被解码时，积和结果寄存器6将其保持值输出到路径P1。比较器22将和积结果寄存器6的保持值的大小与编码的32位整数0x0000_00FF进行比较。极性判定单元23判断由积分结果寄存器6保持的值的第八位是否为ON。复用器24输出由常数发生器21产生的最大值0x0000_00FF，由零发生器25产生的零值0x0000_0000和和积结果寄存器6的保持值到数据总线18之一。

17. 发明授权

US07930520B2 Processor and program execution method capable of efficient program execution 有权
公开(公告)号：US07930520B2
公开(公告)日：2011-04-19
申请号：US12110539
申请日：2008-04-28
申请人： Kazushi Kurata , Tetsuya Tanaka , Nobuo Higaki , Kunihiko Hayashi , Hiroshi Kadota , Tokuzo Kiyohara , Kozo Kimura , Hideshi Nishida , Kazuya Furukawa , Shigeki Fujii , Toshio Sugimura
发明人： Kazushi Kurata , Tetsuya Tanaka , Nobuo Higaki , Kunihiko Hayashi , Hiroshi Kadota , Tokuzo Kiyohara , Kozo Kimura , Hideshi Nishida , Kazuya Furukawa , Shigeki Fujii , Toshio Sugimura
IPC分类号： G06F9/30 , G06F9/44 , G06F1/32
CPC分类号： G06F9/4881 , G06F9/3851 , G06F9/3867 , G06F9/462
摘要： A processor for sequentially executing a plurality of programs using a plurality of register value groups stored in a memory that correspond one-to-one with the programs. The processor includes a plurality of register groups; a select/switch unit operable to select one of the plurality of register groups as an execution target register group on which a program execution is based, and to switch the selection target every time a first predetermined period elapses; a restoring unit operable to restore, every time the switching is performed, one of the register value groups into one of the register groups that is not selected as the execution target register group; a saving unit operable to save, prior to the restoring, register values in the register group targeted for restoring, by overwriting a register value group in the memory that corresponds to the register values; and a program execution unit operable to execute, every time the switching is performed, a program corresponding to a register value group in the execution target register group.

18. 发明申请

US20100180095A1 BUFFER CONTROL DEVICE AND BUFFER MEMORY DEVICE 审中-公开
标题翻译：缓冲器控制器件和缓冲器存储器件
公开(公告)号：US20100180095A1
公开(公告)日：2010-07-15
申请号：US12095610
申请日：2006-11-28
申请人： Masanori Fujibayashi , Nobuo Higaki , Kazushi Kurata , Tomoko Matsui
发明人： Masanori Fujibayashi , Nobuo Higaki , Kazushi Kurata , Tomoko Matsui
IPC分类号： G06F12/14
CPC分类号： G06F5/14 , G06F2205/062
摘要： The buffer control device of this invention includes: a pointer holding unit which holds a virtual pointer different from a read pointer and a write pointer; an access control unit that controls an access to a ring buffer; a judging unit that judges whether or not one of the read pointer and the write pointer has reached an address substantially identical to an address indicated by the virtual pointer; and disabling unit that disables a normal access using the one of the read pointer and the write pointer, when the judging unit judges that the one of the read pointer and the write pointer has reached the address substantially identical to the address indicated by the virtual pointer, the normal access being controlled by the access control unit, wherein the access control unit further controls a reaccess to the ring buffer.
摘要翻译：本发明的缓冲器控制装置包括：保持与读指针不同的虚拟指针和写指针的指针保持单元; 访问控制单元，其控制对环形缓冲器的访问; 判断单元，判断读指针和写指针之一是否达到与虚拟指针所指示的地址基本相同的地址; 以及禁止单元，其在所述读取指针和所述写入指针之一达到与所述虚拟指针所指示的地址基本相同的地址的情况下，使用所述读取指针和所述写入指针中的一者禁止正常访问正常访问由访问控制单元控制，其中访问控制单元进一步控制对环形缓冲器的重新访问。

19. 发明申请

US20100169614A1 PROCESSOR FOR EXECUTING HIGHLY EFFICIENT VLIW 有权
标题翻译：执行高效VLIW的处理器
公开(公告)号：US20100169614A1
公开(公告)日：2010-07-01
申请号：US12705300
申请日：2010-02-12
申请人： Shuichi TAKAYAMA , Nobuo Higaki
发明人： Shuichi TAKAYAMA , Nobuo Higaki
IPC分类号： G06F9/30 , G06F9/302
CPC分类号： G06F9/3822 , G06F9/30145 , G06F9/30149 , G06F9/30163 , G06F9/30167 , G06F9/30181 , G06F9/383 , G06F9/3853
摘要： A 32-bit instruction 50 is composed of a 4-bit format field 51, a 4-bit operation field 52, and two 12-bit operation fields 59 and 60. The 4-bit operation field 52 can only include (1) an operation code “cc” that indicates a branch operation which uses a stored value of the implicitly indicated constant register 36 as the branch address, or (2) a constant “const”. The content of the 4-bit operation field 52 is specified by a format code provided in the format field 51.
摘要翻译： 32位指令50由4位格式字段51，4位操作字段52和2位12位操作字段59和60组成.4位操作字段52只能包括（1）指示使用隐含指示的常数寄存器36的存储值作为分支地址的分支操作的操作代码“cc”，或者（2）常数“const”。 4位操作字段52的内容由格式字段51中提供的格式代码指定。

20. 发明申请

US20090063734A1 BUS CONTROLLER 审中-公开
标题翻译：总线控制器
公开(公告)号：US20090063734A1
公开(公告)日：2009-03-05
申请号：US11817094
申请日：2006-02-27
申请人： Kazushi Kurata , Nobuo Higaki
发明人： Kazushi Kurata , Nobuo Higaki
IPC分类号： G06F3/00
CPC分类号： G06F13/28 , G06F13/4059
摘要： A bus controller capable of shortening the time required before a flush is completed so as not to degrade the performance of a processor. A bus controller includes: a FIFO for temporarily holding, on a first-in first-out basis, data to be stored from a processor into a memory; a flush pointer for holding a pointer which indicates end data held by the FIFO at a time when a trigger signal is received; a memory control unit for writing a portion of the data held by the FIFO into the memory according to the trigger signal so as to partially flush the FIFO, the portion ranging from start data through end data indicated by the flush pointer; and a wait circuit for generating a wait signal for a specific access instruction, which is executed by the processor, until the memory control unit completes the partial flush.
摘要翻译：一种总线控制器，能够在完成冲洗之前缩短所需的时间，从而不降低处理器的性能。总线控制器包括：FIFO，用于将先前从处理器存储的数据暂时保存在存储器中; 用于保持指示器的刷新指针，其指示在接收到触发信号时由FIFO保持的结束数据; 存储器控制单元，用于根据触发信号将由FIFO保存的数据的一部分写入存储器，以部分地刷新FIFO，该部分从开始数据到由刷新指针指示的结束数据; 以及等待电路，用于产生由处理器执行的特定访问指令的等待信号，直到存储器控制单元完成部分刷新。

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