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11. 发明授权

US07738299B2 Erase discharge control method of nonvolatile semiconductor memory device 有权
标题翻译：擦除非易失性半导体存储器件的放电控制方法
公开(公告)号：US07738299B2
公开(公告)日：2010-06-15
申请号：US11819172
申请日：2007-06-26
申请人： Masao Kuriyama , Makoto Hirano , Hiroki Murakami , Yuichiro Nakagaki
发明人： Masao Kuriyama , Makoto Hirano , Hiroki Murakami , Yuichiro Nakagaki
IPC分类号： G11C11/34
CPC分类号： G11C16/14
摘要： According to an example embodiment, an erase discharge method may include drawing charges accumulated in a floating gate of a floating gate type field effect transistor into a semiconductor substrate to perform an erase operation by applying a first voltage to a word line, a second voltage to an N-well and a P-well, and/or opening a bit line and a ground line. The word line may be grounded, and a discharge transistor connected to the bit line may be turned on. The N-well and the P-well may be grounded to discharge charges accumulated in the N-well and P-well.
摘要翻译：根据示例实施例，擦除放电方法可以包括将浮置栅极型场效应晶体管的浮动栅极中累积的电荷绘制到半导体衬底中，以通过对字线施加第一电压来执行擦除操作，将第二电压 N阱和P阱，和/或打开位线和接地线。字线可以接地，并且连接到位线的放电晶体管可以被接通。 N阱和P阱可以被接地以放电累积在N阱和P阱中的电荷。

12. 发明申请

US20080123434A1 Erase discharge control method of nonvolatile semiconductor memory device 有权
标题翻译：擦除非易失性半导体存储器件的放电控制方法
公开(公告)号：US20080123434A1
公开(公告)日：2008-05-29
申请号：US11819172
申请日：2007-06-26
申请人： Masao Kuriyama , Makoto Hirano , Hiroki Murakami , Yuichiro Nakagaki
发明人： Masao Kuriyama , Makoto Hirano , Hiroki Murakami , Yuichiro Nakagaki
IPC分类号： G11C16/14
CPC分类号： G11C16/14
摘要： According to an example embodiment, an erase discharge method may include drawing charges accumulated in a floating gate of a floating gate type field effect transistor into a semiconductor substrate to perform an erase operation by applying a first voltage to a word line, a second voltage to an N-well and a P-well, and/or opening a bit line and a ground line. The word line may be grounded, and a discharge transistor connected to the bit line may be turned on. The N-well and the P-well may be grounded to discharge charges accumulated in the N-well and P-well.
摘要翻译：根据示例实施例，擦除放电方法可以包括将浮置栅极型场效应晶体管的浮动栅极中累积的电荷绘制到半导体衬底中，以通过对字线施加第一电压来执行擦除操作，将第二电压 N阱和P阱，和/或打开位线和接地线。字线可以接地，并且连接到位线的放电晶体管可以被接通。 N阱和P阱可以被接地以放电累积在N阱和P阱中的电荷。

13. 发明申请

US20070236998A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE WHICH STORES MULTIVALUE DATA 有权
标题翻译：存储数据数据的非易失性半导体存储器件
公开(公告)号：US20070236998A1
公开(公告)日：2007-10-11
申请号：US11763690
申请日：2007-06-15
申请人： Yasuhiko Honda , Masao Kuriyama
发明人： Yasuhiko Honda , Masao Kuriyama
IPC分类号： G11C16/28
CPC分类号： G11C16/28 , G11C11/5642 , G11C16/3445 , G11C16/3454 , G11C16/3459 , G11C2211/5621 , G11C2211/5634
摘要： A reference current generating circuit generates at least one reference current. A voltage generating circuit generates voltage. A sense amplifier compares a current caused to flow in a memory cell according to the voltage supplied from the voltage generating circuit with the reference current supplied from the reference current generating circuit. A control section is supplied with an output signal of the sense amplifier. When verifying the threshold voltage of the memory cell, the control section causes the voltage generating circuit to generate verify voltage which is the same as readout voltage generated at the time of data readout from the memory cell.
摘要翻译：参考电流产生电路产生至少一个参考电流。电压产生电路产生电压。感测放大器根据从电压产生电路提供的电压与从参考电流产生电路提供的参考电流将存储单元中的流量引起的电流进行比较。控制部分被提供有读出放大器的输出信号。当验证存储单元的阈值电压时，控制部分使得电压产生电路产生与从存储器单元读出数据时产生的读出电压相同的验证电压。

14. 发明授权

US07126855B2 Semiconductor device that enables simultaneous read and write/read operation 失效
标题翻译：实现同时读/写操作的半导体器件
公开(公告)号：US07126855B2
公开(公告)日：2006-10-24
申请号：US11125073
申请日：2005-05-10
申请人： Yasuhiko Honda , Hideo Kato , Hidetoshi Saito , Masao Kuriyama , Tokumasa Hara , Takafumi Ikeda , Tatsuya Hiramatsu
发明人： Yasuhiko Honda , Hideo Kato , Hidetoshi Saito , Masao Kuriyama , Tokumasa Hara , Takafumi Ikeda , Tatsuya Hiramatsu
IPC分类号： G11C16/06 , G11C16/04
CPC分类号： G11C8/12 , G11C16/10 , G11C16/26 , G11C2216/22
摘要： A semiconductor device has a memory cell array having the arrangement of a plurality of cores, each of which comprises one block or a set of a plurality of blocks, each block defining a range of memory cells serving as a unit of data erase. The semiconductor device has a bank setting memory circuit configured to select an optional number of cores of the cores as a first bank and to set the remaining cores as a second bank, so as to allow a data read operation to be carried out in one of the first and second banks while a data write or erase operation is carried out in the other of the first and second banks.
摘要翻译：半导体器件具有存储单元阵列，其具有多个核心的布置，每个核心包括一个块或一组多个块，每个块定义作为数据擦除单位的存储单元的范围。半导体器件具有存储体设置存储器电路，其被配置为选择核心的可选数量的核心作为第一存储体，并且将剩余的核心设置为第二存储体，以便允许数据读取操作以在第一和第二组中的另一个中进行数据写入或擦除操作的第一和第二存储体。

15. 发明申请

US20050207247A1 Semiconductor device that enables simultaneous read and write/read operation 失效
公开(公告)号：US20050207247A1
公开(公告)日：2005-09-22
申请号：US11125073
申请日：2005-05-10
申请人： Yasuhiko Honda , Hideo Kato , Hidetoshi Saito , Masao Kuriyama , Tokumasa Hara , Takafumi Ikeda , Tatsuya Hiramatsu
发明人： Yasuhiko Honda , Hideo Kato , Hidetoshi Saito , Masao Kuriyama , Tokumasa Hara , Takafumi Ikeda , Tatsuya Hiramatsu
IPC分类号： G11C16/00 , G11C5/00 , G11C8/12 , G11C16/10 , G11C16/26
CPC分类号： G11C8/12 , G11C16/10 , G11C16/26 , G11C2216/22
摘要： A semiconductor device has a memory cell array having the arrangement of a plurality of cores, each of which comprises one block or a set of a plurality of blocks, each block defining a range of memory cells serving as a unit of data erase. The semiconductor device has a bank setting memory circuit configured to select an optional number of cores of the cores as a first bank and to set the remaining cores as a second bank, so as to allow a data read operation to be carried out in one of the first and second banks while a data write or erase operation is carried out in the other of the first and second banks.

16. 发明授权

US06856543B2 Semiconductor integrated circuit device with erasable and programmable fuse memory 失效
标题翻译：具有可擦除和可编程保险丝存储器的半导体集成电路器件
公开(公告)号：US06856543B2
公开(公告)日：2005-02-15
申请号：US10743385
申请日：2003-12-23
申请人： Shigeru Atsumi , Masao Kuriyama , Akira Umezawa , Hironori Banba , Tadayuki Taura , Hidetoshi Saito
发明人： Shigeru Atsumi , Masao Kuriyama , Akira Umezawa , Hironori Banba , Tadayuki Taura , Hidetoshi Saito
IPC分类号： G11C5/00 , G11C5/14 , G11C16/04 , H01L29/78 , H03K5/153 , H03K5/22
CPC分类号： G11C5/143 , G11C5/14 , G11C7/1045 , G11C16/26 , G11C16/30
摘要： A semiconductor integrated circuit device includes fuse cells arranged at a fuse cell array, a fuse cell data program and erase circuit, a fuse cell data control circuit, and fuse data latch circuits. The fuse cells include erasable and programmable nonvolatile memory cells. The fuse cell data program and erase circuit programs fuse data to the memory cells and erases the fuse data from the memory cells. The fuse cell data control circuit controls read out timing of the fuse data stored in the memory cells based on a signal generated upon detection of power-on. The fuse data latch circuits latch the fuse data read out from the memory cells.
摘要翻译：半导体集成电路器件包括设置在熔丝单元阵列处的熔丝单元，熔丝单元数据程序和擦除电路，熔丝单元数据控制电路和熔丝数据锁存电路。熔丝单元包括可擦除和可编程的非易失性存储单元。熔丝单元数据程序和擦除电路程序将数据熔化到存储单元，并从存储单元擦除熔丝数据。熔丝单元数据控制电路基于在检测到通电时产生的信号来控制存储在存储单元中的熔丝数据的读出定时。熔丝数据锁存电路锁存从存储器单元读出的熔丝数据。

17. 发明授权

US06281665B1 High speed internal voltage generator with reduced current draw 有权
标题翻译：具有降低电流消耗的高速内部电压发生器
公开(公告)号：US06281665B1
公开(公告)日：2001-08-28
申请号：US09494298
申请日：2000-01-31
申请人： Takeshi Miyaba , Tooru Tanzawa , Masao Kuriyama
发明人： Takeshi Miyaba , Tooru Tanzawa , Masao Kuriyama
IPC分类号： G03F163
CPC分类号： G11C5/147
摘要： A first and a second transistor are connected to an output node. A first and a second differential amplifier compare a reference voltage with the voltage supplied from a voltage setting circuit. When the voltage at the output node is raised, the differential amplifier drives the first transistor, thereby charging the output node. In addition, when the voltage at the output node is lowered, the second differential amplifier drives the second transistor, thereby discharging the charges at the output node. The voltage setting circuit connected to the output node is composed of a current-summing D/A converter. In the voltage setting circuit, the value of the load resistance is varied according to the voltage appearing at the output node.
摘要翻译：第一和第二晶体管连接到输出节点。第一和第二差分放大器将参考电压与从电压设置电路提供的电压进行比较。当输出节点的电压升高时，差分放大器驱动第一晶体管，从而对输出节点充电。此外，当输出节点处的电压降低时，第二差分放大器驱动第二晶体管，从而在输出节点处放电。连接到输出节点的电压设置电路由电流求和D / A转换器组成。在电压设定电路中，负载电阻值根据输出节点出现的电压而变化。

18. 发明授权

US06236609B1 Nonvolatile semiconductor memory 有权
标题翻译：非易失性半导体存储器
公开(公告)号：US06236609B1
公开(公告)日：2001-05-22
申请号：US09527513
申请日：2000-03-16
申请人： Toru Tanzawa , Tadayuki Taura , Masao Kuriyama
发明人： Toru Tanzawa , Tadayuki Taura , Masao Kuriyama
IPC分类号： G11C1140
CPC分类号： G11C16/107 , G11C16/30 , G11C16/3409 , G11C16/344 , G11C16/3445 , G11C16/3459 , G11C16/3477
摘要： A potential generating circuit generates two types of erase verify threshold values EVT1 and EVT2. These values satisfy the relationship of EVT2=EVT1+(OEVT−EVTL). OEVT is an over-erase verify threshold value. While the erase verify threshold value is set at EVT2, the lower limit of a threshold voltage distribution after data erase is higher than OEVT. EVTL is the lower limit of the threshold voltage distribution after data erase while the erase verify threshold value is set at EVT1 and is lower than OEVT. The erase verify threshold values EVT1 and EVT2 are switched according to an operation mode. During a write/erase test, for example, the erase verify threshold value is set at EVT2. On the other hand, during the normal operation, the erase verify threshold value is set at EVT1.
摘要翻译：电位产生电路产生两种类型的擦除验证阈值EVT1和EVT2。这些值满足EVT2 = EVT1 +（OEVT-EVTL）的关系。 OEVT是过擦除验证阈值。当擦除验证阈值设定为EVT2时，数据擦除后阈值电压分布的下限高于OEVT。 EVTL是数据擦除后的阈值电压分布的下限，擦除验证阈值设定为EVT1，低于OEVT。根据操作模式切换擦除验证阈值EVT1和EVT2。在写入/擦除测试期间，例如，擦除验证阈值被设置为EVT2。另一方面，在正常操作期间，将擦除验证阈值设置为EVT1。

19. 发明授权

US06222773B1 Nonvolatile semiconductor memory in which the number of programming or erasing bits increases with the progress of programming or erasing 失效
标题翻译：非易失性半导体存储器，其中编程或擦除位的数量随着编程或擦除的进行而增加
公开(公告)号：US06222773B1
公开(公告)日：2001-04-24
申请号：US09592661
申请日：2000-06-13
申请人： Tooru Tanzawa , Nobuaki Otsuka , Hironori Banba , Shigeru Atsumi , Masao Kuriyama , Seiichi Mori , Seiji Yamada
发明人： Tooru Tanzawa , Nobuaki Otsuka , Hironori Banba , Shigeru Atsumi , Masao Kuriyama , Seiichi Mori , Seiji Yamada
IPC分类号： G11C1600
CPC分类号： G11C16/10 , G11C16/0483 , G11C16/14
摘要： A NOR type flash memory includes a plurality of word lines, a plurality of bit lines, at least one bit line, a plurality of nonvolatile memory cells, a row decoder, a cell selection circuit and a programming load. Each of the plurality of nonvolatile memory cells includes a gate electrode, drain electrode and source electrode and the gate electrode is connected to a corresponding one of the plurality of word lines, the drain electrode is connected to a corresponding one of the plurality of bit lines and the source electrode is connected to the source line. The row decoder selects one of the plurality of word lines at the time of data programming. The cell selection circuit includes a column decoder and column gates and is constructed to simultaneously select one bit line from each of the plurality of groups among the plurality of bit lines. The programming load increases the number of programming bits with the progress of programming when data of plural bits is programmed into a plurality of memory cells simultaneously selected by the cell selection circuit.
摘要翻译： NOR型闪速存储器包括多个字线，多个位线，至少一个位线，多个非易失性存储器单元，行解码器，单元选择电路和编程负载。多个非易失性存储单元中的每一个包括栅电极，漏电极和源电极，并且栅电极连接到多个字线中的相应一个字线，漏极连接到多个位线中的相应一个位线并且源极连接到源极线。行解码器在数据编程时选择多个字线之一。单元选择电路包括列解码器和列门，并被构造为从多个位线中的多个组中的每一个同时选择一个位线。当多个位的数据被编程到由单元选择电路同时选择的多个存储单元中时，编程负载增加了编程进程的编程位数。

20. 发明授权

US06118697A Nonvolatile semiconductor memory in which the number of programming or erasing bits increases with the progress of programming or erasing 有权
标题翻译：非易失性半导体存储器，其中编程或擦除位的数量随着编程或擦除的进行而增加
公开(公告)号：US06118697A
公开(公告)日：2000-09-12
申请号：US324775
申请日：1999-06-03
申请人： Tooru Tanzawa , Nobuaki Otsuka , Hironori Banba , Shigeru Atsumi , Masao Kuriyama , Seiichi Mori , Seiji Yamada
发明人： Tooru Tanzawa , Nobuaki Otsuka , Hironori Banba , Shigeru Atsumi , Masao Kuriyama , Seiichi Mori , Seiji Yamada
IPC分类号： G11C16/02 , G11C16/04 , G11C16/10 , G11C16/14 , G11C16/00
CPC分类号： G11C16/10 , G11C16/0483 , G11C16/14
摘要： A NOR type flash memory includes a plurality of word lines, a plurality of bit lines, at least one bit line, a plurality of nonvolatile memory cells, a row decoder, a cell selection circuit and a programming load. Each of the plurality of nonvolatile memory cells includes a gate electrode, drain electrode and source electrode and the gate electrode is connected to a corresponding one of the plurality of word lines, the drain electrode is connected to a corresponding one of the plurality of bit lines and the source electrode is connected to the source line. The row decoder selects one of the plurality of word lines at the time of data programming. The cell selection circuit includes a column decoder and column gates and is constructed to simultaneously select one bit line from each of the plurality of groups among the plurality of bit lines. The programming load increases the number of programming bits with the progress of programming when data of plural bits is programmed into a plurality of memory cells simultaneously selected by the cell selection circuit.
摘要翻译： NOR型闪速存储器包括多个字线，多个位线，至少一个位线，多个非易失性存储器单元，行解码器，单元选择电路和编程负载。多个非易失性存储单元中的每一个包括栅电极，漏电极和源电极，并且栅电极连接到多个字线中的相应一个字线，漏极连接到多个位线中的相应一个位线并且源极连接到源极线。行解码器在数据编程时选择多个字线之一。单元选择电路包括列解码器和列门，并被构造为从多个位线中的多个组中的每一个同时选择一个位线。当多个位的数据被编程到由单元选择电路同时选择的多个存储单元中时，编程负载增加了编程进程的编程位数。

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