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1. 发明授权

US07345919B2 Semiconductor device that enables simultaneous read and write/read operation 有权
标题翻译：实现同时读/写操作的半导体器件
公开(公告)号：US07345919B2
公开(公告)日：2008-03-18
申请号：US11453830
申请日：2006-06-16
申请人： Yasuhiko Honda , Hideo Kato , Hidetoshi Saito , Masao Kuriyama , Tokumasa Hara , Takafumi Ikeda , Tatsuya Hiramatsu
发明人： Yasuhiko Honda , Hideo Kato , Hidetoshi Saito , Masao Kuriyama , Tokumasa Hara , Takafumi Ikeda , Tatsuya Hiramatsu
IPC分类号： G11C16/04
CPC分类号： G11C8/12 , G11C16/10 , G11C16/26 , G11C2216/22
摘要： A semiconductor device includes a memory cell array including a plurality of cores, each of said cores including one block or a plurality of blocks. The semiconductor device further includes a first power supply line which is provided commonly for said plurality of cores and which provides a data reading power supply potential; a second power supply line which is provided commonly for said plurality of cores and which provides a data writing or erasing power supply potential; and a power supply line switching circuit which is provided for each of said plurality of cores and which selectively connects a corresponding one of said plurality of cores to said first power supply line or said second power supply line in accordance with whether said corresponding one of said plurality of cores is in a data read mode or a data write or erase mode.
摘要翻译：半导体器件包括包括多个核的存储单元阵列，每个所述核包括一个块或多个块。所述半导体器件还包括第一电源线，所述第一电源线通常为所述多个芯提供，并提供数据读取电源电位; 第二电源线，其为所述多个核心共同提供，并且提供数据写入或擦除电源电位; 以及电源线切换电路，其被设置用于所述多个芯中的每一个，并且根据所述多个核中的所述相应一个选择性地将所述多个核中的相应一个核连接到所述第一电源线或所述第二电源线多个核心处于数据读取模式或数据写入或擦除模式。

2. 发明授权

US06842377B2 Nonvolatile semiconductor memory device with first and second read modes 失效
标题翻译：具有第一和第二读取模式的非易失性半导体存储器件
公开(公告)号：US06842377B2
公开(公告)日：2005-01-11
申请号：US10412646
申请日：2003-04-11
申请人： Yoshinori Takano , Yasuhiko Honda , Toru Tanzawa , Masao Kuriyama
发明人： Yoshinori Takano , Yasuhiko Honda , Toru Tanzawa , Masao Kuriyama
IPC分类号： G11C16/02 , G11C7/10 , G11C7/22 , G11C16/06 , G11C16/26 , G11C16/28
CPC分类号： G11C7/22 , G11C7/1021 , G11C16/26 , G11C16/28 , G11C2207/2281
摘要： A nonvolatile semiconductor memory device with a plurality of read modes switchably built therein is provided. This nonvolatile semiconductor memory device is the one that has a memory cell array in which electrically rewritable nonvolatile memory cells are laid out and a read circuit which performs data readout of the memory cell array. The nonvolatile semiconductor memory device has a first read mode and a second read mode. The first read mode is for reading data by means of parallel data transfer of the same bit number when sending data from the memory cell array through the read circuit up to more than one external terminal. The second read mode is for performing parallel data transfer of a greater bit number than that of the first read mode when sending data from the memory cell array to the read circuit while performing data transfer of a smaller bit number than the bit number when sending data from the read circuit up to the external terminal.
摘要翻译：提供了一种具有可切换地构建的多个读取模式的非易失性半导体存储器件。这种非易失性半导体存储器件是具有其中布置有电可重写非易失性存储单元的存储单元阵列，以及执行存储单元阵列的数据读出的读电路。非易失性半导体存储器件具有第一读取模式和第二读取模式。第一读取模式是通过从存储单元阵列通过读取电路向多于一个的外部端子发送数据时，通过相同位数的并行数据传输来读取数据。第二读取模式用于在将数据从存储器单元阵列发送到读取电路时执行比第一读取模式更大位数的并行数据传输，同时在发送数据时执行比位数更小位数的数据传输从读取电路到外部端子。

3. 发明授权

US06532181B2 Semiconductor memory device having redundant circuitry for replacing defective memory cell 有权
标题翻译：具有用于替换有缺陷的存储单元的冗余电路的半导体存储器件
公开(公告)号：US06532181B2
公开(公告)日：2003-03-11
申请号：US09963404
申请日：2001-09-27
申请人： Hidetoshi Saito , Masao Kuriyama , Yasuhiko Honda , Hideo Kato
发明人： Hidetoshi Saito , Masao Kuriyama , Yasuhiko Honda , Hideo Kato
IPC分类号： G11C700
CPC分类号： G11C29/78 , G11C8/06 , G11C16/26 , G11C2216/22
摘要： A nonvolatile semiconductor memory includes a memory cell array and a redundant cell array, and while a data write operation or a data erase operation is carried out in one of banks in the memory cell array, a data read operation can be carried out in the other banks. The redundant cell array has one or more spare blocks and is provided independently of the banks to relieve a defective memory cell of the memory cell array by substituting the spare block for a defective memory block in any of the blocks. The memory block is active when an access block address to be accessed in the memory cell array in the data write or erase operation or the data read operation does not coincide with the defective block address in the defective address storing circuit, whereas the spare block is active when the access block address coincides with the defective block address in the defective address storing circuit.
摘要翻译：非易失性半导体存储器包括存储单元阵列和冗余单元阵列，并且在存储单元阵列中的一个存储体中进行数据写入操作或数据擦除操作时，可以在另一个存储单元阵列中执行数据读取操作银行。冗余单元阵列具有一个或多个备用块，并且独立于存储体提供，以通过将备用块替换为任何块中的有缺陷的存储块来解除存储单元阵列的有缺陷的存储单元。当在数据写入或擦除操作或数据读取操作中要存储在存储单元阵列中的访问块地址与缺陷地址存储电路中的有缺陷块地址不一致时，存储块有效，而备用块是当访问块地址与缺陷地址存储电路中的有缺陷的块地址一致时有效。

4. 发明授权

US06377502B1 Semiconductor device that enables simultaneous read and write/erase operation 有权
标题翻译：实现同时读/写/擦除操作的半导体器件
公开(公告)号：US06377502B1
公开(公告)日：2002-04-23
申请号：US09563348
申请日：2000-05-03
申请人： Yasuhiko Honda , Hideo Kato , Hidetoshi Saito , Masao Kuriyama , Tokumasa Hara , Takafumi Ikeda , Tatsuya Hiramatsu
发明人： Yasuhiko Honda , Hideo Kato , Hidetoshi Saito , Masao Kuriyama , Tokumasa Hara , Takafumi Ikeda , Tatsuya Hiramatsu
IPC分类号： G11C800
CPC分类号： G11C8/12 , G11C16/10 , G11C16/26 , G11C2216/22
摘要： A memory cell array 1 has the arrangement of a plurality of cores, each of which comprises one block or a set of a plurality of blocks, each block defining a range of memory cells serving as a unit of data erase. A core selecting part for selecting an optional number of cores to write/erase data is provided for writing data in memory cells in cores selected on the basis of a write command and for erasing data from selected blocks in cores selected on the basis of an erase command. Thus, there is realized a free core system capable of reading data out from memory cells in unselected cores while writing/erasing data in cores selected by the core selecting part.
摘要翻译：存储单元阵列1具有多个核心的布置，每个核心包括一个块或一组多个块，每个块定义用作数据擦除单位的存储单元的范围。提供用于选择写入/擦除数据的可选数量的核心的核心选择部分，用于将数据写入基于写入命令选择的核心的存储器单元中，并且用于从基于擦除选择的核心中的所选择的块中擦除数据命令。因此，实现了一种自由核心系统，其能够在由核心选择部分选择的核心中写入/擦除数据时，从未选择的核心中的存储器单元读出数据。

5. 发明申请

US20070236998A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE WHICH STORES MULTIVALUE DATA 有权
标题翻译：存储数据数据的非易失性半导体存储器件
公开(公告)号：US20070236998A1
公开(公告)日：2007-10-11
申请号：US11763690
申请日：2007-06-15
申请人： Yasuhiko Honda , Masao Kuriyama
发明人： Yasuhiko Honda , Masao Kuriyama
IPC分类号： G11C16/28
CPC分类号： G11C16/28 , G11C11/5642 , G11C16/3445 , G11C16/3454 , G11C16/3459 , G11C2211/5621 , G11C2211/5634
摘要： A reference current generating circuit generates at least one reference current. A voltage generating circuit generates voltage. A sense amplifier compares a current caused to flow in a memory cell according to the voltage supplied from the voltage generating circuit with the reference current supplied from the reference current generating circuit. A control section is supplied with an output signal of the sense amplifier. When verifying the threshold voltage of the memory cell, the control section causes the voltage generating circuit to generate verify voltage which is the same as readout voltage generated at the time of data readout from the memory cell.
摘要翻译：参考电流产生电路产生至少一个参考电流。电压产生电路产生电压。感测放大器根据从电压产生电路提供的电压与从参考电流产生电路提供的参考电流将存储单元中的流量引起的电流进行比较。控制部分被提供有读出放大器的输出信号。当验证存储单元的阈值电压时，控制部分使得电压产生电路产生与从存储器单元读出数据时产生的读出电压相同的验证电压。

6. 发明授权

US07126855B2 Semiconductor device that enables simultaneous read and write/read operation 失效
标题翻译：实现同时读/写操作的半导体器件
公开(公告)号：US07126855B2
公开(公告)日：2006-10-24
申请号：US11125073
申请日：2005-05-10
申请人： Yasuhiko Honda , Hideo Kato , Hidetoshi Saito , Masao Kuriyama , Tokumasa Hara , Takafumi Ikeda , Tatsuya Hiramatsu
发明人： Yasuhiko Honda , Hideo Kato , Hidetoshi Saito , Masao Kuriyama , Tokumasa Hara , Takafumi Ikeda , Tatsuya Hiramatsu
IPC分类号： G11C16/06 , G11C16/04
CPC分类号： G11C8/12 , G11C16/10 , G11C16/26 , G11C2216/22
摘要： A semiconductor device has a memory cell array having the arrangement of a plurality of cores, each of which comprises one block or a set of a plurality of blocks, each block defining a range of memory cells serving as a unit of data erase. The semiconductor device has a bank setting memory circuit configured to select an optional number of cores of the cores as a first bank and to set the remaining cores as a second bank, so as to allow a data read operation to be carried out in one of the first and second banks while a data write or erase operation is carried out in the other of the first and second banks.
摘要翻译：半导体器件具有存储单元阵列，其具有多个核心的布置，每个核心包括一个块或一组多个块，每个块定义作为数据擦除单位的存储单元的范围。半导体器件具有存储体设置存储器电路，其被配置为选择核心的可选数量的核心作为第一存储体，并且将剩余的核心设置为第二存储体，以便允许数据读取操作以在第一和第二组中的另一个中进行数据写入或擦除操作的第一和第二存储体。

7. 发明申请

US20050207247A1 Semiconductor device that enables simultaneous read and write/read operation 失效
公开(公告)号：US20050207247A1
公开(公告)日：2005-09-22
申请号：US11125073
申请日：2005-05-10
申请人： Yasuhiko Honda , Hideo Kato , Hidetoshi Saito , Masao Kuriyama , Tokumasa Hara , Takafumi Ikeda , Tatsuya Hiramatsu
发明人： Yasuhiko Honda , Hideo Kato , Hidetoshi Saito , Masao Kuriyama , Tokumasa Hara , Takafumi Ikeda , Tatsuya Hiramatsu
IPC分类号： G11C16/00 , G11C5/00 , G11C8/12 , G11C16/10 , G11C16/26
CPC分类号： G11C8/12 , G11C16/10 , G11C16/26 , G11C2216/22
摘要： A semiconductor device has a memory cell array having the arrangement of a plurality of cores, each of which comprises one block or a set of a plurality of blocks, each block defining a range of memory cells serving as a unit of data erase. The semiconductor device has a bank setting memory circuit configured to select an optional number of cores of the cores as a first bank and to set the remaining cores as a second bank, so as to allow a data read operation to be carried out in one of the first and second banks while a data write or erase operation is carried out in the other of the first and second banks.

8. 发明授权

US07420863B2 Nonvolatile semiconductor memory device which stores multivalue data 失效
公开(公告)号：US07420863B2
公开(公告)日：2008-09-02
申请号：US11763743
申请日：2007-06-15
申请人： Yasuhiko Honda , Masao Kuriyama
发明人： Yasuhiko Honda , Masao Kuriyama
IPC分类号： G11C7/02
CPC分类号： G11C16/28 , G11C11/5642 , G11C16/3445 , G11C16/3454 , G11C16/3459 , G11C2211/5621 , G11C2211/5634
摘要： A reference current generating circuit generates at least one reference current. A voltage generating circuit generates voltage. A sense amplifier compares a current caused to flow in a memory cell according to the voltage supplied from the voltage generating circuit with the reference current supplied from the reference current generating circuit. A control section is supplied with an output signal of the sense amplifier. When verifying the threshold voltage of the memory cell, the control section causes the voltage generating circuit to generate verify voltage which is the same as readout voltage generated at the time of data readout from the memory cell.

9. 发明授权

US07397716B2 Nonvolatile semiconductor memory device which stores multivalue data 有权
公开(公告)号：US07397716B2
公开(公告)日：2008-07-08
申请号：US11401286
申请日：2006-04-11
申请人： Yasuhiko Honda , Masao Kuriyama
发明人： Yasuhiko Honda , Masao Kuriyama
IPC分类号： G11C7/02
CPC分类号： G11C16/28 , G11C11/5642 , G11C16/3445 , G11C16/3454 , G11C16/3459 , G11C2211/5621 , G11C2211/5634
摘要： A reference current generating circuit generates at least one reference current. A voltage generating circuit generates voltage. A sense amplifier compares a current caused to flow in a memory cell according to the voltage supplied from the voltage generating circuit with the reference current supplied from the reference current generating circuit. A control section is supplied with an output signal of the sense amplifier. When verifying the threshold voltage of the memory cell, the control section causes the voltage generating circuit to generate verify voltage which is the same as readout voltage generated at the time of data readout from the memory cell.

10. 发明授权

US06829194B2 Semiconductor device that enables simultaneous read and write/read operation 有权
标题翻译：实现同时读/写操作的半导体器件
公开(公告)号：US06829194B2
公开(公告)日：2004-12-07
申请号：US10307283
申请日：2002-12-02
申请人： Yasuhiko Honda , Hideo Kato , Hidetoshi Saito , Masao Kuriyama , Tokumasa Hara , Takafumi Ikeda , Tatsuya Hiramatsu
发明人： Yasuhiko Honda , Hideo Kato , Hidetoshi Saito , Masao Kuriyama , Tokumasa Hara , Takafumi Ikeda , Tatsuya Hiramatsu
IPC分类号： G11C800
CPC分类号： G11C8/12 , G11C16/10 , G11C16/26 , G11C2216/22
摘要： A memory cell array 1 has the arrangement of a plurality of cores, each of which comprises one block or a set of a plurality of blocks, each block defining a range of memory cells serving as a unit of data erase. A core selecting part for selecting an optional number of cores to write/erase data is provided for writing data in memory cells in cores selected on the basis of a write command and for erasing data from selected blocks in cores selected on the basis of an erase command. Thus, there is realized a free core system capable of reading data out from memory cells in unselected cores while writing/erasing data in cores selected by the core selecting part.
摘要翻译：半导体器件具有存储单元阵列，其具有多个核心的布置，每个核心包括一个块或一组多个块，每个块定义用作数据擦除单位的存储单元范围。半导体设备具有存储体设置存储器电路，其被配置为选择核心的可选数量的核心作为第一存储体，并且将剩余的核心设置为第二存储体，以便允许数据读取操作在第一存储器和第二存储体，同时在第一和第二存储体的另一个中进行数据写入或擦除操作。

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