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1. 发明授权

US06222773B1 Nonvolatile semiconductor memory in which the number of programming or erasing bits increases with the progress of programming or erasing 失效
标题翻译：非易失性半导体存储器，其中编程或擦除位的数量随着编程或擦除的进行而增加
公开(公告)号：US06222773B1
公开(公告)日：2001-04-24
申请号：US09592661
申请日：2000-06-13
申请人： Tooru Tanzawa , Nobuaki Otsuka , Hironori Banba , Shigeru Atsumi , Masao Kuriyama , Seiichi Mori , Seiji Yamada
发明人： Tooru Tanzawa , Nobuaki Otsuka , Hironori Banba , Shigeru Atsumi , Masao Kuriyama , Seiichi Mori , Seiji Yamada
IPC分类号： G11C1600
CPC分类号： G11C16/10 , G11C16/0483 , G11C16/14
摘要： A NOR type flash memory includes a plurality of word lines, a plurality of bit lines, at least one bit line, a plurality of nonvolatile memory cells, a row decoder, a cell selection circuit and a programming load. Each of the plurality of nonvolatile memory cells includes a gate electrode, drain electrode and source electrode and the gate electrode is connected to a corresponding one of the plurality of word lines, the drain electrode is connected to a corresponding one of the plurality of bit lines and the source electrode is connected to the source line. The row decoder selects one of the plurality of word lines at the time of data programming. The cell selection circuit includes a column decoder and column gates and is constructed to simultaneously select one bit line from each of the plurality of groups among the plurality of bit lines. The programming load increases the number of programming bits with the progress of programming when data of plural bits is programmed into a plurality of memory cells simultaneously selected by the cell selection circuit.
摘要翻译： NOR型闪速存储器包括多个字线，多个位线，至少一个位线，多个非易失性存储器单元，行解码器，单元选择电路和编程负载。多个非易失性存储单元中的每一个包括栅电极，漏电极和源电极，并且栅电极连接到多个字线中的相应一个字线，漏极连接到多个位线中的相应一个位线并且源极连接到源极线。行解码器在数据编程时选择多个字线之一。单元选择电路包括列解码器和列门，并被构造为从多个位线中的多个组中的每一个同时选择一个位线。当多个位的数据被编程到由单元选择电路同时选择的多个存储单元中时，编程负载增加了编程进程的编程位数。

2. 发明授权

US06118697A Nonvolatile semiconductor memory in which the number of programming or erasing bits increases with the progress of programming or erasing 有权
标题翻译：非易失性半导体存储器，其中编程或擦除位的数量随着编程或擦除的进行而增加
公开(公告)号：US06118697A
公开(公告)日：2000-09-12
申请号：US324775
申请日：1999-06-03
申请人： Tooru Tanzawa , Nobuaki Otsuka , Hironori Banba , Shigeru Atsumi , Masao Kuriyama , Seiichi Mori , Seiji Yamada
发明人： Tooru Tanzawa , Nobuaki Otsuka , Hironori Banba , Shigeru Atsumi , Masao Kuriyama , Seiichi Mori , Seiji Yamada
IPC分类号： G11C16/02 , G11C16/04 , G11C16/10 , G11C16/14 , G11C16/00
CPC分类号： G11C16/10 , G11C16/0483 , G11C16/14
摘要： A NOR type flash memory includes a plurality of word lines, a plurality of bit lines, at least one bit line, a plurality of nonvolatile memory cells, a row decoder, a cell selection circuit and a programming load. Each of the plurality of nonvolatile memory cells includes a gate electrode, drain electrode and source electrode and the gate electrode is connected to a corresponding one of the plurality of word lines, the drain electrode is connected to a corresponding one of the plurality of bit lines and the source electrode is connected to the source line. The row decoder selects one of the plurality of word lines at the time of data programming. The cell selection circuit includes a column decoder and column gates and is constructed to simultaneously select one bit line from each of the plurality of groups among the plurality of bit lines. The programming load increases the number of programming bits with the progress of programming when data of plural bits is programmed into a plurality of memory cells simultaneously selected by the cell selection circuit.
摘要翻译： NOR型闪速存储器包括多个字线，多个位线，至少一个位线，多个非易失性存储器单元，行解码器，单元选择电路和编程负载。多个非易失性存储单元中的每一个包括栅电极，漏电极和源电极，并且栅电极连接到多个字线中的相应一个字线，漏极连接到多个位线中的相应一个位线并且源极连接到源极线。行解码器在数据编程时选择多个字线之一。单元选择电路包括列解码器和列门，并被构造为从多个位线中的多个组中的每一个同时选择一个位线。当多个位的数据被编程到由单元选择电路同时选择的多个存储单元中时，编程负载增加了编程进程的编程位数。

3. 发明授权

US06281665B1 High speed internal voltage generator with reduced current draw 有权
标题翻译：具有降低电流消耗的高速内部电压发生器
公开(公告)号：US06281665B1
公开(公告)日：2001-08-28
申请号：US09494298
申请日：2000-01-31
申请人： Takeshi Miyaba , Tooru Tanzawa , Masao Kuriyama
发明人： Takeshi Miyaba , Tooru Tanzawa , Masao Kuriyama
IPC分类号： G03F163
CPC分类号： G11C5/147
摘要： A first and a second transistor are connected to an output node. A first and a second differential amplifier compare a reference voltage with the voltage supplied from a voltage setting circuit. When the voltage at the output node is raised, the differential amplifier drives the first transistor, thereby charging the output node. In addition, when the voltage at the output node is lowered, the second differential amplifier drives the second transistor, thereby discharging the charges at the output node. The voltage setting circuit connected to the output node is composed of a current-summing D/A converter. In the voltage setting circuit, the value of the load resistance is varied according to the voltage appearing at the output node.
摘要翻译：第一和第二晶体管连接到输出节点。第一和第二差分放大器将参考电压与从电压设置电路提供的电压进行比较。当输出节点的电压升高时，差分放大器驱动第一晶体管，从而对输出节点充电。此外，当输出节点处的电压降低时，第二差分放大器驱动第二晶体管，从而在输出节点处放电。连接到输出节点的电压设置电路由电流求和D / A转换器组成。在电压设定电路中，负载电阻值根据输出节点出现的电压而变化。

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