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1. 发明授权

US07120053B2 Semiconductor intergrated circuit device with a main cell array and a fuse cell array whose word lines and bit lines are extended in the same directions 失效
标题翻译：半导体集成电路器件具有主单元阵列和熔丝单元阵列，其字线和位线在相同方向上延伸
公开(公告)号：US07120053B2
公开(公告)日：2006-10-10
申请号：US11033398
申请日：2005-01-12
申请人： Shigeru Atsumi , Masao Kuriyama , Akira Umezawa , Hironori Banba , Tadayuki Taura , Hidetoshi Saito
发明人： Shigeru Atsumi , Masao Kuriyama , Akira Umezawa , Hironori Banba , Tadayuki Taura , Hidetoshi Saito
IPC分类号： G11C16/22
CPC分类号： G11C5/143 , G11C5/14 , G11C7/1045 , G11C16/26 , G11C16/30
摘要： A semiconductor integrated circuit device includes a main cell array, a fuse cell array, main cell word lines arranged at the main cell array, and fuse cell word lines arranged at the fuse cell array. The fuse cell word lines are formed in a same direction as a direction of the main cell word lines.
摘要翻译：半导体集成电路器件包括主单元阵列，熔丝单元阵列，布置在主单元阵列处的主单元字线以及布置在熔丝单元阵列处的熔丝单元字线。熔丝单元字线形成在与主单元字线的方向相同的方向上。

2. 发明授权

US06356499B1 Power supply circuit and semiconductor memory device having the same 有权
公开(公告)号：US06356499B1
公开(公告)日：2002-03-12
申请号：US09640370
申请日：2000-08-17
申请人： Hironori Banba , Shigeru Atsumi
发明人： Hironori Banba , Shigeru Atsumi
IPC分类号： G11C700
CPC分类号： G11C16/30 , G11C5/145 , H02M3/073
摘要： A number of booster circuits to be operated out of a plurality of booster circuits are selected in accordance with a level of the boosted voltage to be provided at a common voltage output terminal of the plurality of booster circuits. With such an arrangement, fluctuations in the output voltage that can appear when a light load is applied to the voltage output terminal of the booster circuits can be effectively reduced to make the semiconductor memory device driven by the power supply circuit operate reliably. Further, one of the output terminals of intermediate voltage booster circuits is connected to the output terminal of a high voltage booster circuit. Then, a desired voltage can be obtained from the booster circuits that are implemented without using costly transistors to reduce the chip cost.

3. 发明授权

US06326834B1 Pump circuit boosting a supply voltage 失效
标题翻译：泵电路提升电源电压
公开(公告)号：US06326834B1
公开(公告)日：2001-12-04
申请号：US09602896
申请日：2000-06-23
申请人： Hironobu Akita , Masaharu Wada , Kenji Tsuchida , Hironori Banba
发明人： Hironobu Akita , Masaharu Wada , Kenji Tsuchida , Hironori Banba
IPC分类号： G05F110
CPC分类号： H02M3/073
摘要： First transistors for charging respective one side nodes of a plurality of capacitors are connected to these nodes of the capacitors, respectively. Second transistors for outputting electric charge of each capacitor are connected between respective one side nodes of the capacitors and an output terminal, respectively. A plurality of third transistors for transferring the electric charge of the other side nodes of the capacitors to the other nodes are connected to the respective other nodes. The electric charge of each capacitor is serially transferred from nodes of a high electric potential to nodes of a lower electric potential through one path by sequentially controlling the third transistors, or the electric charge of each capacitor is parallel transferred between arbitrary nodes of a high electric potential and low nodes through a plurality of paths. By these operations, electric charge of each capacitor is recycled.
摘要翻译：用于对多个电容器的各个侧面节点进行充电的第一晶体管分别连接到电容器的这些节点。用于输出每个电容器的电荷的第二晶体管分别连接在电容器的相应的一个侧面节点和输出端子之间。用于将电容器的另一侧节点的电荷转移到其他节点的多个第三晶体管连接到相应的其他节点。每个电容器的电荷通过顺序地控制第三晶体管，通过一个路径从高电位的节点被串行地传递到较低电位的节点，或者每个电容器的电荷在高电位的任意节点之间并行传送潜在和低节点通过多个路径。通过这些操作，每个电容器的电荷被再循环。

4. 发明授权

US06195307B1 Booster circuit and semiconductor memory device having the same 有权
标题翻译：具有相同功能的升压电路和半导体存储器件
公开(公告)号：US06195307B1
公开(公告)日：2001-02-27
申请号：US09502045
申请日：2000-02-11
申请人： Akira Umezawa , Shigeru Atsumi , Hironori Banba
发明人： Akira Umezawa , Shigeru Atsumi , Hironori Banba
IPC分类号： G11C700
CPC分类号： G11C5/145 , G11C16/30
摘要： In a booster circuit, a gate of an input-side transistor whose end is supplied with a power supply voltage is supplied with an inverted signal of a signal supplied to a signal input terminal of a booster unit at a first stage or supplied with an AND signal of the inverted signal and a booster circuit activation signal. Therefore, when the transistor at the first stage operates, the input-side transistor is turned off. Accordingly, a back flow of a current from inside the booster circuit to a power supply is prevented, so that the efficiency of the booster circuit can be improved. Further, fluctuations of the output voltage are not brought about even when the power supply voltage greatly fluctuates, so that the reliability of peripheral elements and memory cells can be improved and the allowable range of an external power supply voltage can be widened.
摘要翻译：在升压电路中，向其端部供给电源电压的输入侧晶体管的栅极提供在第一级提供给增压器单元的信号输入端子的信号的反相信号，或者被提供有“ 反相信号的信号和升压电路激活信号。因此，当第一级的晶体管工作时，输入侧晶体管截止。因此，防止了从升压电路内部到电源的电流的反向流动，从而可以提高升压电路的效率。此外，即使当电源电压剧烈波动时也不会产生输出电压的波动，从而可以提高外围元件和存储单元的可靠性，并且可以扩大外部电源电压的允许范围。

5. 发明授权

US6144582A Nonvolatile semiconductor memory device 失效
公开(公告)号：US6144582A
公开(公告)日：2000-11-07
申请号：US220328
申请日：1998-12-24
申请人： Shigeru Atsumi , Hironori Banba
发明人： Shigeru Atsumi , Hironori Banba
IPC分类号： G11C16/06 , G11C5/06 , G11C11/34 , G11C16/02 , G11C16/04 , G11C16/08 , G11C16/16
CPC分类号： G11C16/16 , G11C16/08
摘要： A nonvolatile semiconductor memory device includes a row decoder circuit having first and second N-channel MOS transistors and first and second P-channel MOS transistors which correspond to each of word lines. One end of a source-to-drain current path of the first N-channel MOS transistor is connected to the word line, and the other end thereof is connected to a corresponding one of output terminals of a predecoder circuit. One end of a source-to-drain current path of the second N-channel MOS transistor is connected to the word line, and the other end thereof is supplied with a voltage of 0V or more in a data erase mode and is supplied with a low logical level signal in modes other than the data erase mode. A source-to-drain current path of the first P-channel MOS transistor is connected in parallel to the source-to-drain current path of the first N-channel MOS transistor, and a source-to-drain current path of the second P-channel MOS transistor is connected in parallel to the source-to-drain current path of the second N-channel MOS transistor.

6. 发明授权

US6041012A Semiconductor integrated circuit device having a booster circuit and a storage device 失效
标题翻译：具有升压电路和存储装置的半导体集成电路装置
公开(公告)号：US6041012A
公开(公告)日：2000-03-21
申请号：US31686
申请日：1998-02-27
申请人： Hironori Banba , Hitoshi Shiga , Shigeru Atsumi , Akira Umezawa
发明人： Hironori Banba , Hitoshi Shiga , Shigeru Atsumi , Akira Umezawa
IPC分类号： G11C5/14 , G11C16/30 , G11C7/00
CPC分类号： G11C5/143 , G11C16/30 , G11C5/145 , G11C5/147
摘要： A semiconductor integrated circuit device according to the present invention includes a booster circuit 1 for raising an external power supply voltage Vccext, a level detecting circuit 2 for detecting fluctuation in a stepped-up voltage Vccint2, an internal voltage generating circuit 3 for generating an internal voltage Vccint on the basis of the stepped-up voltage Vccint2, an address buffer 4, an address decoder 5, and a memory cell array 6 of an EEPROM structure. The level detecting circuit 2 includes a first level detecting part for performing level detection during a memory access state, and a second level detecting part for performing level detection during a stand-by state. During the stand-by state, the internal voltage generating circuit 3 short-circuits the stepped-up voltage Vccint2 and the internal voltage Vccint. The second level detecting part has lower power consumption than that of the first level detecting part, so that it is possible to reducing the power consumption during the stand-by state without lowering the driving voltage.
摘要翻译：根据本发明的半导体集成电路器件包括用于提高外部电源电压Vccext的升压电路1，用于检测升压电压Vccint2中的波动的电平检测电路2，用于产生内部电压的内部电压产生电路3 基于升压电压Vccint2的电压Vccint，地址缓冲器4，地址解码器5和EEPROM结构的存储单元阵列6。电平检测电路2包括用于在存储器访问状态期间执行电平检测的第一电平检测部分和用于在待机状态期间执行电平检测的第二电平检测部分。在待机状态下，内部电压产生电路3使升压电压Vccint2和内部电压Vccint短路。第二电平检测部件具有比第一电平检测部件低的功率消耗，从而可以在不降低驱动电压的情况下降低待机状态下的功耗。

7. 发明授权

US06700817B2 Semiconductor integrated circuit device with operation/function setting information memory 失效
标题翻译：具有操作/功能设定信息存储器的半导体集成电路器件
公开(公告)号：US06700817B2
公开(公告)日：2004-03-02
申请号：US10265728
申请日：2002-10-08
申请人： Shigeru Atsumi , Masao Kuriyama , Akira Umezawa , Hironori Banba , Tadayuki Taura , Hidetoshi Saito
发明人： Shigeru Atsumi , Masao Kuriyama , Akira Umezawa , Hironori Banba , Tadayuki Taura , Hidetoshi Saito
IPC分类号： G11C1604
CPC分类号： G11C5/143 , G11C5/14 , G11C7/1045 , G11C16/26 , G11C16/30
摘要： A semiconductor integrated circuit device includes a nonvolatile memory cell, a source of the cell receiving a ground potential, and a gate of the cell receiving a first control signal; a transistor, a source of the transistor receiving a drain potential of the cell, and a gate of the transistor receiving a second control signal; and a controller. The controller receives a third control signal generated upon detection of power-on and outputs the first and second control signals. A potential of the first control signal changes from the ground potential to a potential different from the ground potential, which is maintained during a first period of time, and a potential of the second control signal changes from the ground potential to a potential different from the ground potential, which is maintained during a second period of time.
摘要翻译：半导体集成电路装置包括：非易失性存储单元，接收地电位的单元的源极和接收第一控制信号的单元的栅极; 晶体管，晶体管的源极，接收所述单元的漏极电位，以及所述晶体管的栅极接收第二控制信号; 和控制器。控制器接收在检测到电源接通时产生的第三控制信号，并输出第一和第二控制信号。第一控制信号的电位从接地电位变化到在第一时间段期间保持的接地电位不同的电位，并且第二控制信号的电位从地电势变为不同于地电位，在第二段时间内保持。

8. 发明授权

US06433619B1 Pump circuit boosting a supply voltage 有权
公开(公告)号：US06433619B1
公开(公告)日：2002-08-13
申请号：US09972905
申请日：2001-10-10
申请人： Hironobu Akita , Masaharu Wada , Kenji Tsuchida , Hironori Banba
发明人： Hironobu Akita , Masaharu Wada , Kenji Tsuchida , Hironori Banba
IPC分类号： G05F110
摘要： First transistors for charging respective one side nodes of a plurality of capacitors are connected to these nodes of the capacitors, respectively. Second transistors for outputting electric charge of each capacitor are connected between respective one side nodes of the capacitors and an output terminal, respectively. A plurality of third transistors for transferring the electric charge of the other side nodes of the capacitors to the other nodes are connected to the respective other nodes. The electric charge of each capacitor is serially transferred from nodes of a high electric potential to nodes of a lower electric potential through one path by sequentially controlling the third transistors, or the electric charge of each capacitor is parallel transferred between arbitrary nodes of a high electric potential and low nodes through a plurality of paths. By these operations, electric charge of each capacitor is recycled.

9. 发明授权

US06385087B2 Nonvolatile semiconductor memory device 失效
标题翻译：非易失性半导体存储器件
公开(公告)号：US06385087B2
公开(公告)日：2002-05-07
申请号：US09851332
申请日：2001-05-09
申请人： Shigeru Atsumi , Hironori Banba
发明人： Shigeru Atsumi , Hironori Banba
IPC分类号： G11C1134
CPC分类号： G11C16/16 , G11C16/08
摘要： A nonvolatile semiconductor memory device includes a row decoder circuit having first and second N-channel MOS transistors and first and second P-channel MOS transistors which correspond to each of word lines. One end of a source-to-drain current path of the first N-channel MOS transistor is connected to the word line, and the other end thereof is connected to a corresponding one of output terminals of a predecoder circuit. One end of a source-to-drain current path of the second N-channel MOS transistor is connected to the word line, and the other end thereof is supplied with a voltage of 0V or more in a data erase mode and is supplied with a low logical level signal in modes other than the data erase mode. A source-to-drain current path of the first P-channel MOS transistor is connected in parallel to the source-to-drain current path of the first N-channel MOS transistor, and a source-to-drain current path of the second P-channel MOS transistor is connected in parallel to the source-to-drain current path of the second N-channel MOS transistor.
摘要翻译：非易失性半导体存储器件包括具有第一和第二N沟道MOS晶体管的行解码器电路和对应于每条字线的第一和第二P沟道MOS晶体管。第一N沟道MOS晶体管的源极 - 漏极电流路径的一端连接到字线，并且其另一端连接到预解码器电路的对应的一个输出端。第二N沟道MOS晶体管的源极到漏极电流路径的一端连接到字线，并且在数据擦除模式中，其另一端被提供0V以上的电压，并被提供有低数据擦除模式以外的模式下的低逻辑电平信号。第一P沟道MOS晶体管的源极 - 漏极电流路径并联连接到第一N沟道MOS晶体管的源极 - 漏极电流路径，并且第二P沟道MOS晶体管的源极 - 漏极电流路径 P沟道MOS晶体管与第二N沟道MOS晶体管的源极 - 漏极电流路径并联连接。

10. 发明授权

US06320428B1 Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件
公开(公告)号：US06320428B1
公开(公告)日：2001-11-20
申请号：US09527582
申请日：2000-03-17
申请人： Shigeru Atsumi , Masao Kuriyama , Akira Umezawa , Hironori Banba , Tadayuki Taura , Hidetoshi Saito
发明人： Shigeru Atsumi , Masao Kuriyama , Akira Umezawa , Hironori Banba , Tadayuki Taura , Hidetoshi Saito
IPC分类号： H03K522
CPC分类号： G11C5/143 , G11C5/14 , G11C7/1045 , G11C16/26 , G11C16/30
摘要： A semiconductor integrated circuit device has a data storage section for storing mode setting data corresponding to products of a plurality of types, redundancy data, and so on. The redundancy storage section is made up of a nonvolatile transistor for storing the mode setting data corresponding to the products, the redundancy data, etc., a latch circuit for latching data read out from the nonvolatile transistor and generating a mode signal, and a transmission gate for transmitting the data from read out from the nonvolatile transistor to the latch circuit. The semiconductor integrated circuit device also has an internal voltage generator for generating an internal voltage. This internal voltage is used as the power supply voltage of the data storage section.
摘要翻译：半导体集成电路装置具有用于存储对应于多种类型，冗余数据等的产品的模式设置数据的数据存储部分。冗余存储部分由用于存储对应于产品，冗余数据等的模式设置数据的非易失性晶体管，用于锁存从非易失性晶体管读出的数据并产生模式信号的锁存电路，以及传输用于将从非易失性晶体管读出的数据发送到锁存电路。半导体集成电路器件还具有用于产生内部电压的内部电压发生器。该内部电压用作数据存储部分的电源电压。

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