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1. 发明授权

US06972446B1 Semiconductor integrated circuit device and flash EEPROM 失效
标题翻译：半导体集成电路器件和闪存EEPROM
公开(公告)号：US06972446B1
公开(公告)日：2005-12-06
申请号：US09028276
申请日：1998-02-24
申请人： Shigeru Atsumi
发明人： Shigeru Atsumi
IPC分类号： H01L21/8247 , G11C16/26 , H01L21/8239 , H01L27/10 , H01L27/105 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/105 , G11C16/26 , H01L27/1052
摘要： A number of transistors including gate oxide films of different thicknesses and an external terminal are formed on a semiconductor substrate. The transistor connected directly to the external terminal is a transistor other than the transistor having the thinnest gate oxide film. That is, a node which is in contact with an external power supply and thus requires a high breakdown voltage is formed of a thick gate oxide film transistor, while a node which is not in contact with the external power supply is formed of a thin gate oxide film transistor. With this structure, a number of transistors including gate oxide films of different thicknesses can be integrated in a single chip without deterioration of the transistor characteristics. Hence, the degree of freedom with which to design devices/circuits can be remarkably enhanced.
摘要翻译：在半导体衬底上形成包括不同厚度的栅极氧化物膜和外部端子的多个晶体管。直接连接到外部端子的晶体管是具有最薄栅极氧化膜的晶体管以外的晶体管。也就是说，与外部电源接触并且因此需要高的击穿电压的节点由厚栅极氧化物膜晶体管形成，而与外部电源不接触的节点由薄栅极形成氧化膜晶体管。利用这种结构，可以在单个芯片中集成多个不同厚度的栅极氧化膜的晶体管，而不会降低晶体管特性。因此，可以显着提高设计装置/电路的自由度。

2. 发明申请

US20050117406A1 Semiconductor integrated circuit device with main cell array and fuse cell array 失效
标题翻译：具有主单元阵列和熔丝单元阵列的半导体集成电路器件
公开(公告)号：US20050117406A1
公开(公告)日：2005-06-02
申请号：US11033398
申请日：2005-01-12
申请人： Shigeru Atsumi , Masao Kuriyama , Akira Umezawa , Hironori Banba , Tadayuki Taura , Hidetoshi Saito
发明人： Shigeru Atsumi , Masao Kuriyama , Akira Umezawa , Hironori Banba , Tadayuki Taura , Hidetoshi Saito
IPC分类号： G11C5/00 , G11C5/14 , G11C16/04 , H01L29/78 , H03K5/153 , H03K5/22
CPC分类号： G11C5/143 , G11C5/14 , G11C7/1045 , G11C16/26 , G11C16/30
摘要： A semiconductor integrated circuit device includes a main cell array, a fuse cell array, main cell word lines arranged at the main cell array, and fuse cell word lines arranged at the fuse cell array. The fuse cell word lines are formed in a same direction as a direction of the main cell word lines.
摘要翻译：半导体集成电路器件包括主单元阵列，熔丝单元阵列，布置在主单元阵列处的主单元字线以及布置在熔丝单元阵列处的熔丝单元字线。熔丝单元字线形成在与主单元字线的方向相同的方向上。

3. 发明申请

US20050111269A1 Semiconductor memory with nonvolatile memory cell array and semiconductor device with nonvolatile memory cell array and logic device 有权
标题翻译：具有非易失性存储单元阵列的半导体存储器和具有非易失性存储单元阵列和逻辑器件的半导体器件
公开(公告)号：US20050111269A1
公开(公告)日：2005-05-26
申请号：US10661520
申请日：2003-09-15
申请人： Seiichi Mori , Shigeru Atsumi
发明人： Seiichi Mori , Shigeru Atsumi
IPC分类号： G11C16/04 , H01L21/8247 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792 , G11C7/00
CPC分类号： H01L27/11521 , G11C16/0416 , H01L27/115
摘要： A semiconductor device at least has a memory cell array. The memory cell array has active regions extending linearly in parallel with one another at predetermined intervals and each containing alternating source and drain regions, gate electrodes orthogonally crossing the active regions between the source and drain regions and each having a floating gate and a control gate laid one upon another, first conductors extending linearly in parallel with the gate electrodes and connected to corresponding ones of the source regions through source contacts, and second conductors connected to corresponding ones of the drain regions through drain contacts.
摘要翻译：半导体器件至少具有存储单元阵列。存储单元阵列具有以预定间隔彼此平行地线性延伸的有源区，并且每个包含交替的源极和漏极区，栅电极正交地与源极和漏极区之间的有源区相交，并且每个具有浮置栅极和控制栅极一个接一个地，第一导体与栅电极平行延伸并且通过源触点连接到相应的源极区，并且通过漏极触点连接到相应的漏区。

4. 发明授权

US06888764B2 Semiconductor device including semiconductor memory 失效
标题翻译：包括半导体存储器的半导体器件
公开(公告)号：US06888764B2
公开(公告)日：2005-05-03
申请号：US10231283
申请日：2002-08-30
申请人： Hitoshi Shiga , Tadayuki Taura , Shigeru Atsumi
发明人： Hitoshi Shiga , Tadayuki Taura , Shigeru Atsumi
IPC分类号： G01R31/28 , G11C16/02 , G11C16/06 , G11C17/00 , G11C29/00 , G11C29/04 , G11C29/10 , G11C29/12 , G11C7/00
CPC分类号： G11C29/76 , G11C16/04 , G11C2029/1802
摘要： A semiconductor device has an address counter to output, in a first mode, a first block address whereas, in a second mode, a second block address selected from a block-address space two times larger than a block-address space corresponding to memory blocks, the memory blocks and at least one redundant block being included in a memory section, and a block-selection controller, in the second mode, one of the memory blocks, which corresponds to the output of the address counter, when the most significant value of the second block address as the output of the address counter is at a first level whereas select the redundant block while the memory blocks are inhibited from selection, when the most significant value is at a second level.
摘要翻译：半导体器件具有地址计数器，以第一模式输出第一块地址，而在第二模式中，从与存储块对应的块地址空间大2倍的块地址空间中选择第二块地址存储器块和至少一个冗余块被包括在存储器部分中，以及块选择控制器，在第二模式中，当最大有效值时对应于地址计数器的输出的存储块之一作为地址计数器的输出的第二块地址处于第一级，而当最高有效值处于第二级时，选择该冗余块而存储块被禁止选择。

5. 发明授权

US06850437B2 Nonvolatile semiconductor memory device and method of retrieving faulty in the same 失效
标题翻译：非易失性半导体存储器件及其检测方法相同
公开(公告)号：US06850437B2
公开(公告)日：2005-02-01
申请号：US10781921
申请日：2004-02-20
申请人： Tadayuki Taura , Shigeru Atsumi , Toru Tanzawa
发明人： Tadayuki Taura , Shigeru Atsumi , Toru Tanzawa
IPC分类号： G01R1/06 , G01R31/28 , G11C16/02 , G11C16/06 , G11C16/20 , G11C17/00 , G11C29/00 , G11C29/04 , G11C29/34
CPC分类号： G11C29/846 , G11C16/20 , G11C2029/1208
摘要： A nonvolatile semiconductor memory device includes a first memory cell array including electrically re-programmable main memory cells, a second memory cell array including electrically data-programmable redundancy memory cells, a first storage configured to store a specified code, a first comparator configured to compare a selected code with the specified code to generate an activating signal, a faulty address latch circuit configured to be activated by the activating signal and controlled to temporarily latch a fault address corresponding to the fault, a second storage configured to store the faulty address latched by the faulty address latch circuit, a second comparator configured to compare an input address with the faulty address to generate a replacement control signal when the input address coincides with the faulty address, and a replacing circuit configured to replace an output of the first memory cell array with an output of the second memory cell array.
摘要翻译：非易失性半导体存储器件包括包括电可重新编程的主存储器单元的第一存储单元阵列，包括电数据可编程冗余存储器单元的第二存储单元阵列，被配置为存储指定代码的第一存储器，配置为比较的第一比较器具有指定代码的选择代码以产生激活信号，故障地址锁存电路被配置为由激活信号激活并被控制以临时锁存与该故障相对应的故障地址;第二存储器，被配置为存储由该故障锁存的故障地址故障地址锁存电路，第二比较器，被配置为当输入地址与故障地址一致时，将输入地址与故障地址进行比较，以产生替换控制信号;以及替换电路，被配置为替换第一存储单元阵列的输出具有第二存储单元阵列的输出。

6. 发明授权

US06801457B2 Non-volatile semiconductor memory 失效
公开(公告)号：US06801457B2
公开(公告)日：2004-10-05
申请号：US10665014
申请日：2003-09-22
申请人： Toru Tanzawa , Shigeru Atsumi
发明人： Toru Tanzawa , Shigeru Atsumi
IPC分类号： G11C1604
CPC分类号： G11C11/5635 , G11C7/06 , G11C7/1006 , G11C11/5628 , G11C11/5642 , G11C16/28 , G11C16/344 , G11C2211/5641 , G11C2211/565
摘要： A non-volatile semiconductor memory comprises a memory cell array having a plurality of non-volatile memory cells, at least one reference cell, a read circuit for reading data by applying a first voltage to one of word lines to compare a current flowing through one of bit lines with a current flowing through the reference cell, an erase circuit for erasing the data by applying a voltage to at least two selected from the word lines, the bit lines, the source lines and a semiconductor region including the memory cells, first and second regulators, and an erase verify circuit for detecting whether the erase has finished by applying an output voltage of the first regulator to word lines of the memory cells to be erased, while applying an output voltage of the second regulator to a word line of the reference cell, thereby comparing a cell current of selected one of the memory cells with a cell current of the reference cell.

7. 发明授权

US06711057B2 Nonvolatile semiconductor memory device and method of retrieving faulty in the same 失效
标题翻译：非易失性半导体存储器件及其检测方法相同
公开(公告)号：US06711057B2
公开(公告)日：2004-03-23
申请号：US10234704
申请日：2002-09-05
申请人： Tadayuki Taura , Shigeru Atsumi , Toru Tanzawa
发明人： Tadayuki Taura , Shigeru Atsumi , Toru Tanzawa
IPC分类号： G11C1606
CPC分类号： G11C29/846 , G11C16/20 , G11C2029/1208
摘要： A nonvolatile semiconductor memory device comprises a first memory cell array including electrically re-programmable main memory cells, a second memory cell array including electrically data-programmable redundancy memory cells, a first storage configured to store a specified code, a first comparator configured to compare a selected code with the specified code to generate an activating signal, a faulty address latch circuit configured to be activated by the activating signal and controlled to temporarily latch a fault address corresponding to the fault, a second storage configured to store the faulty address latched by the faulty address latch circuit, a second comparator configured to compare an input address with the faulty address to generate a replacement control signal when the input address coincides with the faulty address, and a replacing circuit configured to replace an output of the first memory cell array with an output of the second memory cell array.
摘要翻译：非易失性半导体存储器件包括包括电可重新编程的主存储器单元的第一存储单元阵列，包括电数据可编程冗余存储器单元的第二存储单元阵列，被配置为存储指定代码的第一存储器，被配置为比较的第一比较器具有指定代码的选择代码以产生激活信号，故障地址锁存电路被配置为由激活信号激活并被控制以临时锁存与该故障相对应的故障地址;第二存储器，被配置为存储由该故障锁存的故障地址故障地址锁存电路，第二比较器，被配置为当输入地址与故障地址一致时，将输入地址与故障地址进行比较，以产生替换控制信号;以及替换电路，被配置为替换第一存储单元阵列的输出具有第二存储单元阵列的输出。

8. 发明授权

US06671203B2 Nonvolatile semiconductor memory having page mode with a plurality of banks 有权
标题翻译：具有多个存储体的页面模式的非易失性半导体存储器
公开(公告)号：US06671203B2
公开(公告)日：2003-12-30
申请号：US10233133
申请日：2002-08-30
申请人： Toru Tanzawa , Shigeru Atsumi , Akira Umezawa , Tadayuki Taura , Hitoshi Shiga , Yoshinori Takano
发明人： Toru Tanzawa , Shigeru Atsumi , Akira Umezawa , Tadayuki Taura , Hitoshi Shiga , Yoshinori Takano
IPC分类号： G11C1604
CPC分类号： G11C16/0408 , G11C16/08 , G11C16/26 , G11C29/70
摘要： A nonvolatile semiconductor memory includes first and second nonvolatile memory banks, a data-line for read, a data-line for program and verify, a sense amplifier for read, a sense amplifier for program and verify, and a program circuit. The data-lines are arranged in a region between the first and second nonvolatile memory banks, and selectively connected to the bit-lines of the first and second nonvolatile memory banks. The sense amplifier for read is connected to the data-line for read. The sense amplifier for program and verify and the program circuit are connected to the data-line for program and verify.
摘要翻译：非易失性半导体存储器包括第一和第二非易失性存储器组，用于读取的数据线，用于编程和验证的数据线，用于读取的读出放大器，用于编程和验证的读出放大器以及程序电路。数据线布置在第一和第二非易失性存储体之间的区域中，并且选择性地连接到第一和第二非易失性存储体的位线。用于读取的读出放大器连接到数据线进行读取。用于程序和验证的读出放大器和程序电路连接到数据线进行程序和验证。

9. 发明授权

US06560144B2 Nonvolatile semiconductor memory device 失效
标题翻译：非易失性半导体存储器件
公开(公告)号：US06560144B2
公开(公告)日：2003-05-06
申请号：US10086869
申请日：2002-03-04
申请人： Shigeru Atsumi , Hironori Banba
发明人： Shigeru Atsumi , Hironori Banba
IPC分类号： G11C1604
CPC分类号： G11C16/16 , G11C16/08
摘要： A nonvolatile semiconductor memory device includes a row decoder circuit having first and second N-channel MOS transistors and first and second P-channel MOS transistors which correspond to each of word lines. One end of a source-to-drain current path of the first N-channel MOS transistor is connected to the word line, and the other end thereof is connected to a corresponding one of output terminals of a predecoder circuit. One end of a source-to-drain current path of the second N-channel MOS transistor is connected to the word line, and the other end thereof is supplied with a voltage of OV or more in a data erase mode and is supplied with a low logical level signal in modes other than the data erase mode. A source-to-drain current path of the first P-channel MOS transistor is connected in parallel to the source-to-drain current path of the first N-channel MOS transistor, and a source-to-drain current path of the second P-channel MOS transistor is connected in parallel to the source-to-drain current path of the second N-channel MOS transistor.
摘要翻译：非易失性半导体存储器件包括具有第一和第二N沟道MOS晶体管的行解码器电路和对应于每条字线的第一和第二P沟道MOS晶体管。第一N沟道MOS晶体管的源极 - 漏极电流路径的一端连接到字线，并且其另一端连接到预解码器电路的对应的一个输出端。第二N沟道MOS晶体管的源极 - 漏极电流路径的一端连接到字线，并且其另一端在数据擦除模式下被提供0V以上的电压，并被提供有低数据擦除模式以外的模式下的低逻辑电平信号。第一P沟道MOS晶体管的源极 - 漏极电流路径并联连接到第一N沟道MOS晶体管的源极 - 漏极电流路径，并且第二P沟道MOS晶体管的源极 - 漏极电流路径 P沟道MOS晶体管与第二N沟道MOS晶体管的源极 - 漏极电流路径并联连接。

10. 发明授权

US06498761B2 Power supply circuit and semiconductor memory device having the same 失效
公开(公告)号：US06498761B2
公开(公告)日：2002-12-24
申请号：US09983258
申请日：2001-10-23
申请人： Hironori Banba , Shigeru Atsumi
发明人： Hironori Banba , Shigeru Atsumi
IPC分类号： G11C700
CPC分类号： G11C16/30 , G11C5/145 , H02M3/073
摘要： A number of booster circuits to be operated out of a plurality of booster circuits are selected in accordance with a level of the boosted voltage to be provided at a common voltage output terminal of the plurality of booster circuits. With such an arrangement, fluctuations in the output voltage that can appear when a light load is applied to the voltage output terminal of the booster circuits can be effectively reduced to make the semiconductor memory device driven by the power supply circuit operate reliably. Further, one of the output terminals of intermediate voltage booster circuits is connected to the output terminal of a high voltage booster circuit. Then, a desired voltage can be obtained from the booster circuits that are implemented without using costly transistors to reduce the chip cost.

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