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11. 发明授权

US5572703A Method and apparatus for snoop stretching using signals that convey snoop results 失效
标题翻译：使用传达窥探结果的信号进行窥探伸展的方法和装置
公开(公告)号：US5572703A
公开(公告)日：1996-11-05
申请号：US203802
申请日：1994-03-01
申请人： Peter MacWilliams , Nitin V. Sarangdhar , Matthew Fisch , Amit Merchant
发明人： Peter MacWilliams , Nitin V. Sarangdhar , Matthew Fisch , Amit Merchant
IPC分类号： G06F12/08 , G06F13/14
CPC分类号： G06F12/0831
摘要： A protocol and related apparatus for snoop stretching in a computer system having at least one requesting agent for issuing bus transaction requests and at least one snooping agent for monitoring transaction requests and issuing bus signals onto an external bus. The bus transactions are timed by a bus clock signal having a plurality of cycles. To indicate snoop stretching, during a first cycle a first snooping agent asserts both a HIT# bus signal and a HITM# bus signal together to indicate that the first snooping agent must delay assertion of valid snoop results for a predetermined snoop period. During a later cycle, to indicate the end of the snoop stretch, the first snooping agent deasserts the assertion of both the HIT# and HITM# signals together and asserts its valid snoop results. The HIT# and HITM# signals alone each represent valid snoop results. If the first snooping agent must continue delaying assertion of valid snoop results, then it reasserts both the HIT# and HITM# bus signals together for the predetermined snoop period. If a second snooping agent is ready to assert its valid snoop results, it will do so while the first snooping agent causes a snoop stretch, and will reassert its valid snoop results up to and including the cycle that the first snooping agent deasserts it snoop stretch and asserts its own valid snoop results.
摘要翻译：一种用于在具有发出总线事务请求的至少一个请求代理的计算机系统中的窥探扩展的协议和相关装置，以及用于监视事务请求和向总线信号发出总线信号的至少一个侦听代理。总线事务由具有多个周期的总线时钟信号定时。为了指示窥探伸展，在第一周期期间，第一窥探代理将HIT＃总线信号和HITM＃总线信号一起断言，以指示第一侦听代理必须在预定的窥探期间延迟有效窥探结果的断言。在稍后的循环中，为了指示窥探伸展的结束，第一次窥探代理将HIT＃和HITM＃信号的断言声明为一致，并断言其有效的窥探结果。 HIT＃和HITM＃信号单独表示有效的窥探结果。如果第一个窥探代理人必须继续延迟有效的窥探结果的断言，则在预定的窥探期间，它将HIT＃和HITM＃总线信号一起重新提供。如果第二个侦听代理程序准备好声明其有效的侦听结果，则会在第一个侦听代理程序导致侦听扩展时执行此操作，并将重新发送其有效的侦听结果，直到并包括第一个侦听代理程序将其忽略的循环snoop stretch 并声明自己有效的窥探结果。

12. 发明授权

US5572702A Method and apparatus for supporting read, write, and invalidation operations to memory which maintain cache consistency 失效
公开(公告)号：US5572702A
公开(公告)日：1996-11-05
申请号：US202790
申请日：1994-02-28
申请人： Nitin V. Sarangdhar , Michael W. Rhodehamel , Amit A. Merchant , Matthew A. Fisch , James M. Brayton
发明人： Nitin V. Sarangdhar , Michael W. Rhodehamel , Amit A. Merchant , Matthew A. Fisch , James M. Brayton
IPC分类号： G06F12/08 , G06F13/16 , G06F13/14
CPC分类号： G06F12/0831 , G06F12/0833 , G06F13/1668
摘要： Requests to memory issued by an agent on a bus are satisfied while maintaining cache consistency. The requesting agent may issue a request to another agent, or the memory unit, by placing the request on the bus. Each agent on the bus snoops the bus to determine whether the issued request can be satisfied by accessing its cache. An agent which can satisfy the request using its cache, i.e., the snooping agent, issues a signal to the requesting agent indicating so. The snooping agent places the cache line which corresponds to the request onto the bus, which is retrieved by the requesting agent. In the event of a read request, the memory unit also retrieves the cache line data from the bus and stores the cache line in main memory. In the event of a write request, the requesting agent transfers write data over the bus along with the request. This write data is retrieved by both the memory unit, which temporarily stores the data, and the snooping agent. Subsequently, the snooping agent transfers the entire cache line over the bus. The memory unit retrieves this cache line, merges it with the write data previously stored, and writes the merged cache line to memory.

13. 发明申请

US20170185434A1 VERSATILE INPUT/OUTPUT DEVICE ACCESS FOR VIRTUAL MACHINES 有权
公开(公告)号：US20170185434A1
公开(公告)日：2017-06-29
申请号：US14757417
申请日：2015-12-23
申请人： Nitin V. Sarangdhar , Ioannis Yannis T. Schoinas , Raul Gutierrez , Ravi Kolagotla
发明人： Nitin V. Sarangdhar , Ioannis Yannis T. Schoinas , Raul Gutierrez , Ravi Kolagotla
IPC分类号： G06F9/455 , G06F13/28 , G06F13/10
CPC分类号： G06F9/45558 , G06F9/4411 , G06F9/5077 , G06F13/102 , G06F13/28 , G06F2009/45579 , G06F2009/45587
摘要： Embodiments are directed to managing access to input/output devices by virtual machines (VMs). A first VM and a second VM are implemented. An I/O device controller driver has a first driver portion in the first VM and a second driver portion in the second VM. The first driver portion includes a configuration engine to configure the I/O device controller with I/O device-VM mappings, where a first I/O device is mapped exclusively to the first VM, and a second I/O device is mapped to at least the second VM. The second VM includes a general processing engine to call for I/O devices via the second driver portion, and in response to a call by the general processing engine for access to the first I/O device the second driver portion is to send an access request to the first driver portion.

14. 发明授权

US08954747B2 Protecting keystrokes received from a keyboard in a platform containing embedded controllers 有权
标题翻译：保护从包含嵌入式控制器的平台中的键盘接收的按键
公开(公告)号：US08954747B2
公开(公告)日：2015-02-10
申请号：US13174857
申请日：2011-07-01
申请人： Nitin V. Sarangdhar , Jasmeet Chhabra
发明人： Nitin V. Sarangdhar , Jasmeet Chhabra
IPC分类号： G06F11/30 , G06F21/83
CPC分类号： G06F21/83
摘要： Systems and methods of managing keystroke data in embedded keyboard environments may involve transferring a mode request from a management controller to an embedded controller of a keyboard via a dedicated communication channel. Keystroke activity can be detected at the keyboard, and keystroke data may be transferred from the embedded controller to the management controller via the dedicated communication channel in response to the keystroke activity and the mode request. In addition, the management controller may be used to encrypt the keystroke data, wherein the encrypted keystroke data can be transmitted from the management controller to an off-platform service via a network controller.
摘要翻译：在嵌入式键盘环境中管理按键数据的系统和方法可以涉及经由专用通信信道将模式请求从管理控制器传送到键盘的嵌入式控制器。可以在键盘上检测到击键活动，并且响应于击键活动和模式请求，按键击数据可以经由专用通信信道从嵌入式控制器传送到管理控制器。此外，管理控制器可以用于加密按键数据，其中可以经由网络控制器将加密的击键数据从管理控制器发送到离线服务。

15. 发明授权

US5903738A Method and apparatus for performing bus transactions in a computer system 失效
标题翻译：用于在计算机系统中执行总线事务的方法和装置
公开(公告)号：US5903738A
公开(公告)日：1999-05-11
申请号：US715049
申请日：1996-09-17
申请人： Nitin V. Sarangdhar , Konrad K. Lai , Gurbir Singh
发明人： Nitin V. Sarangdhar , Konrad K. Lai , Gurbir Singh
IPC分类号： G06F13/368 , G06F13/37 , G06F13/42 , G06F3/00
CPC分类号： G06F13/4213 , G06F13/368 , G06F13/37
摘要： A method and apparatus of performing bus transactions on the external bus of the computer system. The present invention includes a method and apparatus for permitting out-of-order replies in a pipelined bus system. The out-of-order responses include the sending of tokens between both the requesting agents and the responding agents in the computer system without the use of dedicated token buses.
摘要翻译：一种在计算机系统的外部总线上执行总线事务的方法和装置。本发明包括一种用于允许流水线总线系统中的无序回复的方法和装置。无序响应包括在计算机系统中的请求代理和响应代理之间发送令牌，而不使用专用令牌总线。

16. 发明授权

US5797026A Method and apparatus for self-snooping a bus during a boundary transaction 失效
标题翻译：在边界交易过程中自动侦听总线的方法和装置
公开(公告)号：US5797026A
公开(公告)日：1998-08-18
申请号：US921845
申请日：1997-09-02
申请人： Michael W. Rhodehamel , Nitin V. Sarangdhar , Amit A. Merchant , Matthew A. Fisch , James M. Brayton
发明人： Michael W. Rhodehamel , Nitin V. Sarangdhar , Amit A. Merchant , Matthew A. Fisch , James M. Brayton
IPC分类号： G06F12/08 , G06F13/00
CPC分类号： G06F12/0831
摘要： A self-snooping mechanism for enabling a processor being coupled to dedicated cache memory and a processor-system bus to snoop its own request issued on the processor-system bus. The processor-system bus enables communication between the processor and other bus agents such as a memory subsystem, I/O subsystem and/or other processors. The self-snooping mechanism is commenced upon determination that the request is based on a boundary condition so that initial internal cache lookup is bypassed to improve system efficiency.
摘要翻译：一种用于使处理器耦合到专用高速缓存存储器和处理器系统总线的自侦听机制，以窥探其在处理器系统总线上发出的自身请求。处理器系统总线实现处理器与其它总线代理（例如存储器子系统，I / O子系统和/或其他处理器）之间的通信。自我侦听机制在确定请求是基于边界条件的情况下开始，以便绕过初始内部高速缓存查找以提高系统效率。

17. 发明授权

US5682516A Computer system that maintains system wide cache coherency during deferred communication transactions 失效
标题翻译：计算机系统在延迟通信事务期间维持系统级缓存一致性
公开(公告)号：US5682516A
公开(公告)日：1997-10-28
申请号：US205023
申请日：1994-03-01
申请人： Nitin V. Sarangdhar , Wen Han Wang , Michael W. Rhodehamel , James M. Brayton , Amit Merchant , Matthew A. Fisch
发明人： Nitin V. Sarangdhar , Wen Han Wang , Michael W. Rhodehamel , James M. Brayton , Amit Merchant , Matthew A. Fisch
IPC分类号： G06F12/08 , G06F13/368 , H04L29/06 , G06F13/18
CPC分类号： G06F12/0831 , G06F13/368 , H04L29/06 , G06F12/0813
摘要： A computer system is disclosed having a requesting bus agent that issues a communication transaction over a bus and an addressed bus agent that defers the communication transaction to avoid high bus latency. The addressed bus agent later issues a deferred reply transaction over the bus to complete the communication transaction. Special snoop ownership and cache state transition rules maintain cache coherency and processor consistency during deferred communication transactions.
摘要翻译：公开了一种计算机系统，其具有通过总线发布通信事务的请求总线代理和用于延迟通信事务以避免高总线等待时间的寻址总线代理。所处理的总线代理商随后通过总线发出延迟回复交易，以完成通信交易。特殊侦听所有权和缓存状态转换规则在延迟通信事务期间保持缓存一致性和处理器一致性。

18. 发明授权

US5551005A Apparatus and method of handling race conditions in mesi-based multiprocessor system with private caches 失效
标题翻译：在具有私有高速缓存的基于Mesi的多处理器系统中处理竞争条件的装置和方法
公开(公告)号：US5551005A
公开(公告)日：1996-08-27
申请号：US201854
申请日：1994-02-25
申请人： Nitin V. Sarangdhar , Wen-Hann Wang , Matthew Fisch
发明人： Nitin V. Sarangdhar , Wen-Hann Wang , Matthew Fisch
IPC分类号： G06F12/08
CPC分类号： G06F12/0808 , G06F12/0831
摘要： In a computer system having a plurality of processors with internal caches, a method for handling race conditions arising when multiple processors simultaneously write to a particular cache line. Initially, a determination is made as to whether the cache line is in an exclusive, modified, invalid, or shared state. If the cache line is in either the exclusive or modified state, the cache line is written to and then set to the modified state. If the cache line is in the invalid state, a Bus-Read-Invalidate operation is performed. However, if the cache line is in the shared state and multiple processors initiate Bus-Write-Invalidate operations, the invalidation request belonging to the first processor is allowed to complete. Thereupon, the cache line is sent to the exclusive state, data is updated, and the cache line is set to the modified state. The second processor receives a second cache line, updates this second cache line, and sets the second cache line to the modified state.
摘要翻译：在具有多个具有内部高速缓存的处理器的计算机系统中，一种用于处理当多个处理器同时写入特定高速缓存行时产生的竞争条件的方法。首先，确定高速缓存行是否处于排他，修改，无效或共享状态。如果缓存行处于独占状态或修改状态，则将高速缓存行写入并设置为修改状态。如果缓存行处于无效状态，则执行总线读取无效操作。然而，如果高速缓存行处于共享状态，并且多个处理器启动总线写入无效操作，则允许属于第一处理器的无效请求完成。于是缓存行被发送到独占状态，数据被更新，高速缓存行被设置为修改状态。第二处理器接收第二高速缓存行，更新第二高速缓存行，并将第二高速缓存行设置为修改状态。

19. 发明授权

US5550988A Apparatus and method for performing error correction in a multi-processor system 失效
标题翻译：用于在多处理器系统中执行纠错的装置和方法
公开(公告)号：US5550988A
公开(公告)日：1996-08-27
申请号：US205604
申请日：1994-03-01
申请人： Nitin V. Sarangdhar , Konrad K. Lai
发明人： Nitin V. Sarangdhar , Konrad K. Lai
IPC分类号： G06F11/14 , G06F13/36
CPC分类号： G06F13/36 , G06F11/1402
摘要： In a multi-processor system having a first processor, a second processor, and a bus coupling the first processor to the second processor, a method for correcting an erroneous signal corresponding to the first processor while maintaining lock atomicity. When an erroneous transaction is detected, the first processor aborts that transaction and performs a retry. On the retry, an arbitration process arbitrates between the first processor and the second processor to determine which processor is granted access to the bus. If an error is detected during the arbitration process, an arbitration re-synchronization process is initiated. In the arbitration re-synchronization process, bus requests are de-asserted and then re-arbitrated. In the re-arbitration process, the first processor initiates its request ahead of the other processor in order to maintain lock atomicity.
摘要翻译：在具有第一处理器，第二处理器和将第一处理器耦合到第二处理器的总线的多处理器系统中，一种用于在保持锁原子性的同时校正与第一处理器相对应的错误信号的方法。当检测到错误的事务时，第一处理器中止该事务并执行重试。在重试时，仲裁过程在第一处理器和第二处理器之间进行仲裁以确定哪个处理器被授权访问总线。如果在仲裁过程中检测到错误，则启动仲裁重新同步过程。在仲裁重新同步过程中，总线请求被取消断言，然后重新仲裁。在重新仲裁过程中，第一个处理器在另一个处理器之前发起其请求，以保持锁定原子性。

20. 发明申请

US20150278003A1 PROTECTING A MEMORY DEVICE FROM BECOMING UNUSABLE 有权
标题翻译：保护存储设备免于不可用
公开(公告)号：US20150278003A1
公开(公告)日：2015-10-01
申请号：US14229345
申请日：2014-03-28
申请人： Nitin V. Sarangdhar , Sudhakar Otturu
发明人： Nitin V. Sarangdhar , Sudhakar Otturu
IPC分类号： G06F11/07
CPC分类号： G06F11/0787 , G06F11/073 , G06F11/0775
摘要： In an embodiment, a computing device may include a memory device that may be rendered unusable after a certain number of operations are performed on the memory device. The computing device may incorporate one or more techniques for protecting the memory device. Processing logic contained in the computing device may be configured to implement the techniques. The techniques may include, for example, acquiring a request to write or erase information stored in a memory device contained in a first computing device, saving the request for execution after a user visible event has been generated on the first computing device, generating the user visible event on the first computing device, and executing the saved request after the user visible event has been generated. In addition, the techniques may include reporting the request. The request may be reported to, for example, an anti-malware agent.
摘要翻译：在一个实施例中，计算设备可以包括可以在对存储器设备执行一定数量的操作之后使其不可用的存储器设备。计算设备可以包括用于保护存储器设备的一种或多种技术。包含在计算设备中的处理逻辑可以被配置为实现这些技术。技术可以包括例如获取写入或擦除存储在包含在第一计算设备中的存储器设备中的信息的请求，在第一计算设备上已经生成用户可见事件之后保存执行请求，生成用户在第一计算设备上的可见事件，以及在生成用户可见事件之后执行保存的请求。此外，技术可以包括报告请求。该请求可以被报告给例如反恶意软件代理。

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