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1. 发明授权

US5572702A Method and apparatus for supporting read, write, and invalidation operations to memory which maintain cache consistency 失效
公开(公告)号：US5572702A
公开(公告)日：1996-11-05
申请号：US202790
申请日：1994-02-28
申请人： Nitin V. Sarangdhar , Michael W. Rhodehamel , Amit A. Merchant , Matthew A. Fisch , James M. Brayton
发明人： Nitin V. Sarangdhar , Michael W. Rhodehamel , Amit A. Merchant , Matthew A. Fisch , James M. Brayton
IPC分类号： G06F12/08 , G06F13/16 , G06F13/14
CPC分类号： G06F12/0831 , G06F12/0833 , G06F13/1668
摘要： Requests to memory issued by an agent on a bus are satisfied while maintaining cache consistency. The requesting agent may issue a request to another agent, or the memory unit, by placing the request on the bus. Each agent on the bus snoops the bus to determine whether the issued request can be satisfied by accessing its cache. An agent which can satisfy the request using its cache, i.e., the snooping agent, issues a signal to the requesting agent indicating so. The snooping agent places the cache line which corresponds to the request onto the bus, which is retrieved by the requesting agent. In the event of a read request, the memory unit also retrieves the cache line data from the bus and stores the cache line in main memory. In the event of a write request, the requesting agent transfers write data over the bus along with the request. This write data is retrieved by both the memory unit, which temporarily stores the data, and the snooping agent. Subsequently, the snooping agent transfers the entire cache line over the bus. The memory unit retrieves this cache line, merges it with the write data previously stored, and writes the merged cache line to memory.

2. 发明授权

US5797026A Method and apparatus for self-snooping a bus during a boundary transaction 失效
标题翻译：在边界交易过程中自动侦听总线的方法和装置
公开(公告)号：US5797026A
公开(公告)日：1998-08-18
申请号：US921845
申请日：1997-09-02
申请人： Michael W. Rhodehamel , Nitin V. Sarangdhar , Amit A. Merchant , Matthew A. Fisch , James M. Brayton
发明人： Michael W. Rhodehamel , Nitin V. Sarangdhar , Amit A. Merchant , Matthew A. Fisch , James M. Brayton
IPC分类号： G06F12/08 , G06F13/00
CPC分类号： G06F12/0831
摘要： A self-snooping mechanism for enabling a processor being coupled to dedicated cache memory and a processor-system bus to snoop its own request issued on the processor-system bus. The processor-system bus enables communication between the processor and other bus agents such as a memory subsystem, I/O subsystem and/or other processors. The self-snooping mechanism is commenced upon determination that the request is based on a boundary condition so that initial internal cache lookup is bypassed to improve system efficiency.
摘要翻译：一种用于使处理器耦合到专用高速缓存存储器和处理器系统总线的自侦听机制，以窥探其在处理器系统总线上发出的自身请求。处理器系统总线实现处理器与其它总线代理（例如存储器子系统，I / O子系统和/或其他处理器）之间的通信。自我侦听机制在确定请求是基于边界条件的情况下开始，以便绕过初始内部高速缓存查找以提高系统效率。

3. 发明授权

US5909699A Method and apparatus for supporting read, write, and invalidation operations to memory which maintain cache consistency 失效
标题翻译：用于支持对存储器进行读取，写入和无效操作的方法和装置，其保持缓存一致性
公开(公告)号：US5909699A
公开(公告)日：1999-06-01
申请号：US672422
申请日：1996-06-28
申请人： Nitin V. Sarangdhar , Michael W. Rhodehamel , Amit A. Merchant , Matthew A. Fisch , James M. Brayton
发明人： Nitin V. Sarangdhar , Michael W. Rhodehamel , Amit A. Merchant , Matthew A. Fisch , James M. Brayton
IPC分类号： G06F12/08 , G06F13/16 , G06F13/14
CPC分类号： G06F12/0831 , G06F12/0833 , G06F13/1668
摘要： Requests to memory issued by an agent on a bus are satisfied while maintaining cache consistency. The requesting agent may issue a request to another agent, or the memory unit, by placing the request on the bus. Each agent on the bus snoops the bus to determine whether the issued request can be satisfied by accessing its cache. An agent which can satisfy the request using its cache, i.e., the snooping agent, issues a signal to the requesting agent indicating so. The snooping agent places the cache line which corresponds to the request onto the bus, which is retrieved by the requesting agent. In the event of a read request, the memory unit also retrieves the cache line data from the bus and stores the cache line in main memory. In the event of a write request, the requesting agent transfers write data over the bus along with the request. This write data is retrieved by both the memory unit, which temporarily stores the data, and the snooping agent. Subsequently, the snooping agent transfers the entire cache line over the bus. The memory unit retrieves this cache line, merges it with the write data previously stored, and writes the merged cache line to memory.
摘要翻译：总线上代理发出的内存请求在保持缓存一致性的同时得到满足。请求代理可以通过将请求放在总线上向另一代理或存储器单元发出请求。总线上的每个代理都会窥探总线，以确定是否可以通过访问其缓存来满足发出的请求。可以使用其缓存来满足请求的代理，即窥探代理，向请求代理发出指示这样的信号。侦听代理将与请求相对应的高速缓存行放置在由请求代理检索到的总线上。在读取请求的情况下，存储器单元还从总线检索高速缓存线数据，并将高速缓存行存储在主存储器中。在写请求的情况下，请求代理随着请求传送总线上的写数据。该写入数据由临时存储数据的存储单元和监听代理二者检索。随后，窥探代理通过总线传输整个高速缓存行。存储器单元检索该高速缓存线，将其与先前存储的写数据合并，并将合并的高速缓存行写入存储器。

4. 发明授权

US06385715B1 Multi-threading for a processor utilizing a replay queue 有权
标题翻译：使用重放队列的处理器的多线程
公开(公告)号：US06385715B1
公开(公告)日：2002-05-07
申请号：US09848423
申请日：2001-05-04
申请人： Amit A. Merchant , Darrell D. Boggs , David J. Sager
发明人： Amit A. Merchant , Darrell D. Boggs , David J. Sager
IPC分类号： G06F1500
CPC分类号： G06F9/383 , G06F9/3838 , G06F9/3842 , G06F9/3851 , G06F9/3863 , G06F9/3869
摘要： A processor is provided that includes an execution unit for executing instructions and a replay system for replaying instructions which have not executed properly. The replay system is coupled to the execution unit and includes a checker for determining whether each instruction has executed properly and a plurality of replay queues or replay queue sections coupled to the checker for temporarily storing one or more instructions for replay. In one embodiment, thread-specific replay queue sections may each be used to store long latency instruction for each thread until the long latency instruction is ready to be executed (e.g., data for a load instruction has been retrieved from external memory). By storing the long latency instruction and its dependents in a replay queue section for one thread which has stalled, execution resources are made available for improving the speed of execution of other threads which have not stalled.
摘要翻译：提供了一种处理器，其包括用于执行指令的执行单元和用于重放未正确执行的指令的重放系统。重播系统耦合到执行单元，并且包括用于确定每个指令是否已正确执行的检查器和耦合到检验器的多个重播队列或重放队列部分，用于临时存储用于重放的一个或多个指令。在一个实施例中，线程特定的重放队列部分可以各自用于存储每个线程的长延时指令，直到长等待时间指令准备执行（例如，已经从外部存储器检索到加载指令的数据）。通过将延迟时间长的指令及其依赖项存储在已停播的一个线程的重放队列部分中，执行资源可用于提高未停滞的其他线程的执行速度。

5. 发明授权

US6163838A Computer processor with a replay system 失效
标题翻译：具有重播系统的计算机处理器
公开(公告)号：US6163838A
公开(公告)日：2000-12-19
申请号：US106857
申请日：1998-06-30
申请人： Amit A. Merchant , David J. Sager , Darrell D. Boggs
发明人： Amit A. Merchant , David J. Sager , Darrell D. Boggs
IPC分类号： G06F9/38 , G06F15/00
CPC分类号： G06F9/383 , G06F9/3838 , G06F9/3842 , G06F9/3851 , G06F9/3863 , G06F9/3869
摘要： A computer processor includes a multiplexer having a first input, a second input, and an output, and a scheduler coupled to the multiplexer first input. The processor further includes an execution unit coupled to the multiplexer output. The execution unit is adapted to receive a plurality of instructions from the multiplexer. The processor further includes a replay system coupled to the second multiplexer input and the scheduler. The replay system replays an instruction that has not correctly executed by sending a stop scheduler signal to the scheduler and sending the instruction to the multiplexer.
摘要翻译：计算机处理器包括具有第一输入，第二输入和输出的多路复用器以及耦合到多路复用器第一输入的调度器。处理器还包括耦合到多路复用器输出的执行单元。执行单元适于从多路复用器接收多个指令。处理器还包括耦合到第二多路复用器输入和调度器的重播系统。重播系统通过向调度器发送停止调度器信号并将指令发送到多路复用器来重放未正确执行的指令。

6. 发明授权

US5875467A Method and apparatus for maintaining cache coherency in a computer system with a highly pipelined bus and multiple conflicting snoop requests 失效
标题翻译：用于在具有高流水线总线和多个冲突窥探请求的计算机系统中维持高速缓存一致性的方法和装置
公开(公告)号：US5875467A
公开(公告)日：1999-02-23
申请号：US826556
申请日：1997-04-04
申请人： Amit A. Merchant
发明人： Amit A. Merchant
IPC分类号： G06F12/08 , G06F13/18
CPC分类号： G06F12/0831 , G06F12/0833
摘要： A method of maintaining cache coherency for snoop operations includes initiating a first snoop operation in response to a snoop request while one or more previous snoop operations are pending in a queue. Furthermore, one or more subsequent snoop operations can be queued, wherein a step of determining if the one or more snoop requests are orthogonal, i.e. the processing of one request is not dependent on the outcome of a previous request, is included. The step of determining if the one or more snoop requests are orthogonal includes utilizing a block bit, a sleep bit, and a plurality of previously pending snoop request bits in a snoop queue entry to determine if the entry is orthogonal or not.
摘要翻译：维持侦听操作的高速缓存一致性的方法包括响应于窥探请求发起第一次窥探操作，而一个或多个先前侦听操作在队列中等待处理。此外，可以对一个或多个后续的窥探操作进行排队，其中包括确定一个或多个窥探请求是否正交的步骤，即一个请求的处理不依赖于先前请求的结果。确定一个或多个窥探请求是否正交的步骤包括在窥探队列条目中利用块比特，睡眠比特和多个先前等待的窥探请求比特来确定该条目是否正交。

7. 发明授权

US07219349B2 Multi-threading techniques for a processor utilizing a replay queue 有权
标题翻译：使用重放队列的处理器的多线程技术
公开(公告)号：US07219349B2
公开(公告)日：2007-05-15
申请号：US10792154
申请日：2004-03-02
申请人： Amit A. Merchant , Darrell D. Boggs , David J. Sager
发明人： Amit A. Merchant , Darrell D. Boggs , David J. Sager
IPC分类号： G06F9/46 , G06F9/40 , G06F15/76
CPC分类号： G06F9/383 , G06F9/3838 , G06F9/3842 , G06F9/3851 , G06F9/3863 , G06F9/3869
摘要： A processor is provided that includes an execution unit for executing instructions and a replay system for replaying instructions which have not executed properly. The replay system is coupled to the execution unit and includes a checker for determining whether each instruction has executed properly and a plurality of replay queues or replay queue sections coupled to the checker for temporarily storing one or more instructions for replay. In one embodiment, thread-specific replay queue sections may each be used to store a long latency instruction for each thread until the long latency instruction is ready to be executed (e.g., data for a load instruction has been retrieved from external memory). By storing the long latency instruction and its dependents in a replay queue section for one thread which has stalled, execution resources are made available for improving the speed of execution of other threads which have not stalled.
摘要翻译：提供了一种处理器，其包括用于执行指令的执行单元和用于重放未正确执行的指令的重放系统。重播系统耦合到执行单元，并且包括用于确定每个指令是否已正确执行的检查器和耦合到检验器的多个重播队列或重放队列部分，用于临时存储用于重放的一个或多个指令。在一个实施例中，线程特定的重播队列部分可以各自用于存储每个线程的长等待时间指令，直到长等待时间指令准备执行（例如，已经从外部存储器检索到加载指令的数据）。通过将延迟时间长的指令及其依赖项存储在已停播的一个线程的重放队列部分中，执行资源可用于提高未停滞的其他线程的执行速度。

8. 发明授权

US06792446B2 Storing of instructions relating to a stalled thread 有权
标题翻译：存储与停止的线程相关的指令
公开(公告)号：US06792446B2
公开(公告)日：2004-09-14
申请号：US10060264
申请日：2002-02-01
申请人： Amit A. Merchant , Darrell D. Buggs , David J. Sager
发明人： Amit A. Merchant , Darrell D. Buggs , David J. Sager
IPC分类号： G06F900
CPC分类号： G06F9/383 , G06F9/3838 , G06F9/3842 , G06F9/3851 , G06F9/3863 , G06F9/3869
摘要： A processor is provided that includes an execution unit for executing instructions and a replay system for replaying instructions which have not executed properly. The replay system is coupled to the execution unit and includes a checker for determining whether each instruction has executed properly and a plurality of replay queues or replay queue sections coupled to the checker for temporarily storing one or more instructions for replay. In one embodiment, thread-specific replay queue sections may each be used to store a long latency instruction for each thread until the long latency instruction is ready to be executed (e.g., data for a load instruction has been retrieved from external memory). By storing the long latency instruction and its dependents in a replay queue section for one thread which has stalled, execution resources are made available for improving the speed of execution of other threads which have not stalled.
摘要翻译：提供了一种处理器，其包括用于执行指令的执行单元和用于重放未正确执行的指令的重放系统。重播系统耦合到执行单元，并且包括用于确定每个指令是否已正确执行的检查器和耦合到检验器的多个重播队列或重放队列部分，用于临时存储用于重放的一个或多个指令。在一个实施例中，线程特定的重播队列部分可以各自用于存储每个线程的长等待时间指令，直到长等待时间指令准备执行（例如，已经从外部存储器检索到加载指令的数据）。通过将延迟时间长的指令及其依赖项存储在已停播的一个线程的重放队列部分中，执行资源可用于提高未停滞的其他线程的执行速度。

9. 发明授权

US5893151A Method and apparatus for maintaining cache coherency in a computer system with a highly pipelined bus and multiple conflicting snoop requests 失效
标题翻译：用于在具有高流水线总线和多个冲突窥探请求的计算机系统中维持高速缓存一致性的方法和装置
公开(公告)号：US5893151A
公开(公告)日：1999-04-06
申请号：US826553
申请日：1997-04-04
申请人： Amit A. Merchant
发明人： Amit A. Merchant
IPC分类号： G06F12/08 , G06F13/18
CPC分类号： G06F12/0831 , G06F12/0833
摘要： An apparatus for maintaining cache coherency for snoop operations includes a processor core for fetching, decoding, and executing instructions, a data cache coupled to the processor core for providing data to the processor core and for receiving data from the processor core, and a system bus coupling the processor core to the data cache. The apparatus further includes a snoop scheduler coupled to the processor core, the data cache, and the system bus, where the snoop scheduler is coupled to receive addresses from the system bus. The snoop scheduler also determines if snoop operations are orthogonal and schedules one or more out-of-order and at least partially overlapping snoop operations. Determining which snoop operations are orthogonal includes utilizing a block bit, a sleep bit, and a plurality of previously pending snoop request bits in a snoop queue entry to determine if the entry is orthogonal or not.
摘要翻译：用于维持窥探操作的高速缓存一致性的装置包括用于取出，解码和执行指令的处理器核心，耦合到处理器核心的数据高速缓存器，用于向处理器核心提供数据并从处理器核心接收数据，以及系统总线将处理器内核耦合到数据高速缓存。该装置还包括耦合到处理器核心，数据高速缓存和系统总线的侦听调度器，其中侦听调度器被耦合以从系统总线接收地址。侦听调度程序还确定窥探操作是否正交，并调度一个或多个无序和至少部分重叠的侦听操作。确定哪个窥探操作是正交的，包括在窥探队列条目中利用块比特，睡眠比特和多个先前未决的窥探请求比特来确定该条目是否正交。

10. 发明授权

US5890200A Method and apparatus for maintaining cache coherency in a computer system with a highly pipelined bus and multiple conflicting snoop requests 失效
标题翻译：用于在具有高流水线总线和多个冲突窥探请求的计算机系统中维持高速缓存一致性的方法和装置
公开(公告)号：US5890200A
公开(公告)日：1999-03-30
申请号：US825719
申请日：1997-04-04
申请人： Amit A. Merchant
发明人： Amit A. Merchant
IPC分类号： G06F12/08 , G06F13/18
CPC分类号： G06F12/0831 , G06F12/0833
摘要： An apparatus for maintaining cache coherency for snoop operations includes a snoop scheduler coupled to receive addresses from a system bus. The snoop scheduler utilizes a content addressable memory array. The snoop scheduler determines if snoop operations are orthogonal and schedules one or more out-of-order and at least partially overlapping snoop operations. Determining which snoop operations are orthogonal includes utilizing a block bit, a sleep bit, and a plurality of previously pending snoop request bits in a snoop queue entry to determine if the entry is orthogonal or not.
摘要翻译：用于维持侦听操作的高速缓存一致性的装置包括被连接以从系统总线接收地址的侦听调度器。侦听调度器利用内容可寻址存储器阵列。侦听调度程序确定侦听操作是否正交，并调度一个或多个无序和至少部分重叠的侦听操作。确定哪个窥探操作是正交的，包括在窥探队列条目中利用块比特，睡眠比特和多个先前未决的窥探请求比特来确定该条目是否正交。

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