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11. 发明授权

US5633177A Method for producing a semiconductor gate conductor having an impurity migration barrier 失效
标题翻译：一种具有杂质迁移屏障的半导体栅极导体的制造方法
公开(公告)号：US5633177A
公开(公告)日：1997-05-27
申请号：US194985
申请日：1993-11-08
申请人： Mohammed Anjum
发明人： Mohammed Anjum
IPC分类号： H01L21/28 , H01L21/336 , H01L21/265
CPC分类号： H01L29/66575 , H01L21/28052
摘要： A PMOS device is provided having a diffusion barrier placed within the polysilicon gate. The diffusion barrier is purposefully deposited to a concentration peak density within the gate which is deeper than subsequently placed impurity dopant. The barrier comprises germanium atoms placed in fairly close proximity to one another within the gate conductor, and the impurity dopant comprises an ionized compound of BF.sub.2 subsequently placed as boron within the gate and source/drain region, at least a majority and preferably greater than eighty percent of which are placed shallower within the gate than the germanium atoms. The barrier region substantially prevents or retards penetration of boron atoms through the gate oxide and into the channel region. Thus, the barrier helps prevent change in channel concentration and problems associated with boron penetration such as flatband voltage (Vfb) and threshold voltage (Vth) shift.
摘要翻译：提供PMOS器件，其具有放置在多晶硅栅极内的扩散势垒。扩散阻挡层被有目的地沉积到栅极内的浓度峰值密度，其比随后放置的杂质掺杂物更深。阻挡层包括在栅极导体内彼此非常接近地放置的锗原子，杂质掺杂剂包括随后在栅极和源极/漏极区中放置为硼的电离化合物BF 2，至少大部分，优选大于八十其中百分之一比锗原子在门内更浅。阻挡区域基本上防止或阻止硼原子穿过栅极氧化物并进入沟道区域。因此，屏障有助于防止通道浓度的变化和与硼渗透相关的问题，例如平带电压（Vfb）和阈值电压（Vth）偏移。

12. 发明授权

US5258637A Semiconductor devices produced according to a method which reduces contact resistance at silicide/active area interfaces 失效
标题翻译：根据降低硅化物/有源区界面处的接触电阻的方法制造的半导体器件
公开(公告)号：US5258637A
公开(公告)日：1993-11-02
申请号：US849685
申请日：1992-03-11
申请人： Gurtej S. Sandhu , Mohammed Anjum
发明人： Gurtej S. Sandhu , Mohammed Anjum
IPC分类号： H01L21/265 , H01L21/285 , H01L23/48 , H01L29/40
CPC分类号： H01L21/26506 , H01L21/28518 , H01L21/76814 , H01L21/76843 , H01L21/76855 , H01L23/485 , H01L2924/0002
摘要： Disclosed is a semiconductor processing method for reducing contact resistance between an active area and an overlying silicide resulting from diffusion of an impurity from the active area into the silicide. The method comprises implanting germanium through the contact opening and into the active area of the wafer to a peak density at an elevation which is at or above the elevation of the peak density of the conductivity enhancing impurity. A layer of metal is applied atop the wafer and into the contact opening to contact the active area. The metal and silicon within the contact opening are annealed to form a metal silicide. The annealing step consumes elemental silicon into the wafer to an elevation which is at or above the elevation of the germanium peak density. The germanium restricts diffusion of the conductivity enhancing impurity therethrough during the silicide anneal.
摘要翻译：公开了一种半导体处理方法，用于降低有源区和由有源区扩散到硅化物中而产生的上覆硅化物之间的接触电阻。该方法包括将锗通过接触开口植入到晶片的有效区域中，使其处于等于或高于导电性增强杂质峰值密度的高度处的峰值密度。将一层金属施加在晶片顶部并进入接触开口以接触有源区。接触孔内的金属和硅退火形成金属硅化物。退火步骤将元素硅消耗到晶片中至高于锗峰密度的高度的高度。锗在硅化物退火期间限制了增强导电性杂质的扩散。

13. 发明授权

US5360749A Method of making semiconductor structure with germanium implant for reducing short channel effects and subthreshold current near the substrate surface 失效
标题翻译：制造具有锗注入的半导体结构以减少衬底表面附近的短沟道效应和亚阈值电流的方法
公开(公告)号：US5360749A
公开(公告)日：1994-11-01
申请号：US166305
申请日：1993-12-10
申请人： Mohammed Anjum , Klaus H. Koop , Maung H. Kyaw
发明人： Mohammed Anjum , Klaus H. Koop , Maung H. Kyaw
IPC分类号： H01L21/265 , H01L21/336 , H01L29/78
CPC分类号： H01L29/66477 , H01L21/26506 , H01L21/26586 , H01L29/6659 , H01L29/78
摘要： A semiconductor structure with germanium implant is provided for reducing V.sub.T shifts at the channel edges thereby minimizing short channel effects and subthreshold currents at or near the substrate surface. The semiconductor structure is adapted to receive non-perpendicular implant of germanium in the juncture between the channel and the source/drain regions as well as in the juncture between field oxide channel stop implant and source/drain regions. By carefully and controllably placing the germanium at select channel and field regions, segregation and redistribution of threshold adjust implant and channel stop implant dopant materials is substantially minimized. Reducing the redistribution of such materials provides a reduction in the short channel effects and, particularly, a reduction in substrate surface current or DIBL-induced current.
摘要翻译：提供了具有锗注入的半导体结构，用于减小沟道边缘处的VT偏移，从而最小化衬底表面处或附近的短沟道效应和亚阈值电流。半导体结构适于在沟道和源极/漏极区之间的接合处以及场氧化物沟道停止注入和源极/漏极区之间的接合处接收锗的非垂直注入。通过仔细且可控地将锗置于选择的通道和场区，阈值调节注入和通道停留注入掺杂剂材料的分离和重新分布基本上最小化。减少这种材料的重新分布提供了短通道效应的降低，特别是降低了衬底表面电流或DIBL感应电流。

14. 发明授权

US5358894A Oxidation enhancement in narrow masked field regions of a semiconductor wafer 失效
标题翻译：半导体晶片的窄掩模场区域的氧化增强
公开(公告)号：US5358894A
公开(公告)日：1994-10-25
申请号：US175481
申请日：1993-12-30
申请人： Pierre Fazan , Viju Mathews , Gurtej S. Sandhu , Mohammed Anjum , Hiang C. Chan
发明人： Pierre Fazan , Viju Mathews , Gurtej S. Sandhu , Mohammed Anjum , Hiang C. Chan
IPC分类号： H01L21/316 , H01L21/762 , H01L21/76
CPC分类号： H01L21/02238 , H01L21/02299 , H01L21/31662 , H01L21/76213 , Y10S148/116 , Y10S148/163
摘要： A LOCOS process is enhanced by enhancing the depth of field oxide in regions having a narrow field oxide width. Subsequent to forming a pattern of nitride to define the field oxide and active area, photoresist is applied to selected areas of the wafer. An impurity is then applied to the underlying semiconductor substrate in areas not protected by photoresist and nitride. The impurity results in an enhanced oxidation rate and therefore compensates for a thinning effect in selected field oxide areas, such as those having a narrow width. Subsequent formation of the field oxide results in the doped material being consumed by the oxide.
摘要翻译：通过在具有窄场氧化物宽度的区域中增强场氧化物来增强LOCOS工艺。在形成氮化物图案以限定场氧化物和有源区域之后，将光致抗蚀剂施加到晶片的选定区域。然后在不受光致抗蚀剂和氮化物保护的区域中将杂质施加到下面的半导体衬底。杂质导致增强的氧化速率，因此补偿了选择的场氧化物区域（例如具有窄宽度的区域）中的稀化效应。随后形成场氧化物导致掺杂材料被氧化物消耗。

15. 发明授权

US5108954A Method of reducing contact resistance at silicide/active area interfaces and semiconductor devices produced according to the method 失效
标题翻译：根据该方法制造的硅化物/有源区界面和半导体器件的接触电阻降低的方法
公开(公告)号：US5108954A
公开(公告)日：1992-04-28
申请号：US764352
申请日：1991-09-23
申请人： Gurtej S. Sandhu , Mohammed Anjum
发明人： Gurtej S. Sandhu , Mohammed Anjum
IPC分类号： H01L21/285
CPC分类号： H01L21/28518 , H01L21/76814 , H01L21/76843 , H01L21/76855 , H01L23/485 , H01L2924/0002 , Y10S148/019
摘要： Disclosed is a semiconductor processing method for reducing contact resistance between an active area and an overlying silicide resulting from diffusion of an impurity from the active area into the silicide. The method comprises implanting germanium through the contact opening and into the active area of the wafer to a peak density at an elevation which is at or above the elevation of the peak density of the conductivity enhancing impurity. A layer of metal is applied atop the wafer and into the contact opening to contact the active area. The metal and silicon within the contact opening are annealed to form a metal silicide. The annealing step consumes elemental silicon into the wafer to an elevation which is at or above the elevation of the germanium peak density. The germanium restricts diffusion of the conductivity enhancing impurity therethrough during the silicide anneal.
摘要翻译：公开了一种半导体处理方法，用于降低有源区和由有源区扩散到硅化物中而产生的上覆硅化物之间的接触电阻。该方法包括将锗通过接触开口植入到晶片的有效区域中，使其处于等于或高于导电性增强杂质峰值密度的高度处的峰值密度。将一层金属施加在晶片顶部并进入接触开口以接触有源区。接触孔内的金属和硅退火形成金属硅化物。退火步骤将元素硅消耗到晶片中至高于锗峰密度的高度的高度。锗在硅化物退火期间限制了增强导电性杂质的扩散。

16. 发明授权

US06331458B1 Active region implant methodology using indium to enhance short channel performance of a surface channel PMOS device 失效
标题翻译：使用铟的有源区域注入方法来增强表面沟道PMOS器件的短沟道性能
公开(公告)号：US06331458B1
公开(公告)日：2001-12-18
申请号：US08532861
申请日：1995-09-22
申请人： Mohammed Anjum , Alan L. Stuber , Ibrahim K. Burki
发明人： Mohammed Anjum , Alan L. Stuber , Ibrahim K. Burki
IPC分类号： H01L21336
CPC分类号： H01L29/0847 , H01L21/823807
摘要： An MOS device is provided using indium as a threshold adjust implant in the channel regions of an NMOS device and/or in the conductive gate overlying the channel region in a PMOS device. Indium ions are relatively immobile and achieve location stability in the areas in which they are implanted. They do not readily segregate and diffuse in the lateral directions as well as in directions perpendicular to the silicon substrate. Placement immobility is necessary in order to minimize problems of threshold skew and gate oxide thickness enhancement. Additionally, it is believed that indium atoms within the channel region minimize hot carrier effects and the problems associated therewith.
摘要翻译：使用铟作为在NMOS器件的沟道区域中和/或在PMOS器件中的沟道区域上的导电栅极中的阈值调整注入来提供MOS器件。铟离子相对不动，并且在植入它们的区域中实现位置稳定性。它们不容易在横向方向以及垂直于硅衬底的方向上分离和扩散。放置不动是必要的，以最小化阈值偏移和栅极氧化物厚度增强的问题。另外，相信沟道区域内的铟原子使热载流子效应和与之相关的问题最小化。

17. 发明授权

US5429972A Method of fabricating a capacitor with a textured polysilicon interface and an enhanced dielectric 失效
标题翻译：制造具有纹理多晶硅界面和增强电介质的电容器的方法
公开(公告)号：US5429972A
公开(公告)日：1995-07-04
申请号：US239453
申请日：1994-05-09
申请人： Mohammed Anjum , Klaus H. Koop , Maung H. Kyaw
发明人： Mohammed Anjum , Klaus H. Koop , Maung H. Kyaw
IPC分类号： H01L27/04 , H01L21/02 , H01L21/265 , H01L21/822 , H01L21/8242 , H01L27/108
CPC分类号： H01L27/10852 , H01L27/10808 , H01L28/82 , H01L28/84 , Y10S148/014 , Y10S438/964
摘要： An enhanced capacitor configuration is provided in which the conductive and insulative layers are formed by implantation rather than deposition. The conductive regions are implanted at dissimilar depths and the insulative region is implanted between the conductive regions to form the conductive plates and intermediate dielectric material. By implanting rather than depositing, the dielectric material remains free of pinholes and can be configured thinner than conventional dielectrics, with a higher dielectric constant (k) due to the absence of an oxide. Moreover, cross-diffusions which occur during the anneal step allow texturization of the dielectric/conductive juncture. Texturization corresponds to an increase in surface area of the capacitor and, similar to increase in dielectric constant and decrease in dielectric thickness, increases the capacitive value of the ensuing capacitor.
摘要翻译：提供了一种增强的电容器配置，其中通过注入而不是沉积形成导电绝缘层和绝缘层。导电区域以不同的深度注入，并且绝缘区域被注入在导电区域之间以形成导电板和中间介电材料。通过注入而不是沉积，电介质材料保持没有针孔，并且可以被配置为比常规电介质薄，由于不存在氧化物而具有较高的介电常数（k）。此外，在退火步骤期间发生的交叉扩散允许电介质/导电接合体的纹理化。纹理化对应于电容器的表面积的增加，并且类似于介电常数的增加和电介质厚度的减小，增加随后的电容器的电容值。

18. 发明授权

US5891791A Contamination free source for shallow low energy junction implants 失效
标题翻译：浅层低能量结植入物的无污染源
公开(公告)号：US5891791A
公开(公告)日：1999-04-06
申请号：US863993
申请日：1997-05-27
申请人： Gurtej S. Sandhu , Mohammed Anjum
发明人： Gurtej S. Sandhu , Mohammed Anjum
IPC分类号： H01L21/265 , H01L21/285
CPC分类号： H01L21/26513 , H01L21/26506 , H01L21/28518
摘要： A method for forming a P-type region in a semiconducting crystalline substrate by ion implantation is disclosed, wherein the implant specie is an ionic molecule that contains titanium and boron.
摘要翻译：公开了一种通过离子注入在半导体晶体衬底中形成P型区域的方法，其中植入物是含有钛和硼的离子分子。

19. 发明授权

US5471293A Method and device for determining defects within a crystallographic substrate 失效
标题翻译：用于确定晶体基底内的缺陷的方法和装置
公开(公告)号：US5471293A
公开(公告)日：1995-11-28
申请号：US191387
申请日：1994-02-02
申请人： John K. Lowell , Mohammed Anjum , Valerie A. Wenner , Norman L. Armour , Maung H. Kyaw
发明人： John K. Lowell , Mohammed Anjum , Valerie A. Wenner , Norman L. Armour , Maung H. Kyaw
IPC分类号： G01N21/17 , G01R31/265 , G01N21/00
CPC分类号： G01R31/2656 , G01N21/17
摘要： A method and device is provided for determining defects within a single crystal substrate. The methodology includes a surface photovoltage (SPV) technique in which the magnitude of non-linearity is quantified and correlated to defects within the crystal lattice. The correlation factor is determined in a rapid and efficient manner using least square correlation methodology without having to determine diffusion length and incur difficulties associated therewith. Obtaining a quantifiable least square correlation factor allows the operator to quickly determine the amount of crystalline damage often encountered by, for example, ion implantation. In addition, the operator can determine the relative depth and position of defective crystalline layers within the substrate based upon demarcations between monotonically and non-monotonically aligned points plotted in a graph of reciprocal photovoltage versus reciprocal absorption coefficient.
摘要翻译：提供了一种用于确定单晶衬底内的缺陷的方法和装置。该方法包括表面光电压（SPV）技术，其中非线性的量值被量化并与晶格内的缺陷相关联。使用最小二乘相关方法以快速和有效的方式确定相关因子，而不必确定扩散长度并引起与之相关的困难。获得可量化的最小二乘相关因子允许操作者快速确定例如离子注入常常遇到的结晶损伤的量。此外，操作者可以基于在互逆光电压对相对吸收系数的曲线图中绘制的单调和非单调对准点之间的分界来确定衬底内的有缺陷的晶体层的相对深度和位置。

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