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1. 发明授权

US5965932A Contamination free source for shallow low energy junction implants using implanted molecules containing titanium and boron 失效
标题翻译：使用含有钛和硼的注入分子的浅层能量结植入物的无污染源
公开(公告)号：US5965932A
公开(公告)日：1999-10-12
申请号：US73257
申请日：1998-05-05
申请人： Gurtej S. Sandhu , Mohammed Anjum
发明人： Gurtej S. Sandhu , Mohammed Anjum
IPC分类号： H01L21/265 , H01L21/285
CPC分类号： H01L21/26513 , H01L21/26506 , H01L21/28518
摘要： A method for forming a P-type region in a semiconducting crystalline substrate by ion implantation is disclosed, wherein the implant species is an ionic molecule that contains titanium and boron.
摘要翻译：公开了一种通过离子注入在半导体晶体衬底中形成P型区的方法，其中注入物质是含有钛和硼的离子分子。

2. 发明授权

US5258637A Semiconductor devices produced according to a method which reduces contact resistance at silicide/active area interfaces 失效
标题翻译：根据降低硅化物/有源区界面处的接触电阻的方法制造的半导体器件
公开(公告)号：US5258637A
公开(公告)日：1993-11-02
申请号：US849685
申请日：1992-03-11
申请人： Gurtej S. Sandhu , Mohammed Anjum
发明人： Gurtej S. Sandhu , Mohammed Anjum
IPC分类号： H01L21/265 , H01L21/285 , H01L23/48 , H01L29/40
CPC分类号： H01L21/26506 , H01L21/28518 , H01L21/76814 , H01L21/76843 , H01L21/76855 , H01L23/485 , H01L2924/0002
摘要： Disclosed is a semiconductor processing method for reducing contact resistance between an active area and an overlying silicide resulting from diffusion of an impurity from the active area into the silicide. The method comprises implanting germanium through the contact opening and into the active area of the wafer to a peak density at an elevation which is at or above the elevation of the peak density of the conductivity enhancing impurity. A layer of metal is applied atop the wafer and into the contact opening to contact the active area. The metal and silicon within the contact opening are annealed to form a metal silicide. The annealing step consumes elemental silicon into the wafer to an elevation which is at or above the elevation of the germanium peak density. The germanium restricts diffusion of the conductivity enhancing impurity therethrough during the silicide anneal.
摘要翻译：公开了一种半导体处理方法，用于降低有源区和由有源区扩散到硅化物中而产生的上覆硅化物之间的接触电阻。该方法包括将锗通过接触开口植入到晶片的有效区域中，使其处于等于或高于导电性增强杂质峰值密度的高度处的峰值密度。将一层金属施加在晶片顶部并进入接触开口以接触有源区。接触孔内的金属和硅退火形成金属硅化物。退火步骤将元素硅消耗到晶片中至高于锗峰密度的高度的高度。锗在硅化物退火期间限制了增强导电性杂质的扩散。

3. 发明授权

US5358894A Oxidation enhancement in narrow masked field regions of a semiconductor wafer 失效
标题翻译：半导体晶片的窄掩模场区域的氧化增强
公开(公告)号：US5358894A
公开(公告)日：1994-10-25
申请号：US175481
申请日：1993-12-30
申请人： Pierre Fazan , Viju Mathews , Gurtej S. Sandhu , Mohammed Anjum , Hiang C. Chan
发明人： Pierre Fazan , Viju Mathews , Gurtej S. Sandhu , Mohammed Anjum , Hiang C. Chan
IPC分类号： H01L21/316 , H01L21/762 , H01L21/76
CPC分类号： H01L21/02238 , H01L21/02299 , H01L21/31662 , H01L21/76213 , Y10S148/116 , Y10S148/163
摘要： A LOCOS process is enhanced by enhancing the depth of field oxide in regions having a narrow field oxide width. Subsequent to forming a pattern of nitride to define the field oxide and active area, photoresist is applied to selected areas of the wafer. An impurity is then applied to the underlying semiconductor substrate in areas not protected by photoresist and nitride. The impurity results in an enhanced oxidation rate and therefore compensates for a thinning effect in selected field oxide areas, such as those having a narrow width. Subsequent formation of the field oxide results in the doped material being consumed by the oxide.
摘要翻译：通过在具有窄场氧化物宽度的区域中增强场氧化物来增强LOCOS工艺。在形成氮化物图案以限定场氧化物和有源区域之后，将光致抗蚀剂施加到晶片的选定区域。然后在不受光致抗蚀剂和氮化物保护的区域中将杂质施加到下面的半导体衬底。杂质导致增强的氧化速率，因此补偿了选择的场氧化物区域（例如具有窄宽度的区域）中的稀化效应。随后形成场氧化物导致掺杂材料被氧化物消耗。

4. 发明授权

US5108954A Method of reducing contact resistance at silicide/active area interfaces and semiconductor devices produced according to the method 失效
标题翻译：根据该方法制造的硅化物/有源区界面和半导体器件的接触电阻降低的方法
公开(公告)号：US5108954A
公开(公告)日：1992-04-28
申请号：US764352
申请日：1991-09-23
申请人： Gurtej S. Sandhu , Mohammed Anjum
发明人： Gurtej S. Sandhu , Mohammed Anjum
IPC分类号： H01L21/285
CPC分类号： H01L21/28518 , H01L21/76814 , H01L21/76843 , H01L21/76855 , H01L23/485 , H01L2924/0002 , Y10S148/019
摘要： Disclosed is a semiconductor processing method for reducing contact resistance between an active area and an overlying silicide resulting from diffusion of an impurity from the active area into the silicide. The method comprises implanting germanium through the contact opening and into the active area of the wafer to a peak density at an elevation which is at or above the elevation of the peak density of the conductivity enhancing impurity. A layer of metal is applied atop the wafer and into the contact opening to contact the active area. The metal and silicon within the contact opening are annealed to form a metal silicide. The annealing step consumes elemental silicon into the wafer to an elevation which is at or above the elevation of the germanium peak density. The germanium restricts diffusion of the conductivity enhancing impurity therethrough during the silicide anneal.
摘要翻译：公开了一种半导体处理方法，用于降低有源区和由有源区扩散到硅化物中而产生的上覆硅化物之间的接触电阻。该方法包括将锗通过接触开口植入到晶片的有效区域中，使其处于等于或高于导电性增强杂质峰值密度的高度处的峰值密度。将一层金属施加在晶片顶部并进入接触开口以接触有源区。接触孔内的金属和硅退火形成金属硅化物。退火步骤将元素硅消耗到晶片中至高于锗峰密度的高度的高度。锗在硅化物退火期间限制了增强导电性杂质的扩散。

5. 发明授权

US5891791A Contamination free source for shallow low energy junction implants 失效
标题翻译：浅层低能量结植入物的无污染源
公开(公告)号：US5891791A
公开(公告)日：1999-04-06
申请号：US863993
申请日：1997-05-27
申请人： Gurtej S. Sandhu , Mohammed Anjum
发明人： Gurtej S. Sandhu , Mohammed Anjum
IPC分类号： H01L21/265 , H01L21/285
CPC分类号： H01L21/26513 , H01L21/26506 , H01L21/28518
摘要： A method for forming a P-type region in a semiconducting crystalline substrate by ion implantation is disclosed, wherein the implant specie is an ionic molecule that contains titanium and boron.
摘要翻译：公开了一种通过离子注入在半导体晶体衬底中形成P型区域的方法，其中植入物是含有钛和硼的离子分子。

6. 发明授权

US09099314B2 Pitch multiplication spacers and methods of forming the same 有权
标题翻译：间距倍增器及其形成方法
公开(公告)号：US09099314B2
公开(公告)日：2015-08-04
申请号：US12827506
申请日：2010-06-30
申请人： Gurtej S. Sandhu , Kirk D. Prall
发明人： Gurtej S. Sandhu , Kirk D. Prall
IPC分类号： H01L21/3213 , H01L21/033 , H01L21/308 , H01L21/3205
CPC分类号： H01L21/67063 , H01L21/0337 , H01L21/0338 , H01L21/3086 , H01L21/3088 , H01L21/32053 , H01L21/32134
摘要： Spacers in a pitch multiplication process are formed without performing a spacer etch. Rather, the mandrels are formed over a substrate and then the sides of the mandrels are reacted, e.g., in an oxidization, nitridation, or silicidation step, to form a material that can be selectively removed relative to the unreacted portions of the mandrel. The unreacted portions are selectively removed to leave a pattern of free-standing spacers. The free-standing spacers can serve as a mask for subsequent processing steps, such as etching the substrate.
摘要翻译：在不执行间隔物蚀刻的情况下形成间距倍增过程中的间隔物。相反，心轴形成在衬底上，然后心轴的侧面例如在氧化，氮化或硅化步骤中反应，以形成相对于心轴的未反应部分可以选择性去除的材料。选择性地去除未反应部分以留下独立间隔物的图案。独立的间隔物可以用作后续处理步骤的掩模，例如蚀刻基底。

7. 发明授权

US08999492B2 Method to produce nanometer-sized features with directed assembly of block copolymers 有权
标题翻译：通过嵌段共聚物的定向组装制备纳米尺寸特征的方法
公开(公告)号：US08999492B2
公开(公告)日：2015-04-07
申请号：US12026214
申请日：2008-02-05
申请人： Dan B. Millward , Gurtej S. Sandhu
发明人： Dan B. Millward , Gurtej S. Sandhu
IPC分类号： G03G7/00 , B05D5/02 , C08F2/46 , C03C25/68 , G03F7/00 , B81C99/00 , B82Y10/00 , B05D1/28 , B82Y30/00 , B82Y40/00
CPC分类号： B41N1/08 , B05D1/283 , B41N3/036 , B81C99/009 , B81C2201/0149 , B82Y10/00 , B82Y30/00 , B82Y40/00 , G03F7/0002 , G03F7/0017 , Y02C20/30 , Y10T428/24802
摘要： Methods for fabricating stamps and systems for patterning a substrate, and devices resulting from those methods are provided.
摘要翻译：提供用于制造用于图案化衬底的印记和系统的方法以及由这些方法产生的器件。

8. 发明授权

US08946903B2 Electrically conductive laminate structure containing graphene region 有权
标题翻译：导电层压结构
公开(公告)号：US08946903B2
公开(公告)日：2015-02-03
申请号：US12833074
申请日：2010-07-09
申请人： Gurtej S. Sandhu
发明人： Gurtej S. Sandhu
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40 , H01B13/00 , H01L21/768 , H01L23/532
CPC分类号： H01L23/53276 , H01L21/76805 , H01L21/76843 , H01L21/76847 , H01L21/76865 , H01L21/76877 , H01L23/53209 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： Some embodiments include electrical interconnects. The interconnects may contain laminate structures having a graphene region sandwiched between non-graphene regions. In some embodiments the graphene and non-graphene regions may be nested within one another. In some embodiments an electrically insulative material may be over an upper surface of the laminate structure, and an opening may extend through the insulative material to a portion of the laminate structure. Electrically conductive material may be within the opening and in electrical contact with at least one of the non-graphene regions of the laminate structure. Some embodiments include methods of forming electrical interconnects in which non-graphene material and graphene are alternately formed within a trench to form nested non-graphene and graphene regions.
摘要翻译：一些实施例包括电互连。互连可以包含层压结构，其具有夹在非石墨烯区域之间的石墨烯区域。在一些实施例中，石墨烯和非石墨烯区域可以彼此嵌套。在一些实施例中，电绝缘材料可以在层压结构的上表面之上，并且开口可以延伸穿过绝缘材料到层压结构的一部分。导电材料可以在开口内并且与层压结构的非石墨烯区域中的至少一个电接触。一些实施例包括形成电互连的方法，其中在沟槽内交替形成非石墨烯材料和石墨烯以形成嵌套的非石墨烯和石墨烯区域。

9. 发明授权

US08923038B2 Memory cells, semiconductor device structures, memory systems, and methods of fabrication 有权
标题翻译：存储单元，半导体器件结构，存储器系统和制造方法
公开(公告)号：US08923038B2
公开(公告)日：2014-12-30
申请号：US13527173
申请日：2012-06-19
申请人： Witold Kula , Gurtej S. Sandhu , Stephen J. Kramer
发明人： Witold Kula , Gurtej S. Sandhu , Stephen J. Kramer
IPC分类号： G11C11/15 , G11C11/00 , H01L29/82
CPC分类号： H01L43/08 , G11C11/161 , H01L27/228 , H01L43/02 , H01L43/12
摘要： Methods of forming magnetic memory cells are disclosed. Magnetic and non-magnetic materials are formed into a primal precursor structure in an initial stress state of essentially no strain, compressive strain, or tensile strain. A stress-compensating material, e.g., a non-sacrificial, conductive material, is formed to be disposed on the primal precursor structure to form a stress-compensated precursor structure in a net beneficial stress state. Thereafter, the stress-compensated precursor structure may be patterned to form a cell core of a memory cell. The net beneficial stress state of the stress-compensated precursor structure lends to formation of one or more magnetic regions, in the cell core, exhibiting a vertical magnetic orientation without deteriorating a magnetic strength of the one or more magnetic regions. Also disclosed are memory cells, memory cell structures, semiconductor device structures, and spin torque transfer magnetic random access memory (STT-MRAM) systems.
摘要翻译：公开了形成磁存储器单元的方法。磁性和非磁性材料在基本上没有应变，压缩应变或拉伸应变的初始应力状态下形成原始前体结构。形成应力补偿材料，例如非牺牲导电材料，以设置在原始前体结构上以在净有益应力状态下形成应力补偿前体结构。此后，应力补偿前体结构可以被图案化以形成存储单元的单元芯。应力补偿前体结构的净有益应力状态有助于在电池芯中形成一个或多个磁性区域，呈现垂直磁性取向而不会使一个或多个磁性区域的磁强度恶化。还公开了存储器单元，存储单元结构，半导体器件结构和自旋转矩传递磁随机存取存储器（STT-MRAM）系统。

10. 发明授权

US08772841B2 Reactive metal implated oxide based memory 有权
标题翻译：反应性金属注入氧化物基记忆
公开(公告)号：US08772841B2
公开(公告)日：2014-07-08
申请号：US13616307
申请日：2012-09-14
申请人： D.V. Nirmal Ramaswamy , Gurtej S. Sandhu
发明人： D.V. Nirmal Ramaswamy , Gurtej S. Sandhu
IPC分类号： H01L29/66 , H01L29/94 , H01L21/70 , H01L27/108
CPC分类号： H01L45/08 , G11C13/0007 , H01L45/145 , H01L45/165
摘要： Methods, devices, and systems associated with oxide based memory can include a method of forming an oxide based memory cell. Forming an oxide based memory cell can include forming a first conductive element, forming an oxide over the first conductive element, implanting a reactive metal into the oxide, and forming a second conductive element over the oxide.
摘要翻译：与基于氧化物的存储器相关联的方法，装置和系统可以包括形成基于氧化物的存储器单元的方法。形成基于氧化物的存储单元可以包括形成第一导电元件，在第一导电元件上形成氧化物，将活性金属注入到氧化物中，以及在氧化物上形成第二导电元件。

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