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11. 发明授权

US5495419A Integrated circuit physical design automation system utilizing optimization process decomposition and parallel processing 失效
标题翻译：集成电路物理设计自动化系统利用优化过程分解和并行处理
公开(公告)号：US5495419A
公开(公告)日：1996-02-27
申请号：US229826
申请日：1994-04-19
申请人： Michael D. Rostoker , James S. Koford , Edwin R. Jones , Douglas B. Boyle , Ranko Scepanovic
发明人： Michael D. Rostoker , James S. Koford , Edwin R. Jones , Douglas B. Boyle , Ranko Scepanovic
IPC分类号： G06F17/50 , G06F17/00
CPC分类号： G06F17/5072
摘要： In a physical design automation system for producing an optimized cell placement for an integrated circuit chip, a placement optimization methodology is decomposed into a plurality of cell placement optimization processes that are performed simultaneously by parallel processors on input data representing the chip. The results of the optimization processes are recomposed to produce an optimized cell placement. The fitness of the optimized cell placement is analyzed, and the parallel processors are controlled to selectively repeat performing the optimization processes for further optimizing the optimized cell placement if the fitness does not satisfy a predetermined criterion. The system can be applied to initial placement, routing, placement improvement and other problems. The processors can perform the same optimization process on different placements, or on areas of a single placement. Alternatively, the processors can perform different optimization processes simultaneously on a single initial placement, with the resulting processed placement having the highest fitness being selected as the optimized placement. The processors can further selectively reprocess areas of a placement having high cell interconnect congestion or other low fitness parameters.
摘要翻译：在用于产生用于集成电路芯片的优化的单元布局的物理设计自动化系统中，布局优化方法被分解成由并行处理器在表示芯片的输入数据上同时执行的多个单元布局优化处理。重组优化过程的结果以产生优化的细胞放置。分析优化的单元布局的适应性，并且如果适合度不满足预定标准，则并行处理器被控制以选择性地重复执行优化处理以进一步优化优化的单元布局。该系统可以应用于初始放置，布线，布局改进等问题。处理器可以对不同的展示位置或单个展示位置执行相同的优化过程。或者，处理器可以在单个初始放置上同时执行不同的优化过程，所得到的经处理的放置具有最佳适合度作为优化的位置。处理器可以进一步选择性地重新处理具有高单元互连拥塞或其他低适应度参数的位置的区域。

12. 发明授权

US5870313A Optimization processing for integrated circuit physical design automation system using parallel moving windows 失效
标题翻译：使用平行移动窗口的集成电路物理设计自动化系统的优化处理
公开(公告)号：US5870313A
公开(公告)日：1999-02-09
申请号：US987865
申请日：1997-12-09
申请人： Douglas B. Boyle , James S. Koford , Ranko Scepanovic , Edwin R. Jones , Michael D. Rostoker
发明人： Douglas B. Boyle , James S. Koford , Ranko Scepanovic , Edwin R. Jones , Michael D. Rostoker
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： One or more non-overlapping moving windows are positioned over a placement of cells for an integrated circuit chip to delineate respective subsets of cells. A fitness improvement operation such as simulated evolution is performed on the subsets simultaneously using parallel processors. The windows are either moved to specifically identified high interconnect congestion areas of the placement, or are moved across the placement in a raster type pattern such that each area of the placement is processed at least once. Exchange of misplaced cells between subsets can be accomplished by dimensioning the windows and designing the window movement pattern such that the subsets overlap. Alternatively, such exchange can be accomplished by using two sets of windows of different sizes. As yet another alternative, the improvement operation can allow misplaced cells to move to a border area outside a window. Each misplaced cell is placed on a list, and then moved to the centroid of a net of cells to which it is connected, which can be outside the subset that originally included the misplaced cell.
摘要翻译：一个或多个非重叠移动窗口位于用于集成电路芯片的单元的放置上以描绘相应的单元子集。使用并行处理器同时对子集执行诸如模拟演化的健身改善操作。窗口被移动到该位置的专门识别的高互连拥塞区域，或以栅格类型模式移动到该位置，使得该位置的每个区域至少被处理一次。可以通过对窗口进行尺寸设计和设计窗口移动图案以使得子集重叠来实现子集之间的错放单元的交换。或者，这种交换可以通过使用两组不同大小的窗口来完成。作为另一替代方案，改进操作可以允许错放的单元移动到窗外的边界区域。每个放错的单元格放在一个列表上，然后移动到它所连接的单元格网格的质心，它可能在最初包含放错单元格的子集之外。

13. 发明授权

US5815403A Fail-safe distributive processing method for producing a highest fitness cell placement for an integrated circuit chip 失效
标题翻译：用于产生用于集成电路芯片的最佳适应度单元布局的故障安全分配处理方法
公开(公告)号：US5815403A
公开(公告)日：1998-09-29
申请号：US229954
申请日：1994-04-19
申请人： Edwin R. Jones , James S. Koford , Douglas B. Boyle , Ranko Scepanovic , Michael D. Rostoker
发明人： Edwin R. Jones , James S. Koford , Douglas B. Boyle , Ranko Scepanovic , Michael D. Rostoker
IPC分类号： G06F9/50 , G06F17/50
CPC分类号： G06F9/5033 , G06F17/5072 , G06F2209/5017
摘要： A physical design automation system for producing a highest fitness cell placement for an integrated circuit chip includes a decomposition/recomposition processor for decomposing a cell placement optimization process into a plurality of tasks and recomposing the highest fitness cell placement from results of performing the tasks. A plurality of worker processors independently perform the tasks and produce results. A host processor distributively assigns the tasks to the worker processors in response to work requests received therefrom. Each worker processor sends a work request to the host processor after completing a task. The host processor maintains a list of unassigned tasks, assigned tasks and completed tasks, and revises the list to redesignate assigned tasks as unassigned tasks upon determining that the list includes no unassigned tasks and at least one assigned task, thus making the system immune to the failure of one or more processors.
摘要翻译：用于产生用于集成电路芯片的最佳适应度单元布置的物理设计自动化系统包括分解/重组处理器，用于将小区布置优化过程分解成多个任务，并且从执行任务的结果重新构建最佳适合度单元布局。多个工作者处理器独立执行任务并产生结果。主机处理器响应于从其接收到的工作请求，向任务处理器分配任务。完成任务后，每个工作处理器向主处理器发送工作请求。主处理器维护未分配任务，分配的任务和完成的任务的列表，并且在确定列表不包含未分配的任务和至少一个分配的任务时，修改列表以重新指定被分配的任务作为未分配的任务，从而使系统免受一个或多个处理器的故障。

14. 发明授权

US5745363A Optimization processing for integrated circuit physical design automation system using optimally switched cost function computations 失效
标题翻译：使用最优切换成本函数计算的集成电路物理设计自动化系统的优化处理
公开(公告)号：US5745363A
公开(公告)日：1998-04-28
申请号：US600588
申请日：1996-02-13
申请人： Michael D. Rostoker , James S. Koford , Edwin R. Jones , Douglas B. Boyle , Ranko Scepanovic
发明人： Michael D. Rostoker , James S. Koford , Edwin R. Jones , Douglas B. Boyle , Ranko Scepanovic
IPC分类号： G06F17/50 , G06F15/00
CPC分类号： G06F17/5072
摘要： In a physical design automation system for producing an optimized cell placement for an integrated circuit chip, a placement optimization methodology is decomposed into a plurality of cell placement optimization processes that are performed simultaneously by parallel processors on input data representing the chip. The results of the optimization processes are recomposed to produce an optimized cell placement. The fitness of the optimized cell placement is analyzed, and the parallel processors are controlled to selectively repeat performing the optimization processes for further optimizing the optimized cell placement if the fitness does not satisfy a predetermined criterion. The system can be applied to initial placement, routing, placement improvement and other problems. The processors can perform the same optimization process on different placements, or on areas of a single placement. Alternatively, the processors can perform different optimization processes simultaneously on a single initial placement, with the resulting processed placement having the highest fitness being selected as the optimized placement. The processors can further selectively reprocess areas of a placement having high cell interconnect congestion or other low fitness parameters.
摘要翻译：在用于产生用于集成电路芯片的优化的单元布局的物理设计自动化系统中，布局优化方法被分解成由并行处理器在表示芯片的输入数据上同时执行的多个单元布局优化处理。重组优化过程的结果以产生优化的细胞放置。分析优化的单元布局的适应性，并且如果适合度不满足预定标准，则并行处理器被控制以选择性地重复执行优化处理以进一步优化优化的单元布局。该系统可以应用于初始放置，布线，布局改进等问题。处理器可以对不同的展示位置或单个展示位置执行相同的优化过程。或者，处理器可以在单个初始放置上同时执行不同的优化过程，所得到的经处理的放置具有最佳适合度作为优化的位置。处理器可以进一步选择性地重新处理具有高单元互连拥塞或其他低适应度参数的位置的区域。

15. 发明授权

US5914887A Congestion based cost factor computing apparatus for integrated circuit physical design automation system 失效
标题翻译：用于集成电路物理设计自动化系统的拥塞成本因子计算设备
公开(公告)号：US5914887A
公开(公告)日：1999-06-22
申请号：US229624
申请日：1994-04-19
申请人： Ranko Scepanovic , James S. Koford , Edwin E. Jones , Douglas B. Boyle , Michael D. Rostoker
发明人： Ranko Scepanovic , James S. Koford , Edwin E. Jones , Douglas B. Boyle , Michael D. Rostoker
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： A cell placement for an integrated circuit chip comprises a large number of cells allocated to respective locations on the surface of the chip. The placement is divided into switch boxes that surround the cell locations respectively. A bounding box is constructed around each net of a netlist for the placement. A congestion factor is computed for each switch box as being equal to the number of bounding boxes that overlap the respective switch box. A cost factor for the placement and associated netlist is computed as the maximum value, average value, sum of squares or other function of the congestion factors. The individual congestion factor computation can be modified to require that a pin of a net of one of the bounding boxes overlap or be within a predetermined distance of a switch box in order for the congestion factor to be computed as the sum of the overlapping bounding boxes in order to localize and increase the accuracy of the cost factor estimation. The congestion factor for a switch box can also be weighted in accordance with the proximity of the switch box to a pin.
摘要翻译：用于集成电路芯片的单元布置包括分配给芯片表面上的相应位置的大量单元。该位置分为围绕单元格位置的开关盒。围绕放置网格表的每个网络构建一个边框。对于每个开关盒计算拥塞因子等于与相应开关盒重叠的边界盒的数量。放置和相关网表的成本因子计算为最大值，平均值，平方和或拥挤因子的其他函数。单个拥塞因子计算可以被修改为要求一个边界框的网络的引脚重叠或处于开关盒的预定距离内，以便将拥塞因子计算为重叠边界框的总和以便本地化并提高成本因素估计的准确性。开关盒的拥挤因子也可以根据开关盒与引脚的接近度进行加权。

16. 发明授权

US5742086A Hexagonal DRAM array 失效
标题翻译：六角形DRAM阵列
公开(公告)号：US5742086A
公开(公告)日：1998-04-21
申请号：US517153
申请日：1995-08-21
申请人： Michael D. Rostoker , James S. Koford , Ranko Scepanovic , Edwin R. Jones , Gobi R. Padmanahben , Ashok K. Kapoor , Valeriy B. Kudryavtsev , Alexander E. Andreev , Stanislav V. Aleshin , Alexander S. Podkolzin
发明人： Michael D. Rostoker , James S. Koford , Ranko Scepanovic , Edwin R. Jones , Gobi R. Padmanahben , Ashok K. Kapoor , Valeriy B. Kudryavtsev , Alexander E. Andreev , Stanislav V. Aleshin , Alexander S. Podkolzin
IPC分类号： G06F17/50 , G11C5/02 , G11C5/06 , H01L23/522 , H01L23/528 , H01L27/02 , H01L27/092 , H01L27/108 , H01L27/11 , H01L27/118 , H01L29/06 , H03K19/0944 , H03K19/0948 , H01L29/78 , H01L29/41
CPC分类号： G06F17/5072 , G06F17/5077 , G11C5/025 , G11C5/063 , H01L23/5222 , H01L23/528 , H01L27/0207 , H01L27/0922 , H01L27/108 , H01L27/11 , H01L27/1104 , H01L27/11807 , H03K19/09441 , H03K19/0948 , H01L29/0657 , H01L2924/0002
摘要： Several inventions are disclosed. A cell architecture using hexagonal shaped cells is disclosed. The architecture is not limited to hexagonal shaped cells. Cells may be defined by clusters of two or more hexagons, by triangles, by parallelograms, and by other polygons enabling a variety of cell shapes to be accommodated. Polydirectional non-orthogonal three layer metal routing is disclosed. The architecture may be combined with the tri-directional routing for a particularly advantageous design. In the tri-directional routing arraingement, electrical conductors for interconnecting terminals of microelectronic cells of an integrated circuit preferrably extend in three directions that are angularly displaced from each other by 60.degree.. The conductors that extend in the three directions are preferrably formed in three different layers. A method of minimizing wire length in a semiconductor device is disclosed. A method of minimizing intermetal capacitance in a semiconductor device is disclosed. A novel device called a "tri-ister" is disclosed. Triangular devices are disclosed, including triangular NAND gates, triangular AND gates, and triangular OR gates. A triangular op amp and triode are disclosed. A triangular sense amplifier is disclosed. A DRAM memory array and an SRAM memory array, based upon triangular or parallelogram shaped cells, are disclosed, including a method of interconnecting such arrays. A programmable variable drive transistor is disclosed. CAD algorithms and methods are disclosed for designing and making semiconductor devices, which are particularly applicable to the disclosed architecture and tri-directional three metal layer routing.
摘要翻译：披露了几个发明。公开了一种使用六角形电池的电池结构。该体系结构不限于六角形细胞。单元可以由两个或更多个六边形的簇，通过三角形，平行四边形以及能够容纳各种单元格形状的其他多边形来定义。公开了多向非正交三层金属布线。该架构可以与三向路由组合以用于特别有利的设计。在三向布线布置中，集成电路的微电子单元的互连端的电导体优选地在三个方向上相互延伸60°。沿三个方向延伸的导体优选地以三个不同的层形成。公开了一种使半导体器件中的导线长度最小化的方法。公开了一种使半导体器件中的金属间电容最小化的方法。公开了一种称为“三元器件”的新型器件。公开了三角形器件，包括三角形与非门，三角形与门和三角形或门。公开了三角形运算放大器和三极管。公开了三角形读出放大器。公开了一种基于三角形或平行四边形形状的单元的DRAM存储器阵列和SRAM存储器阵列，其包括互连这种阵列的方法。公开了一种可编程可变驱动晶体管。公开了用于设计和制造半导体器件的CAD算法和方法，其特别适用于所公开的架构和三向三金属层布线。

17. 发明授权

US5973376A Architecture having diamond shaped or parallelogram shaped cells 失效
标题翻译：具有菱形或平行四边形的细胞的建筑
公开(公告)号：US5973376A
公开(公告)日：1999-10-26
申请号：US517406
申请日：1995-08-21
申请人： Michael D. Rostoker , James S. Koford , Ranko Scepanovic , Edwin R. Jones , Gobi R. Padmanahben , Ashok K. Kapoor , Valeriy B. Kudryavtsev , Alexander E. Andreev , Stanislav V. Aleshin , Alexander S. Podkolzin
发明人： Michael D. Rostoker , James S. Koford , Ranko Scepanovic , Edwin R. Jones , Gobi R. Padmanahben , Ashok K. Kapoor , Valeriy B. Kudryavtsev , Alexander E. Andreev , Stanislav V. Aleshin , Alexander S. Podkolzin
IPC分类号： G06F17/50 , G11C5/02 , G11C5/06 , H01L23/522 , H01L23/528 , H01L27/02 , H01L27/092 , H01L27/108 , H01L27/11 , H01L27/118 , H01L29/06 , H03K19/0944 , H03K19/0948 , H01L31/352 , H01L23/52 , H01L29/78
CPC分类号： G06F17/5072 , G06F17/5077 , G11C5/025 , G11C5/063 , H01L23/5222 , H01L23/528 , H01L27/0207 , H01L27/0922 , H01L27/108 , H01L27/11 , H01L27/1104 , H01L27/11807 , H03K19/09441 , H03K19/0948 , H01L29/0657 , H01L2924/0002
摘要： Several inventions are disclosed. A cell architecture using hexagonal shaped cells is disclosed. The architecture is not limited to hexagonal shaped cells. Cells may be defined by clusters of two or more hexagons, by triangles, by parallelograms, and by other polygons enabling a variety of cell shapes to be accommodated. Polydirectional non-orthogonal three layer metal routing is disclosed. The architecture may be combined with the tri-directional routing for a particularly advantageous design. In the tri-directional routing arraingement, electrical conductors for interconnecting terminals of microelectronic cells of an integrated circuit preferrably extend in three directions that are angularly displaced from each other by 60.degree.. The conductors that extend in the three directions are preferrably formed in three different layers. A method of minimizing wire length in a semiconductor device is disclosed. A method of minimizing intermetal capacitance in a semiconductor device is disclosed. A novel device called a "tri-ister" is disclosed. Triangular devices are disclosed, including triangular NAND gates, triangular AND gates, and triangular OR gates. A triangular op amp and triode are disclosed. A triangular sense amplifier is disclosed. A DRAM memory array and an SRAM memory array, based upon triangular or parallelogram shaped cells, are disclosed, including a method of interconnecting such arrays. A programmable variable drive transistor is disclosed. CAD algorithms and methods are disclosed for designing and making semiconductor devices, which are particularly applicable to the disclosed architecture and tri-directional three metal layer routing.
摘要翻译：披露了几个发明。公开了一种使用六角形电池的电池结构。该体系结构不限于六角形细胞。单元可以由两个或更多个六边形的簇，通过三角形，平行四边形以及能够容纳各种单元格形状的其他多边形来定义。公开了多向非正交三层金属布线。该架构可以与三向路由组合以用于特别有利的设计。在三向布线布置中，集成电路的微电子单元的互连端的电导体优选地在三个方向上相互延伸60°。沿三个方向延伸的导体优选地以三个不同的层形成。公开了一种使半导体器件中的导线长度最小化的方法。公开了一种使半导体器件中的金属间电容最小化的方法。公开了一种称为“三元器件”的新型器件。公开了三角形器件，包括三角形与非门，三角形与门和三角形或门。公开了三角形运算放大器和三极管。公开了三角形读出放大器。公开了一种基于三角形或平行四边形形状的单元的DRAM存储器阵列和SRAM存储器阵列，其包括互连这种阵列的方法。公开了一种可编程可变驱动晶体管。公开了用于设计和制造半导体器件的CAD算法和方法，其特别适用于所公开的架构和三向三金属层布线。

18. 发明授权

US5872380A Hexagonal sense cell architecture 失效
标题翻译：六角感知单元架构
公开(公告)号：US5872380A
公开(公告)日：1999-02-16
申请号：US517189
申请日：1995-08-21
申请人： Michael D. Rostoker , James S. Koford , Ranko Scepanovic , Edwin R. Jones , Gobi R. Padmanahben , Ashok K. Kapoor , Valerity B. Kudryavtsev , Alexander E. Andreev , Stanislav V. Aleshin , Alexander S. Podkolzin
发明人： Michael D. Rostoker , James S. Koford , Ranko Scepanovic , Edwin R. Jones , Gobi R. Padmanahben , Ashok K. Kapoor , Valerity B. Kudryavtsev , Alexander E. Andreev , Stanislav V. Aleshin , Alexander S. Podkolzin
IPC分类号： G06F17/50 , G11C5/02 , G11C5/06 , H01L23/522 , H01L23/528 , H01L27/02 , H01L27/092 , H01L27/108 , H01L27/11 , H01L27/118 , H01L29/06 , H03K19/0944 , H03K19/0948 , H01L27/10
CPC分类号： G06F17/5072 , G06F17/5077 , G11C5/025 , G11C5/063 , H01L23/5222 , H01L23/528 , H01L27/0207 , H01L27/0922 , H01L27/108 , H01L27/11 , H01L27/1104 , H01L27/11807 , H03K19/09441 , H03K19/0948 , H01L29/0657 , H01L2924/0002
摘要： Several inventions are disclosed. A cell architecture using hexagonal shaped cells is disclosed. The architecture is not limited to hexagonal shaped cells. Cells may be defined by clusters of two or more hexagons, by triangles, by parallelograms, and by other polygons enabling a variety of cell shapes to be accommodated. Polydirectional non-orthogonal three layer metal routing is disclosed. The architecture may be combined with the tri-directional routing for a particularly advantageous design. In the tri-directional routing arrangement, electrical conductors for interconnecting terminals of microelectronic cells of an integrated circuit preferrably extend in three directions that are angularly displaced from each other by 60.degree.. The conductors that extend in the three directions are preferrably formed in three different layers. A method of minimizing wire length in a semiconductor device is disclosed. A method of minimizing intermetal capacitance in a semiconductor device is disclosed. A novel device called a "tri-ister" is disclosed. Triangular devices are disclosed, including triangular NAND gates, triangular AND gates, and triangular OR gates. A triangular op amp and triode are disclosed. A triangular sense amplifier is disclosed. A DRAM memory array and an SRAM memory array, based upon triangular or parallelogram shaped cells, are disclosed, including a method of interconnecting such arrays. A programmable variable drive transistor is disclosed. CAD algorithms and methods are disclosed for designing and making semiconductor devices, which are particularly applicable to the disclosed architecture and tri-directional three metal layer routing.
摘要翻译：披露了几个发明。公开了一种使用六角形电池的电池结构。该体系结构不限于六角形细胞。单元可以由两个或更多个六边形的簇，通过三角形，平行四边形以及能够容纳各种单元格形状的其他多边形来定义。公开了多向非正交三层金属布线。该架构可以与三向路由组合以用于特别有利的设计。在三向布线布置中，用于互连集成电路的微电子单元的端子的电导体优选地在彼此成角度地移位60度的三个方向上延伸。沿三个方向延伸的导体优选地以三个不同的层形成。公开了一种使半导体器件中的导线长度最小化的方法。公开了一种使半导体器件中的金属间电容最小化的方法。公开了一种称为“三元器件”的新型器件。公开了三角形器件，包括三角形与非门，三角形与门和三角形或门。公开了三角形运算放大器和三极管。公开了三角形读出放大器。公开了一种基于三角形或平行四边形形状的单元的DRAM存储器阵列和SRAM存储器阵列，其包括互连这种阵列的方法。公开了一种可编程可变驱动晶体管。公开了用于设计和制造半导体器件的CAD算法和方法，其特别适用于所公开的架构和三向三金属层布线。

19. 发明授权

US5822214A CAD for hexagonal architecture 失效
标题翻译：六角架构CAD
公开(公告)号：US5822214A
公开(公告)日：1998-10-13
申请号：US517171
申请日：1995-08-21
申请人： Michael D. Rostoker , James S. Koford , Ranko Scepanovic , Edwin R. Jones , Gobi R. Padmanahben , Ashok K. Kapoor , Valeriv B. Kudryavtsev , Alexander E. Andreev , Stanislav V. Aleshin , Alexander S. Podkolzin
发明人： Michael D. Rostoker , James S. Koford , Ranko Scepanovic , Edwin R. Jones , Gobi R. Padmanahben , Ashok K. Kapoor , Valeriv B. Kudryavtsev , Alexander E. Andreev , Stanislav V. Aleshin , Alexander S. Podkolzin
IPC分类号： G06F17/50 , G11C5/02 , G11C5/06 , H01L23/522 , H01L23/528 , H01L27/02 , H01L27/092 , H01L27/108 , H01L27/11 , H01L27/118 , H01L29/06 , H03K19/0944 , H03K19/0948 , G06F15/60
CPC分类号： G06F17/5072 , G06F17/5077 , G11C5/025 , G11C5/063 , H01L23/5222 , H01L23/528 , H01L27/0207 , H01L27/0922 , H01L27/108 , H01L27/11 , H01L27/1104 , H01L27/11807 , H03K19/09441 , H03K19/0948 , H01L29/0657 , H01L2924/0002
摘要： Several inventions are disclosed. A cell architecture using hexagonal shaped cells is disclosed. The architecture is not limited to hexagonal shaped cells. Cells may be defined by clusters of two or more hexagons, by triangles, by parallelograms, and by other polygons enabling a variety of cell shapes to be accommodated. Polydirectional non-orthogonal three layer metal routing is disclosed. The architecture may be combined with the tri-directional routing for a particularly advantageous design. In the tri-directional routing arrangement, electrical conductors for interconnecting terminals of microelectronic cells of an integrated circuit preferably extend in three directions that are angularly displaced from each other by 60.degree.. The conductors that extend in the three directions are preferably formed in three different layers. A method of minimizing wire length in a semiconductor device is disclosed. A method of minimizing intermetal capacitance in a semiconductor device is disclosed. A novel device called a "tri-ister" is disclosed. Triangular devices are disclosed, including triangular NAND gates, triangular AND gates, and triangular OR gates. A triangular op amp and triode are disclosed. A triangular sense amplifier is disclosed. A DRAM memory array and an SRAM memory array, based upon triangular or parallelogram shaped cells, are disclosed, including a method of interconnecting such arrays. A programmable variable drive transistor is disclosed. CAD algorithms and methods are disclosed for designing and making semiconductor devices, which are particularly applicable to the disclosed architecture and tri-directional three metal layer routing.
摘要翻译：披露了几个发明。公开了一种使用六角形电池的电池结构。该体系结构不限于六角形细胞。单元可以由两个或更多个六边形的簇，通过三角形，平行四边形以及能够容纳各种单元格形状的其他多边形来定义。公开了多向非正交三层金属布线。该架构可以与三向路由组合以用于特别有利的设计。在三向布线布置中，用于互连集成电路的微电子单元的端子的电导体优选地在三个方向上彼此成角度地移位60度。沿三个方向延伸的导体优选地形成为三个不同的层。公开了一种使半导体器件中的导线长度最小化的方法。公开了一种使半导体器件中的金属间电容最小化的方法。公开了一种称为“三元器件”的新型器件。公开了三角形器件，包括三角形与非门，三角形与门和三角形或门。公开了三角形运算放大器和三极管。公开了三角形读出放大器。公开了一种基于三角形或平行四边形形状的单元的DRAM存储器阵列和SRAM存储器阵列，其包括互连这种阵列的方法。公开了一种可编程可变驱动晶体管。公开了用于设计和制造半导体器件的CAD算法和方法，其特别适用于所公开的架构和三向三金属层布线。

20. 发明授权

US5811863A Transistors having dynamically adjustable characteristics 失效
标题翻译：具有动态可调特性的晶体管
公开(公告)号：US5811863A
公开(公告)日：1998-09-22
申请号：US517463
申请日：1995-08-21
申请人： Michael D. Rostoker , James S. Koford , Ranko Scepanovic , Edwin R. Jones , Gobi R. Padmanahben , Ashook K. Kapoor , Valeriy B. Kudryavtsev , Alexander E. Andreev , Stanislav V. Aleshin , Alexander S. Podkolzin
发明人： Michael D. Rostoker , James S. Koford , Ranko Scepanovic , Edwin R. Jones , Gobi R. Padmanahben , Ashook K. Kapoor , Valeriy B. Kudryavtsev , Alexander E. Andreev , Stanislav V. Aleshin , Alexander S. Podkolzin
IPC分类号： G06F17/50 , G11C5/02 , G11C5/06 , H01L23/522 , H01L23/528 , H01L27/02 , H01L27/092 , H01L27/108 , H01L27/11 , H01L27/118 , H01L29/06 , H03K19/0944 , H03K19/0948 , H01L29/78 , H01L29/41
CPC分类号： G06F17/5072 , G06F17/5077 , G11C5/025 , G11C5/063 , H01L23/5222 , H01L23/528 , H01L27/0207 , H01L27/0922 , H01L27/108 , H01L27/11 , H01L27/1104 , H01L27/11807 , H03K19/09441 , H03K19/0948 , H01L29/0657 , H01L2924/0002
摘要： Several inventions are disclosed. A cell architecture using hexagonal shaped cells is disclosed. The architecture is not limited to hexagonal shaped cells. Cells may be defined by clusters of two or more hexagons, by triangles, by parallelograms, and by other polygons enabling a variety of cell shapes to be accommodated. Polydirectional non-orthogonal three layer metal routing is disclosed. The architecture may be combined with the tri-directional routing for a particularly advantageous design. In the tri-directional routing arraingement, electrical conductors for interconnecting terminals of microelectronic cells of an integrated circuit preferrably extend in three directions that are angularly displaced from each other by 60.degree.. The conductors that extend in the three directions are preferrably formed in three different layers. A method of minimizing wire length in a semiconductor device is disclosed. A method of minimizing intermetal capacitance in a semiconductor device is disclosed. A novel device called a "tri-ister" is disclosed. Triangular devices are disclosed, including triangular NAND gates, triangular AND gates, and triangular OR gates. A triangular op amp and triode are disclosed. A triangular sense amplifier is disclosed. A DRAM memory array and an SRAM memory array, based upon triangular or parallelogram shaped cells, are disclosed, including a method of interconnecting such arrays. A programmable variable drive transistor is disclosed. CAD algorithms and methods are disclosed for designing and making semiconductor devices, which are particularly applicable to the disclosed architecture and tri-directional three metal layer routing.
摘要翻译：披露了几个发明。公开了一种使用六角形电池的电池结构。该体系结构不限于六角形细胞。单元可以由两个或更多个六边形的簇，通过三角形，平行四边形以及能够容纳各种单元格形状的其他多边形来定义。公开了多向非正交三层金属布线。该架构可以与三向路由组合以用于特别有利的设计。在三向布线布置中，集成电路的微电子单元的互连端的电导体优选地在三个方向上相互延伸60°。沿三个方向延伸的导体优选地以三个不同的层形成。公开了一种使半导体器件中的导线长度最小化的方法。公开了一种使半导体器件中的金属间电容最小化的方法。公开了一种称为“三元器件”的新型器件。公开了三角形器件，包括三角形与非门，三角形与门和三角形或门。公开了三角形运算放大器和三极管。公开了三角形读出放大器。公开了一种基于三角形或平行四边形形状的单元的DRAM存储器阵列和SRAM存储器阵列，其包括互连这种阵列的方法。公开了一种可编程可变驱动晶体管。公开了用于设计和制造半导体器件的CAD算法和方法，其特别适用于所公开的架构和三向三金属层布线。

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