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1. 发明授权

US5742510A Simultaneous placement and routing (SPAR) method for integrated circuit physical design automation system 失效
标题翻译：用于集成电路物理设计自动化系统的同时放置和布线（SPAR）方法
公开(公告)号：US5742510A
公开(公告)日：1998-04-21
申请号：US604181
申请日：1996-02-21
申请人： Michael D. Rostoker , James S. Koford , Edwin R. Jones , Douglas B. Boyle , Ranko Scepanovic
发明人： Michael D. Rostoker , James S. Koford , Edwin R. Jones , Douglas B. Boyle , Ranko Scepanovic
IPC分类号： G06F17/50 , G06F19/00
CPC分类号： G06F17/5072
摘要： In a physical design automation system for producing an optimized cell placement for an integrated circuit chip, a placement optimization methodology is decomposed into a plurality of cell placement optimization processes that are performed simultaneously by parallel processors on input data representing the chip. The results of the optimization processes are recomposed to produce an optimized cell placement. The fitness of the optimized cell placement is analyzed, and the parallel processors are controlled to selectively repeat performing the optimization processes for further optimizing the optimized cell placement if the fitness does not satisfy a predetermined criterion. The system can be applied to initial placement, routing, placement improvement and other problems. The processors can perform the same optimization process on different placements, or on areas of a single placement. Alternatively, the processors can perform different optimization processes simultaneously on a single initial placement, with the resulting processed placement having the highest fitness being selected as the optimized placement. The processors can further selectively reprocess areas of a placement having high cell interconnect congestion or other low fitness parameters.
摘要翻译：在用于生成用于集成电路芯片的优化的单元布置的物理设计自动化系统中，布局优化方法被分解成由并行处理器在表示芯片的输入数据上同时执行的多个单元布局优化处理。重组优化过程的结果以产生优化的细胞放置。分析优化的单元布局的适应性，并且如果适合度不满足预定标准，则并行处理器被控制以选择性地重复执行优化处理以进一步优化优化的单元布局。该系统可以应用于初始放置，布线，布局改进等问题。处理器可以对不同的展示位置或单个展示位置执行相同的优化过程。或者，处理器可以在单个初始放置上同时执行不同的优化过程，所得到的经处理的放置具有最佳适合度作为优化的位置。处理器可以进一步选择性地重新处理具有高单元互连拥塞或其他低适应度参数的位置的区域。

2. 发明授权

US5557533A Cell placement alteration apparatus for integrated circuit chip physical design automation system 失效
标题翻译：集成电路芯片物理设计自动化系统的电池放置改造装置
公开(公告)号：US5557533A
公开(公告)日：1996-09-17
申请号：US229821
申请日：1994-04-19
申请人： James S. Koford , Ranko Scepanovic , Edwin R. Jones , Douglas B. Boyle , Michael D. Rostoker
发明人： James S. Koford , Ranko Scepanovic , Edwin R. Jones , Douglas B. Boyle , Michael D. Rostoker
IPC分类号： G06F17/50 , G06F15/18
CPC分类号： G06F17/5072
摘要： A large number of possible placements of cells on an integrated circuit chip are generated and evaluated to determine the placement with the highest fitness. Cells for transposition or "swapping" within each placement using genetic algorithms are selected using greedy algorithms based on the fitness of each cell. The cell fitnesses are evaluated in terms of interconnect congestion, total net wire length or other criteria. Cells are selected for genetic crossover by sorting the cells in order of fitness and multiplying the cell fitnesses by weighting factors that increase non-linearly with rank. The cells are selected using linear random number generation such that cells with higher fitnesses have a higher probability of selection. Cells having lowest fitness are selected for mutation, and transposed to random locations, to adjacent locations, with cells having second worst fitness, to the center of mass of the respective interconnect nets, or with two or more cells in a cyclical manner.
摘要翻译：生成并评估集成电路芯片上大量可能的单元格放置，以确定具有最高适应度的位置。使用基于每个单元的适应度的贪心算法选择使用遗传算法在每个位置内进行转置或“交换”的单元。根据互连拥塞，总净线长度或其他标准来评估细胞适应度。选择细胞进行遗传交叉，通过按照适合度的顺序排列细胞，并通过与等级线性增加的加权因子乘以细胞适应度。使用线性随机数生成来选择细胞，使得具有较高适应度的细胞具有更高的选择概率。选择具有最低适应度的细胞用于突变，并且以周期性方式转置到随机位置，相邻位置，具有第二最坏适应度的细胞到相应互连网的质心，或者以两个或更多个细胞。

3. 发明授权

US6155725A Cell placement representation and transposition for integrated circuit physical design automation system 失效
标题翻译：集成电路物理设计自动化系统的电池放置表示和转置
公开(公告)号：US6155725A
公开(公告)日：2000-12-05
申请号：US230383
申请日：1994-04-19
申请人： Ranko Scepanovic , James S Koford , Edwin R. Jones , Douglas B. Boyle , Michael D. Rostoker
发明人： Ranko Scepanovic , James S Koford , Edwin R. Jones , Douglas B. Boyle , Michael D. Rostoker
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： A large number of possible cell placements for an integrated circuit chip are evaluated to determine which has the highest fitness in accordance with a predetermined criteria such as interconnect congestion. Each cell placement, which constitutes an individual permutation of cells from a population of possible permutations, is represented as an initial cell placement in combination with a list of individual cell transpositions or swaps by which the cell placement can be derived from the initial cell placement. A cell placement can be genetically mutated and/or inverted by adding swaps to the list for its cell placement which designates cells to be transposed. Genetic crossover can be performed by transposing swaps between the lists for two cell placements. This cell representation and transposition method enables any type of cell transposition to be performed without loss or duplication of cells or generation of illegal placements.
摘要翻译：评估用于集成电路芯片的大量可能的单元布局，以根据诸如互连拥塞的预定标准来确定哪个具有最高适应度。构成来自可能置换群体的细胞的单个排列的每个细胞放置与初始细胞放置结合，表示为可以从初始细胞置换导出细胞置换的单个细胞转置或交换的列表。可以通过向列表中添加交换来进行基因突变和/或反转，用于其细胞放置，其指定要转置的细胞。遗传交叉可以通过在两个单元格展示位置的列表之间转换互换来执行。这种细胞表达和转座方法可以进行任何类型的细胞转座，而不会丢失或重复细胞或产生非法放置。

4. 发明授权

US06493658B1 Optimization processing for integrated circuit physical design automation system using optimally switched fitness improvement algorithms 失效
标题翻译：集成电路物理设计自动化系统优化处理采用最佳切换的健身改进算法
公开(公告)号：US06493658B1
公开(公告)日：2002-12-10
申请号：US08229616
申请日：1994-04-19
申请人： James S. Koford , Michael D. Rostoker , Edwin R. Jones , Douglas B. Boyle , Ranko Scepanovic
发明人： James S. Koford , Michael D. Rostoker , Edwin R. Jones , Douglas B. Boyle , Ranko Scepanovic
IPC分类号： G06F1750
CPC分类号： G06F17/5072
摘要： A physical design automation system produces an optimal placement of microelectronic components or cells on an integrate circuit chip. An initial population of possible cell placements is generated, and repeatedly altered using simulated on or other fitness improvement algorithm to progressively increase the fitnesses (decrease the costs) of the placements. After each alteration step, the fitnesses of the placements are calculated, and less fit placements are discarded in favor of more fit placements. After a termination criterion is reached, the placement having the highest fitness is designated as the optimal placement. Two or more fitness improvement algorithms are available, and are optimally switched from one to the other in accordance with an optimization criterion to maximize convergence of the placements toward the optimal configuration.
摘要翻译：物理设计自动化系统在集成电路芯片上产生微电子元件或单元的最佳布置。生成可能的单元格展示的初始种群，并使用模拟或其他适合度改进算法反复更改，以逐步增加展示位置的适应性（降低成本）。在每个更改步骤之后，计算展示位置的适用性，并且放弃较不适合的展示位置，以便更适合展示位置。达到终止标准后，具有最高适应度的位置被指定为最佳位置。两种或多种健身改进算法是可用的，并且根据优化标准将它们从一个优化地切换到另一个，以最大程度地将展示位置的收敛最大化到最佳配置。

5. 发明授权

US5875117A Simultaneous placement and routing (SPAR) method for integrated circuit physical design automation system 失效
标题翻译：用于集成电路物理设计自动化系统的同时放置和布线（SPAR）方法
公开(公告)号：US5875117A
公开(公告)日：1999-02-23
申请号：US636349
申请日：1996-04-23
申请人： Edwin R. Jones , James S. Koford , Douglas B. Boyle , Ranko Scepanovic , Michael D. Rostoker
发明人： Edwin R. Jones , James S. Koford , Douglas B. Boyle , Ranko Scepanovic , Michael D. Rostoker
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： An initial placement of cells for an integrated circuit chip is decomposed into a hierarchial order of groups of cells. The groups are routed simultaneously using parallel processors, and the results are recomposed to provide a global routing that provides a detailed mapping of cell interconnect congestion in the placement. Areas of high congestion are identified, and a congestion reduction algorithm is applied using the parallel processors to alter the placement in these areas simultaneously. The overall fitness of the placement is then computed, and if it has not attained a predetermined value, the steps of identifying congested areas and applying the congestion reduction algorithm to these areas are repeated. The cumulative error created by altering the placement without repeating the global routing is estimated, and if it exceeds a predetermined value, the global routing is also repeated.
摘要翻译：用于集成电路芯片的单元的初始放置被分解成单元组的分层次序。使用并行处理器同时路由组，并且重新构造结果以提供全局路由，其提供位置中的小区互连拥塞的详细映射。识别高拥塞的区域，并且使用并行处理器来应用拥塞减小算法来同时改变这些区域中的位置。然后计算放置的总体适应度，并且如果没有达到预定值，则重复识别拥挤区域并将这些区域应用拥塞减小算法的步骤。估计通过改变位置而不重复全局路由而产生的累积误差，并且如果超过预定值，则也重复全局路由。

6. 发明授权

US5793644A Cell placement alteration apparatus for integrated circuit chip physical design automation system 失效
公开(公告)号：US5793644A
公开(公告)日：1998-08-11
申请号：US724025
申请日：1996-09-17
申请人： James S. Koford , Ranko Scepanovic , Edwin R. Jones , Douglas B. Boyle , Michael D. Rostoker
发明人： James S. Koford , Ranko Scepanovic , Edwin R. Jones , Douglas B. Boyle , Michael D. Rostoker
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： A large number of possible placements of cells on an integrated circuit chip are generated and evaluated to determine the placement with the highest fitness. Cells for transposition or "swapping" within each placement using genetic algorithms are selected using greedy algorithms based on the fitness of each cell. The cell fitnesses are evaluated in terms of interconnect congestion, total net wire length or other criteria. Cells are selected for genetic crossover by sorting the cells in order of fitness and multiplying the cell fitnesses by weighting factors that increase non-linearly with rank. The cells are selected using linear random number generation such that cells with higher fitnesses have a higher probability of selection. Cells having lowest fitness are selected for mutation, and transposed to random locations, to adjacent locations, with cells having second worst fitness, to the center of mass of the respective interconnect nets, or with two or more cells in a cyclical manner.

7. 发明授权

US5781439A Method for producing integrated circuit chip having optimized cell placement 失效
标题翻译：具有优化电池放置的集成电路芯片的制造方法
公开(公告)号：US5781439A
公开(公告)日：1998-07-14
申请号：US558165
申请日：1995-11-13
申请人： Michael D. Rostoker , James S. Koford , Edwin R. Jones , Douglas B. Boyle , Ranko Scepanovic
发明人： Michael D. Rostoker , James S. Koford , Edwin R. Jones , Douglas B. Boyle , Ranko Scepanovic
IPC分类号： G06F17/50 , G06F17/00
CPC分类号： G06F17/5072
摘要： In a physical design automation system for producing an optimized cell placement for an integrated circuit chip, a placement optimization methodology is decomposed into a plurality of cell placement optimization processes that are performed simultaneously by parallel processors on input data representing the chip. The results of the optimization processes are recomposed to produce an optimized cell placement. The fitness of the optimized cell placement is analyzed, and the parallel processors are controlled to selectively repeat performing the optimization processes for further optimizing the optimized cell placement if the fitness does not satisfy a predetermined criterion. The system can be applied to initial placement, routing, placement improvement and other problems. The processors can perform the same optimization process on different placements, or on areas of a single placement. Alternatively, the processors can perform different optimization processes simultaneously on a single initial placement, with the resulting processed placement having the highest fitness being selected as the optimized placement. The processors can further selectively reprocess areas of a placement having high cell interconnect congestion or other low fitness parameters.
摘要翻译：在用于生成用于集成电路芯片的优化的单元布置的物理设计自动化系统中，布局优化方法被分解成由并行处理器在表示芯片的输入数据上同时执行的多个单元布局优化处理。重组优化过程的结果以产生优化的细胞放置。分析优化的单元布局的适应性，并且如果适合度不满足预定标准，则并行处理器被控制以选择性地重复执行优化处理以进一步优化优化的单元布局。该系统可以应用于初始放置，布线，布局改进等问题。处理器可以对不同的展示位置或单个展示位置执行相同的优化过程。或者，处理器可以在单个初始放置上同时执行不同的优化过程，所得到的经处理的放置具有最佳适合度作为优化的位置。处理器可以进一步选择性地重新处理具有高单元互连拥塞或其他低适应度参数的位置的区域。

8. 发明授权

US5870313A Optimization processing for integrated circuit physical design automation system using parallel moving windows 失效
标题翻译：使用平行移动窗口的集成电路物理设计自动化系统的优化处理
公开(公告)号：US5870313A
公开(公告)日：1999-02-09
申请号：US987865
申请日：1997-12-09
申请人： Douglas B. Boyle , James S. Koford , Ranko Scepanovic , Edwin R. Jones , Michael D. Rostoker
发明人： Douglas B. Boyle , James S. Koford , Ranko Scepanovic , Edwin R. Jones , Michael D. Rostoker
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： One or more non-overlapping moving windows are positioned over a placement of cells for an integrated circuit chip to delineate respective subsets of cells. A fitness improvement operation such as simulated evolution is performed on the subsets simultaneously using parallel processors. The windows are either moved to specifically identified high interconnect congestion areas of the placement, or are moved across the placement in a raster type pattern such that each area of the placement is processed at least once. Exchange of misplaced cells between subsets can be accomplished by dimensioning the windows and designing the window movement pattern such that the subsets overlap. Alternatively, such exchange can be accomplished by using two sets of windows of different sizes. As yet another alternative, the improvement operation can allow misplaced cells to move to a border area outside a window. Each misplaced cell is placed on a list, and then moved to the centroid of a net of cells to which it is connected, which can be outside the subset that originally included the misplaced cell.
摘要翻译：一个或多个非重叠移动窗口位于用于集成电路芯片的单元的放置上以描绘相应的单元子集。使用并行处理器同时对子集执行诸如模拟演化的健身改善操作。窗口被移动到该位置的专门识别的高互连拥塞区域，或以栅格类型模式移动到该位置，使得该位置的每个区域至少被处理一次。可以通过对窗口进行尺寸设计和设计窗口移动图案以使得子集重叠来实现子集之间的错放单元的交换。或者，这种交换可以通过使用两组不同大小的窗口来完成。作为另一替代方案，改进操作可以允许错放的单元移动到窗外的边界区域。每个放错的单元格放在一个列表上，然后移动到它所连接的单元格网格的质心，它可能在最初包含放错单元格的子集之外。

9. 发明授权

US5815403A Fail-safe distributive processing method for producing a highest fitness cell placement for an integrated circuit chip 失效
标题翻译：用于产生用于集成电路芯片的最佳适应度单元布局的故障安全分配处理方法
公开(公告)号：US5815403A
公开(公告)日：1998-09-29
申请号：US229954
申请日：1994-04-19
申请人： Edwin R. Jones , James S. Koford , Douglas B. Boyle , Ranko Scepanovic , Michael D. Rostoker
发明人： Edwin R. Jones , James S. Koford , Douglas B. Boyle , Ranko Scepanovic , Michael D. Rostoker
IPC分类号： G06F9/50 , G06F17/50
CPC分类号： G06F9/5033 , G06F17/5072 , G06F2209/5017
摘要： A physical design automation system for producing a highest fitness cell placement for an integrated circuit chip includes a decomposition/recomposition processor for decomposing a cell placement optimization process into a plurality of tasks and recomposing the highest fitness cell placement from results of performing the tasks. A plurality of worker processors independently perform the tasks and produce results. A host processor distributively assigns the tasks to the worker processors in response to work requests received therefrom. Each worker processor sends a work request to the host processor after completing a task. The host processor maintains a list of unassigned tasks, assigned tasks and completed tasks, and revises the list to redesignate assigned tasks as unassigned tasks upon determining that the list includes no unassigned tasks and at least one assigned task, thus making the system immune to the failure of one or more processors.
摘要翻译：用于产生用于集成电路芯片的最佳适应度单元布置的物理设计自动化系统包括分解/重组处理器，用于将小区布置优化过程分解成多个任务，并且从执行任务的结果重新构建最佳适合度单元布局。多个工作者处理器独立执行任务并产生结果。主机处理器响应于从其接收到的工作请求，向任务处理器分配任务。完成任务后，每个工作处理器向主处理器发送工作请求。主处理器维护未分配任务，分配的任务和完成的任务的列表，并且在确定列表不包含未分配的任务和至少一个分配的任务时，修改列表以重新指定被分配的任务作为未分配的任务，从而使系统免受一个或多个处理器的故障。

10. 发明授权

US5745363A Optimization processing for integrated circuit physical design automation system using optimally switched cost function computations 失效
标题翻译：使用最优切换成本函数计算的集成电路物理设计自动化系统的优化处理
公开(公告)号：US5745363A
公开(公告)日：1998-04-28
申请号：US600588
申请日：1996-02-13
申请人： Michael D. Rostoker , James S. Koford , Edwin R. Jones , Douglas B. Boyle , Ranko Scepanovic
发明人： Michael D. Rostoker , James S. Koford , Edwin R. Jones , Douglas B. Boyle , Ranko Scepanovic
IPC分类号： G06F17/50 , G06F15/00
CPC分类号： G06F17/5072
摘要： In a physical design automation system for producing an optimized cell placement for an integrated circuit chip, a placement optimization methodology is decomposed into a plurality of cell placement optimization processes that are performed simultaneously by parallel processors on input data representing the chip. The results of the optimization processes are recomposed to produce an optimized cell placement. The fitness of the optimized cell placement is analyzed, and the parallel processors are controlled to selectively repeat performing the optimization processes for further optimizing the optimized cell placement if the fitness does not satisfy a predetermined criterion. The system can be applied to initial placement, routing, placement improvement and other problems. The processors can perform the same optimization process on different placements, or on areas of a single placement. Alternatively, the processors can perform different optimization processes simultaneously on a single initial placement, with the resulting processed placement having the highest fitness being selected as the optimized placement. The processors can further selectively reprocess areas of a placement having high cell interconnect congestion or other low fitness parameters.
摘要翻译：在用于产生用于集成电路芯片的优化的单元布局的物理设计自动化系统中，布局优化方法被分解成由并行处理器在表示芯片的输入数据上同时执行的多个单元布局优化处理。重组优化过程的结果以产生优化的细胞放置。分析优化的单元布局的适应性，并且如果适合度不满足预定标准，则并行处理器被控制以选择性地重复执行优化处理以进一步优化优化的单元布局。该系统可以应用于初始放置，布线，布局改进等问题。处理器可以对不同的展示位置或单个展示位置执行相同的优化过程。或者，处理器可以在单个初始放置上同时执行不同的优化过程，所得到的经处理的放置具有最佳适合度作为优化的位置。处理器可以进一步选择性地重新处理具有高单元互连拥塞或其他低适应度参数的位置的区域。

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