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    • 12. 发明申请
    • Semiconductor device
    • 半导体器件
    • US20070164346A1
    • 2007-07-19
    • US10588479
    • 2005-12-19
    • Masaaki Yoshida
    • Masaaki Yoshida
    • H01L29/788
    • G11C16/30G11C16/0433H01L21/823462H01L27/115H01L27/11521H01L27/11524
    • A semiconductor device is disclosed that includes a nonvolatile memory cell having a memory transistor and a selection transistor, and a peripheral circuit transistor. The memory transistor includes a memory gate oxide film that is arranged on a semiconductor substrate, and a floating gate made of polysilicon that is arranged on the memory gate oxide film. The selection transistor is serially connected to the memory transistor and includes a selection gate oxide film that is arranged on the semiconductor substrate, and a selection gate made of polysilicon that is arranged on the selection gate oxide film. The peripheral circuit transistor includes a peripheral circuit gate oxide film that is arranged on the semiconductor substrate, and a peripheral circuit gate made of polysilicon that is arranged on the peripheral circuit gate oxide film. The memory gate oxide film is arranged to be thinner than the peripheral circuit gate oxide film.
    • 公开了一种半导体器件,其包括具有存储晶体管和选择晶体管的非易失性存储单元和外围电路晶体管。 存储晶体管包括布置在半导体衬底上的存储栅极氧化膜和布置在存储栅极氧化膜上的由多晶硅制成的浮置栅极。 选择晶体管串联连接到存储晶体管,并且包括布置在半导体衬底上的选择栅极氧化膜以及布置在选择栅氧化膜上的由多晶硅制成的选择栅极。 外围电路晶体管包括布置在半导体衬底上的外围电路栅极氧化膜,以及设置在外围电路栅氧化膜上的由多晶硅制成的外围电路栅极。 存储栅氧化膜被布置成比外围电路栅极氧化膜薄。
    • 15. 发明授权
    • Interlock apparatus for a transfer machine
    • 用于转印机的联锁装置
    • US06336054B1
    • 2002-01-01
    • US09291045
    • 1999-04-14
    • Yoshiharu OtaMasaaki YoshidaShinya TanoueTatsuya Iwasaki
    • Yoshiharu OtaMasaaki YoshidaShinya TanoueTatsuya Iwasaki
    • G06F1900
    • H01L21/67748H01L21/67242H01L21/67259
    • A processing system for processing a substrate. The processing system includes a plurality of processing machines, a machine movable along a transfer path for transferring the substrate to the machines, a drive unit for driving the machine, and a control unit. The control unit includes a memory for storing a teaching threshold in a teaching mode and a practical operation threshold in a practical operation mode that is higher than the teaching threshold when a moving parameter of the drive unit exceeds a given value. The control unit also includes a controller monitoring a parameter representing a moving state of the drive unit to stop the drive unit when the parameter exceeds the practical operation threshold in the practical operation mode or when the parameter exceeds the teaching threshold in the teaching mode.
    • 一种用于处理衬底的处理系统。 处理系统包括多个处理机器,沿着用于将基板传送到机器的传送路径移动的机器,用于驱动机器的驱动单元和控制单元。 控制单元包括存储器,用于在实际操作模式中存储教学阈值和实际操作阈值,该实际操作模式当驱动单元的移动参数超过给定值时高于教学阈值。 控制单元还包括控制器,当在实践操作模式中参数超过实际操作阈值时或者当教学模式中参数超过教学阈值时,监控表示驱动单元的移动状态的参数以停止驱动单元。
    • 17. 发明授权
    • Method for recording color image, apparatus for recording color image,
and method for controlling recording of color image
    • 用于记录彩色图像的方法,用于记录彩色图像的装置,以及用于控制彩色图像记录的方法
    • US6005596A
    • 1999-12-21
    • US926893
    • 1997-09-10
    • Masaaki YoshidaTomoaki KasugayaShoji NaramotoMasafumi KobayashiNorio Takahashi
    • Masaaki YoshidaTomoaki KasugayaShoji NaramotoMasafumi KobayashiNorio Takahashi
    • B41J2/525B41J2/325B41J2/355B41J2/36H04N1/23H04N1/405H04N1/52H04N1/60H04N1/40
    • H04N1/4056H04N1/52
    • To suppress color moire in a color image recording apparatus, a method for recording a color image by forming record dots of at least first through third colors on a recording medium in a plurality of lines of record dots each extending in a main scan direction and a plurality of rows of record dots each extending in a sub-scan direction, includes the step of forming the record dots of first through third colors with a different disposition pattern effective to avoid the occurrence of color moire. In a preferred embodiment, the disposition pattern of the record dots of one of the three colors comprises an ordinary zigzag printing pattern in which selected ones of the record dots in each line of record dots are shifted in the sub-scan direction by a uniform amount, the disposition pattern of the record dots of another one of the three colors comprises a modified ordinary zigzag pattern in which a dot pitch between lines of record dots in the sub-scan direction is a non-integer multiple of the dot pitch of the ordinary zigzag printing pattern, and the disposition pattern of the remaining one of the three colors comprises a modified ordinary zigzag pattern in which corresponding record dots in adjacent lines of record dots are closer to each other than are the record dots in adjacent rows.
    • 为了抑制彩色图像记录装置中的彩色莫尔条纹,通过在主扫描方向上延伸的多行记录点的记录介质上形成至少第一至第三颜色的记录点来记录彩色图像的方法,以及 多个沿副扫描方向延伸的记录点列包括以不同的配置图案形成第一至第三颜色的记录点的步骤,以有效避免色莫尔的出现。 在一个优选实施例中,三种颜色之一的记录点的配置图案包括常规的之字形打印模式,其中每行记录点中的所选记录点在副扫描方向上以均匀的量移位 三种颜色中的另一种的记录点的配置图案包括修正的普通之字形图案,其中副扫描方向上的记录点线之间的点间距是普通的点间距的非整数倍 锯齿形印刷图案,并且三种颜色中的剩余颜色的配置图案包括修改的普通之字形图案,其中记录点的相邻行中的相应记录点比相邻行中的记录点更接近。
    • 18. 发明授权
    • Semiconductor integrated circuit device
    • 半导体集成电路器件
    • US5410173A
    • 1995-04-25
    • US20793
    • 1993-02-22
    • Ken'ichi KikushimaMasaaki YoshidaShinobu Yabuki
    • Ken'ichi KikushimaMasaaki YoshidaShinobu Yabuki
    • H01L23/485H01L23/528H01L23/532H01L27/02H01L29/78H01L33/00
    • H01L23/53257H01L23/485H01L23/5286H01L24/06H01L27/0207H01L2224/05554H01L2924/10253H01L2924/12036H01L2924/1305H01L2924/1306H01L2924/13091H01L2924/14
    • In a semiconductor integrated circuit device having cells comprising circuit elements including MISFETs, and a multi-layer wiring structure, wirings of a first layer connected to semiconductor regions of the MISFETs (source and drain regions) are formed almost in the entire area over the regions to shunt the regions. Power supply wiring are formed of second layer wirings. First layer wirings and the semiconductor regions are connected through a plurality of contact holes. The power supply wirings are formed to cover at least part of the semiconductor regions. In accordance with another aspect, macro-cells are formed by basic cells, including a plurality of MISFETs with the direction of gate length aligned in a first direction, regularly arranged in the first direction and in a second intersecting direction. The MISFETs in each basic cell are interconnected by a first-layer signal wiring, basic cells adjacently arranged in the second direction are interconnected by a first-layer signal wiring extending in the second direction, and basic cells adjacently arranged in the first direction are interconnected by a second-layer signal wiring extending in the first direction. The MISFETs in basic cells adjacently arranged in the first direction receive power from a second-layer power wiring located in the same layer of the second-layer signal wiring and extended in the same first direction. A fourth-layer power supply wiring and a fourth-layer signal wiring, both extending in the first direction, are also provided.
    • 在具有包括MISFET和多层布线结构的电路元件的单元的半导体集成电路器件中,连接到MISFET(源极和漏极区域)的半导体区域的第一层的布线几乎在该区域的整个区域中形成 分流区域。 电源布线由第二层布线形成。 第一层布线和半导体区域通过多个接触孔连接。 形成电源布线以覆盖半导体区域的至少一部分。 根据另一方面,宏单元由基本单元形成,包括多个MISFET,其栅极长度方向在第一方向上对齐,在第一方向和第二相交方向上规则地排列。 每个基本单元中的MISFET通过第一层信号布线互连,在第二方向上相邻布置的基本单元通过沿第二方向延伸的第一层信号布线互连,并且在第一方向上相邻布置的基本单元互连 通过沿第一方向延伸的第二层信号线。 在第一方向上相邻布置的基本单元中的MISFET从位于第二层信号布线的同一层的第二层电力布线接收电力并沿相同的第一方向延伸。 还提供了沿第一方向延伸的第四层电源布线和第四层信号布线。