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1. 发明授权

US06677214B1 Semiconductor device and method of fabricating the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US06677214B1
公开(公告)日：2004-01-13
申请号：US09593657
申请日：2000-06-12
申请人： Masahiro Shindo , Daisuke Kosaka , Tetsuo Hikawa , Akira Takata , Yukihiro Ukai , Takashi Sawada , Toshifumi Asakawa
发明人： Masahiro Shindo , Daisuke Kosaka , Tetsuo Hikawa , Akira Takata , Yukihiro Ukai , Takashi Sawada , Toshifumi Asakawa
IPC分类号： H01L21331
CPC分类号： H01J37/32678 , B81C1/0038 , C23C16/48 , C23C16/486 , C23C16/511 , C23C16/56 , G01L9/0042 , G01P15/0802 , G02F2001/136281 , H01H59/0009 , H01L27/12 , H01L27/1203 , H01L31/03762 , H01L31/0693 , H01L31/0725 , H01L31/073 , H01L31/078 , H01L31/1804 , H01L31/1828 , H01L31/186 , H02N1/002 , Y02E10/543 , Y02E10/544 , Y02E10/547 , Y02E10/548 , Y02P70/521
摘要： In order to easily and accurately manufacture a micromachine comprising a member which is made of a single-crystalline material and having a complicated structure, an uppermost layer (1104) of a single-crystalline Si substrate (1102) whose (100) plane is upwardly directed is irradiated with Ne atom currents from a plurality of prescribed directions, so that the crystal orientation of the uppermost layer (1104) is converted to such orientation that the (111) plane is upwardly directed. A masking member (106) is employed as a shielding member to anisotropically etch the substrate (1102) from its bottom surface, thereby forming a V-shaped groove (1112). At this time, the uppermost layer (1104) serves as an etching stopper. Thus, it is possible to easily manufacture a micromachine having a single-crystalline diaphragm having a uniform thickness. A micromachine having a complicated member such as a diagram which is made of a single-crystalline material can be easily manufactured through no junction.
摘要翻译：为了容易且精确地制造包括由单晶材料制成且具有复杂结构的构件的微加工机构，（100）面向上的单晶Si衬底（1102）的最上层（1104）从多个规定方向对Ne原子电流进行照射，使得最上层（1104）的晶体取向被转换为（111）面向上方向的取向。采用掩模构件（106）作为屏蔽构件，从其底面各向异性地蚀刻衬底（1102），从而形成V形槽（1112）。此时，最上层（1104）用作蚀刻停止器。因此，可以容易地制造具有均匀厚度的单晶隔膜的微加工机。具有复合构件的微机械，例如由单晶材料制成的图可以容易地通过无接合制造。

2. 发明授权

US06177706B1 Field-effect thin-film transistor device 失效
标题翻译：场效应薄膜晶体管器件
公开(公告)号：US06177706B1
公开(公告)日：2001-01-23
申请号：US08918138
申请日：1997-08-27
申请人： Masahiro Shindo , Daisuke Kosaka , Tetsuo Hikawa , Akira Takata , Yukihiro Ukai , Takashi Sawada , Toshifumi Asakawa
发明人： Masahiro Shindo , Daisuke Kosaka , Tetsuo Hikawa , Akira Takata , Yukihiro Ukai , Takashi Sawada , Toshifumi Asakawa
IPC分类号： H01L2701
CPC分类号： H01J37/32678 , B81B2203/0109 , B81B2203/0118 , B81B2203/0127 , B81C1/0038 , B81C2201/0109 , C23C16/48 , C23C16/486 , C23C16/511 , C23C16/56 , G01L9/0042 , G01P15/0802 , G02F2001/136281 , H01H59/0009 , H01L27/12 , H01L27/1203 , H01L31/03762 , H01L31/0693 , H01L31/0725 , H01L31/073 , H01L31/078 , H01L31/1804 , H01L31/1828 , H01L31/186 , H02N1/002 , Y02E10/543 , Y02E10/544 , Y02E10/547 , Y02E10/548 , Y02P70/521
摘要： In order to easily and accurately manufacture a micromachine comprising a member which is made of a single-crystalline material and having a complicated structure, an uppermost layer (1104) of a single-crystalline Si substrate (1102) whose (100) plane is upwardly directed is irradiated with Ne atoms currents from a plurality of prescribed directions, so that the crystal orientation of the uppermost layer (1104) is converted to such orientation that the (111) plane is upwardly directed. A masking member (106) is employed as a shielding member to anistropically etch the substrate (1102) from its bottom surface, thereby forming a V-shaped groove (1112). At this time, the uppermost layer (1104) serves as an etching stopper. Thus, it is possible to easily manufacture a micromachine having a single-crystalline diaphragm having a uniform thickness. A micromachine having a complicated member such as a diagram which is made of a single-crystalline material can be easily manufactured through no junction.
摘要翻译：为了容易且精确地制造包括由单晶材料制成且具有复杂结构的构件的微加工机构，（100）面向上的单晶Si衬底（1102）的最上层（1104）从多个规定方向照射Ne原子电流，使得最上层（1104）的晶体取向被转换成使得（111）面向上指向的取向。采用掩模构件（106）作为屏蔽构件，从其底面对基板（1102）进行静电蚀刻，从而形成V形槽（1112）。此时，最上层（1104）用作蚀刻停止器。因此，可以容易地制造具有均匀厚度的单晶隔膜的微加工机。具有复合构件的微机械，例如由单晶材料制成的图可以容易地通过无接合制造。

3. 发明授权

US5565697A Semiconductor structure having island forming grooves 失效
标题翻译：具有岛形成槽的半导体结构
公开(公告)号：US5565697A
公开(公告)日：1996-10-15
申请号：US458800
申请日：1995-06-02
申请人： Toshifumi Asakawa , Daisuke Kosaka , Haruo Nakayama
发明人： Toshifumi Asakawa , Daisuke Kosaka , Haruo Nakayama
IPC分类号： H01L21/20 , H01L21/268 , H01L21/74 , H01L21/762 , H01L21/822 , H01L21/782 , H01L27/12 , H01L29/06
CPC分类号： H01L21/8221 , H01L21/2026 , H01L21/268 , H01L21/743 , H01L21/76264 , H01L21/76272 , H01L21/76281
摘要： A semiconductor substrate comprises a foundation, a semiconductor monocrystalline film formed on the foundation, and a high-melting-point metal film or a high-melting-point metal alloy film disposed in at least part of a region between the semiconductor monocrystalline film and the foundation. The high-melting-point metal film disposed below the semiconductor monocrystalline film can be utilized as a conductor in a semiconductor device.
摘要翻译：半导体衬底包括基底，形成在基底上的半导体单晶膜，以及高熔点金属膜或高熔点金属合金膜，其设置在半导体单晶膜和基础。设置在半导体单晶膜下方的高熔点金属膜可以用作半导体器件中的导体。

4. 发明授权

US5173446A Semiconductor substrate manufacturing by recrystallization using a cooling medium 失效
标题翻译：使用冷却介质通过重结晶制造半导体衬底
公开(公告)号：US5173446A
公开(公告)日：1992-12-22
申请号：US715717
申请日：1991-06-13
申请人： Toshifumi Asakawa , Daisuke Kosaka , Haruo Nakayama
发明人： Toshifumi Asakawa , Daisuke Kosaka , Haruo Nakayama
IPC分类号： H01L21/20 , H01L21/268 , H01L21/74 , H01L21/762 , H01L21/822
CPC分类号： H01L21/743 , H01L21/2026 , H01L21/268 , H01L21/76264 , H01L21/8221 , H01L21/76272 , H01L21/76281 , Y10S117/904 , Y10S117/905
摘要： A semiconductor substrate comprises a foundation, a semiconductor monocrystalline film formed on the foundation, and a high-melting-point metal film or a high-melting-point metal alloy film disposed in at least part of a region between the semiconductor monocrystalline film and the foundation. The high-melting-point metal film disposed below the semiconductor monocrystalline film can be utilized as a conductor in a semiconductor device.
摘要翻译：半导体衬底包括基底，形成在基底上的半导体单晶膜，以及高熔点金属膜或高熔点金属合金膜，其设置在半导体单晶膜和基础。设置在半导体单晶膜下方的高熔点金属膜可以用作半导体器件中的导体。

5. 发明授权

US5031019A Method for manufacturing a semiconductor device having isolated islands and its resulting structure 失效
标题翻译：用于制造具有隔离岛的半导体器件的方法及其结果
公开(公告)号：US5031019A
公开(公告)日：1991-07-09
申请号：US199860
申请日：1988-05-27
申请人： Daisuke Kosaka , Yoshinori Ueda , Tetsuo Hikawa , Masami Nishikawa
发明人： Daisuke Kosaka , Yoshinori Ueda , Tetsuo Hikawa , Masami Nishikawa
IPC分类号： H01L21/82 , H01L21/8238 , H01L21/8247 , H01L21/8249 , H01L27/06 , H01L27/092 , H01L27/10 , H01L27/115 , H01L27/118 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11896
摘要： A method for manufacturing a Bi-CMOS device by preparing both of bipolar and MOS standard cells in a library is provided. A substrate of a first conductivity type is provided and a plurality of buried layers of a second conductivity type are formed on selected locations of the substrate. Then an epitaxial layer of the first conductivity type is formed on the substrate covering the buried layers. Then a plurality of wells of the second conductivity type are formed in the epitaxial layer such that each of the wells extends through the epitaxial layer from the top surface to at least a portion of the corresponding buried layer to thereby define a plurality of electrically isolated islands in the epitaxial layer. Then a bipolar transistor is formed in at least one of the islands with a MOS transistor formed in at least another of the islands.
摘要翻译：提供了一种通过在库中制备双极和MOS标准单元来制造Bi-CMOS器件的方法。提供第一导电类型的衬底，并且在衬底的选定位置上形成第二导电类型的多个掩埋层。然后在覆盖埋层的基板上形成第一导电类型的外延层。然后在外延层中形成第二导电类型的多个阱，使得每个阱从顶表面延伸穿过外延层至相应掩埋层的至少一部分，从而限定多个电隔离岛在外延层中。然后在至少一个岛上形成双极晶体管，其中MOS晶体管形成在至少另一个岛中。

6. 发明授权

US4884051A Semiconductor diffusion type force sensing apparatus 失效
标题翻译：半导体扩散型力传感装置
公开(公告)号：US4884051A
公开(公告)日：1989-11-28
申请号：US215412
申请日：1988-07-05
申请人： Junichi Takahashi , Daisuke Kosaka , Hirotoshi Eguchi , Shoji Matsumoto , Takashi Akahori , Hiroshi Yamazaki , Kouji Izumi
发明人： Junichi Takahashi , Daisuke Kosaka , Hirotoshi Eguchi , Shoji Matsumoto , Takashi Akahori , Hiroshi Yamazaki , Kouji Izumi
IPC分类号： G01L1/18 , G01L5/16 , H01L41/04
CPC分类号： G01L5/162 , G01L1/18
摘要： A semiconductor diffusion type force sensing apparatus includes a plate-like semiconductor substrate formed by a single crystal material, and a plurality of sensing elements each constituted by a substantially rectangular impurity-diffused region formed in the semiconductor substrate. The sensing elements have an electric resistance variable in accordance with a deformation thereof due to an external force exerted on the semiconductor substrate. The sensing elements are arranged in a direction in which a longitudinal direction of each of the sensing elements coincides with a crystal orientation of the semiconductor substrate having an external value of a longitudinal piezoresistance coefficient of the impurity-diffused region.
摘要翻译：半导体扩散型力感测装置包括由单晶材料形成的板状半导体衬底和多个感测元件，每个感测元件由形成在半导体衬底中的大致矩形的杂质扩散区域构成。感测元件由于施加在半导体衬底上的外力而具有根据其变形而变化的电阻。感测元件布置在每个感测元件的纵向方向与具有杂质扩散区域的纵向压阻系数的外部值的半导体衬底的晶体取向一致的方向上布置。

7. 发明授权

US06225668B1 Semiconductor device having a single crystal gate electrode and insulation 失效
标题翻译：具有单晶栅电极和绝缘的半导体器件
公开(公告)号：US06225668B1
公开(公告)日：2001-05-01
申请号：US08917268
申请日：1997-08-25
申请人： Masahiro Shindo , Daisuke Kosaka , Tetsuo Hikawa , Akira Takata , Yukihiro Ukai , Takashi Sawada , Toshifumi Asakawa
发明人： Masahiro Shindo , Daisuke Kosaka , Tetsuo Hikawa , Akira Takata , Yukihiro Ukai , Takashi Sawada , Toshifumi Asakawa
IPC分类号： H01L2336
CPC分类号： H01J37/32678 , B81B2203/0109 , B81B2203/0118 , B81B2203/0127 , B81C1/0038 , B81C2201/0109 , C23C16/48 , C23C16/486 , C23C16/511 , C23C16/56 , G01L9/0042 , G01P15/0802 , G02F2001/136281 , H01H59/0009 , H01L27/12 , H01L27/1203 , H01L31/03762 , H01L31/0693 , H01L31/0725 , H01L31/073 , H01L31/078 , H01L31/1804 , H01L31/1828 , H01L31/186 , H02N1/002 , Y02E10/543 , Y02E10/544 , Y02E10/547 , Y02E10/548 , Y02P70/521
摘要： In order to easily and accurately manufacture a micromachine comprising a member which is made of a single-crystalline material and having a complicated structure, an uppermost layer (1104) of a single-crystalline Si substrate (1102) whose (100) plane is upwardly directed is irradiated with Ne atom currents from a plurality of prescribed directions, so that the crystal orientation of the uppermost layer (1104) is converted to such orientation that the (111) plane is upwardly directed. A masking member (106) is employed as a shielding member to anisotropically etch the substrate (1102) from its bottom surface, thereby forming a V-shaped groove (1112). At this time, the uppermost layer (1104) serves as an etching stopper. Thus, it is possible to easily manufacture a micromachine having a single-crystalline diaphragm having a uniform thickness. A micromachine having a complicated member such as a diagram which is made of a single-crystalline material can be easily manufactured through no junction.
摘要翻译：为了容易且精确地制造包括由单晶材料制成且具有复杂结构的构件的微加工机构，（100）面向上的单晶Si衬底（1102）的最上层（1104）从多个规定方向对Ne原子电流进行照射，使得最上层（1104）的晶体取向被转换为（111）面向上方向的取向。采用掩模构件（106）作为屏蔽构件，从其底面各向异性地蚀刻衬底（1102），从而形成V形槽（1112）。此时，最上层（1104）用作蚀刻停止器。因此，可以容易地制造具有均匀厚度的单晶隔膜的微加工机。具有复合构件的微机械，例如由单晶材料制成的图可以容易地通过无接合制造。

8. 发明授权

US5459346A Semiconductor substrate with electrical contact in groove 失效
标题翻译：半导体衬底与沟槽中的电接触
公开(公告)号：US5459346A
公开(公告)日：1995-10-17
申请号：US341265
申请日：1994-11-17
申请人： Toshifumi Asakawa , Daisuke Kosaka , Haruo Nakayama
发明人： Toshifumi Asakawa , Daisuke Kosaka , Haruo Nakayama
IPC分类号： H01L21/20 , H01L21/268 , H01L21/74 , H01L21/762 , H01L21/822 , H01L21/782 , H01L27/12 , H01L29/06
CPC分类号： H01L21/8221 , H01L21/2026 , H01L21/268 , H01L21/743 , H01L21/76264 , H01L21/76272 , H01L21/76281
摘要： A semiconductor substrate comprises a foundation, a semiconductor monocrystalline film formed on the foundation, and a high-melting-point metal film or a high-melting-point metal alloy film disposed in at least part of a region between the semiconductor monocrystalline film and the foundation. The high-melting-point metal film disposed below the semiconductor monocrystalline film can be utilized as a conductor in a semiconductor device.
摘要翻译：半导体衬底包括基底，形成在基底上的半导体单晶膜，以及高熔点金属膜或高熔点金属合金膜，其设置在半导体单晶膜和基础。设置在半导体单晶膜下方的高熔点金属膜可以用作半导体器件中的导体。

9. 发明授权

US5077235A Method of manufacturing a semiconductor integrated circuit device having SOI structure 失效
标题翻译：具有SOI结构的半导体集成电路器件的制造方法
公开(公告)号：US5077235A
公开(公告)日：1991-12-31
申请号：US466059
申请日：1990-01-16
申请人： Daisuke Kosaka
发明人： Daisuke Kosaka
IPC分类号： H01L21/20 , H01L21/268 , H01L21/762
CPC分类号： H01L21/76248 , H01L21/2026 , H01L21/268 , Y10S148/152
摘要： A method of manufacturing a semiconductor integrated circuit device having a SOI structure includes the following steps. The first step is to form a semiconductor layer on a dielectric substrate. The second step is to form an oxide layer on the formed semiconductor layer. The third step is to form a nitride layer on the formed oxide layer. The fourth step is to remove a part of a plurality of layers composed of the semiconductor layer, the oxide layer, and a nitride layer so as to form a separated region in the layers. The fifth step is to coat a cooling agent on a surface of the nitride layer. The sixth step is to irradiate an energy beam from an outer surface of the cooling agent so as to monocrystallize the semiconductor layer. The seventh step is to remove the cooling agent from the surface of the nitride layer. And the final step is to oxidize a portion of the semiconductor layer located in the separated region by using the nitride layer. A semiconductor integrated circuit device having a SOI structure includes a semiconductor layer formed on a dielectric substrate, an oxide film formed on the semiconductor layer, a nitride layer formed on the oxide film, and a monocrystallized and oxidized semiconductor layer formed in hole portions formed in the semiconductor layer passing through the oxide layer and the nitride layer.
摘要翻译：制造具有SOI结构的半导体集成电路器件的方法包括以下步骤。第一步是在电介质基板上形成半导体层。第二步是在形成的半导体层上形成氧化物层。第三步是在所形成的氧化物层上形成氮化物层。第四步骤是去除由半导体层，氧化物层和氮化物层组成的多个层的一部分，以在层中形成分离的区域。第五步是在氮化物层的表面上涂覆冷却剂。第六步是从冷却剂的外表面照射能量束，以使半导体层单晶化。第七步骤是从氮化物层的表面除去冷却剂。最后一步是通过使用氮化物层来氧化位于分离区域中的半导体层的一部分。具有SOI结构的半导体集成电路器件包括形成在电介质基板上的半导体层，形成在半导体层上的氧化膜，形成在氧化物膜上的氮化物层，以及形成在孔部中的单晶氧化半导体层半导体层通过氧化物层和氮化物层。

10. 发明授权

US5041847A Thermal head 失效
标题翻译：热头
公开(公告)号：US5041847A
公开(公告)日：1991-08-20
申请号：US570397
申请日：1990-08-21
申请人： Shoji Matsumoto , Daisuke Kosaka , Masaaki Yoshida , Hidehito Kitakado , Kenji Fujita
发明人： Shoji Matsumoto , Daisuke Kosaka , Masaaki Yoshida , Hidehito Kitakado , Kenji Fujita
IPC分类号： B41J2/335
CPC分类号： B41J2/3353 , B41J2/33535 , B41J2/3355 , B41J2/3357
摘要： A thermal head comprising a substrate, a heat-resistant dielectric resin layer disposed on the substrate, a resistor layer disposed on the resin layer for forming a plurality of heating elements and an electrode layer disposed on the resistor layer for forming electrodes connecting to the heating elements. A protection film covers an end of the substrate and each end of the layers which is substantially in the same plane as the substrate end.
摘要翻译：一种热敏头，包括基底，设置在基底上的耐热电介质树脂层，设置在用于形成多个加热元件的树脂层上的电阻层和设置在电阻层上的电极层，用于形成连接到加热的电极元素。保护膜覆盖基板的端部，并且层的每个端部基本上在与基板端部相同的平面中。

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