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1. 发明授权

US5410173A Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件
公开(公告)号：US5410173A
公开(公告)日：1995-04-25
申请号：US20793
申请日：1993-02-22
申请人： Ken'ichi Kikushima , Masaaki Yoshida , Shinobu Yabuki
发明人： Ken'ichi Kikushima , Masaaki Yoshida , Shinobu Yabuki
IPC分类号： H01L23/485 , H01L23/528 , H01L23/532 , H01L27/02 , H01L29/78 , H01L33/00
CPC分类号： H01L23/53257 , H01L23/485 , H01L23/5286 , H01L24/06 , H01L27/0207 , H01L2224/05554 , H01L2924/10253 , H01L2924/12036 , H01L2924/1305 , H01L2924/1306 , H01L2924/13091 , H01L2924/14
摘要： In a semiconductor integrated circuit device having cells comprising circuit elements including MISFETs, and a multi-layer wiring structure, wirings of a first layer connected to semiconductor regions of the MISFETs (source and drain regions) are formed almost in the entire area over the regions to shunt the regions. Power supply wiring are formed of second layer wirings. First layer wirings and the semiconductor regions are connected through a plurality of contact holes. The power supply wirings are formed to cover at least part of the semiconductor regions. In accordance with another aspect, macro-cells are formed by basic cells, including a plurality of MISFETs with the direction of gate length aligned in a first direction, regularly arranged in the first direction and in a second intersecting direction. The MISFETs in each basic cell are interconnected by a first-layer signal wiring, basic cells adjacently arranged in the second direction are interconnected by a first-layer signal wiring extending in the second direction, and basic cells adjacently arranged in the first direction are interconnected by a second-layer signal wiring extending in the first direction. The MISFETs in basic cells adjacently arranged in the first direction receive power from a second-layer power wiring located in the same layer of the second-layer signal wiring and extended in the same first direction. A fourth-layer power supply wiring and a fourth-layer signal wiring, both extending in the first direction, are also provided.
摘要翻译：在具有包括MISFET和多层布线结构的电路元件的单元的半导体集成电路器件中，连接到MISFET（源极和漏极区域）的半导体区域的第一层的布线几乎在该区域的整个区域中形成分流区域。电源布线由第二层布线形成。第一层布线和半导体区域通过多个接触孔连接。形成电源布线以覆盖半导体区域的至少一部分。根据另一方面，宏单元由基本单元形成，包括多个MISFET，其栅极长度方向在第一方向上对齐，在第一方向和第二相交方向上规则地排列。每个基本单元中的MISFET通过第一层信号布线互连，在第二方向上相邻布置的基本单元通过沿第二方向延伸的第一层信号布线互连，并且在第一方向上相邻布置的基本单元互连通过沿第一方向延伸的第二层信号线。在第一方向上相邻布置的基本单元中的MISFET从位于第二层信号布线的同一层的第二层电力布线接收电力并沿相同的第一方向延伸。还提供了沿第一方向延伸的第四层电源布线和第四层信号布线。

2. 发明授权

US5514895A Semiconductor integrated circuit device 失效
公开(公告)号：US5514895A
公开(公告)日：1996-05-07
申请号：US395997
申请日：1995-02-28
申请人： Ken'ichi Kikushima , Masaaki Yoshida , Shinobu Yabuki
发明人： Ken'ichi Kikushima , Masaaki Yoshida , Shinobu Yabuki
IPC分类号： H01L23/485 , H01L23/528 , H01L23/532 , H01L27/02 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113
CPC分类号： H01L23/53257 , H01L23/485 , H01L23/5286 , H01L24/06 , H01L27/0207 , H01L2224/05554 , H01L2924/10253 , H01L2924/12036 , H01L2924/1305 , H01L2924/1306 , H01L2924/13091 , H01L2924/14
摘要： In a semiconductor integrated circuit device having cells comprising circuit elements including MISFETs, and a multi-layer wiring structure, wirings of a first layer connected to semiconductor regions of the MISFETs (source and drain regions) are formed almost in the entire area over the regions to shunt the regions. Power supply wiring are formed of second layer wirings. First layer wirings and the semiconductor regions are connected through a plurality of contact holes. The power supply wirings are formed to cover at least part of the semiconductor regions. In accordance with another aspect, macro-cells are formed by basic cells, including a plurality of MISFETs with the direction of gate length aligned in a first direction, regularly arranged in the first direction and in a second intersecting direction. The MISFETs in each basic cell are interconnected by a first-layer signal wiring, basic cells adjacently arranged in the second direction are interconnected by a first-layer signal wiring extending in the second direction, and basic cells adjacently arranged in the first direction are interconnected by a second-layer signal wiring extending in the first direction. The MISFETs in basic cells adjacently arranged in the first direction receive power from a second-layer power wiring located in the same layer of the second-layer signal wiring and extended in the same first direction. A fourth-layer power supply wiring and a fourth-layer signal wiring, both extending in the first direction, are also provided.

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