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11. 发明申请

US20150163019A1 EFFICIENT LINK LAYER RETRY PROTOCOL UTILIZING IMPLICIT ACKNOWLEDGEMENTS 有权
标题翻译：有效的链接层复原协议使用隐含的确认
公开(公告)号：US20150163019A1
公开(公告)日：2015-06-11
申请号：US14099323
申请日：2013-12-06
申请人： Mark S. Birrittella
发明人： Mark S. Birrittella
IPC分类号： H04L1/08 , H04L1/16
CPC分类号： H04L1/1657 , G06F9/00 , H04L1/08 , H04L1/1867 , H04L1/1874 , H04L67/104
摘要： Methods, apparatus, and systems for implementing a link layer retry protocol utilizing implicit ACKnowledgements (ACKs). Peer link interfaces are configured to facilitate confirmed error-free delivery of link-layer packets through use of implicit ACKs, while also providing retransmission of packets for which errors are detected and guaranteeing the link control data is either successfully received or data transfer over the link is prevented. In conjunction with transmitting packets, reliable packets are copied into sequential slots in a replay buffer. Each link interface tracks the slot at which each reliable packet is buffered, and in response to detection of an error, a retry request is sent to the transmit-side to retransmit the errant packet. The previously buffered copy of the errant packet is retrieved from the replay buffer and retransmitted. Through use of a link roundtrip detection mechanism, absence of a retry request by the time a replay buffer has returned to the slot of a reliable packet (plus a predetermined number of additional transfer cycles, if applicable) provides an implicit ACK that the packet was received without error.
摘要翻译：用于实现使用隐式确认（ACK）的链路层重试协议的方法，装置和系统。对等链路接口被配置为通过使用隐式ACK来促进确认的无差错地传送链路层分组，同时还提供重传检测到错误的分组，并且确保链路控制数据被成功接收或通过链路的数据传送被阻止结合发送分组，可靠的分组被复制到重播缓冲器中的顺序时隙中。每个链路接口跟踪缓冲每个可靠分组的时隙，并且响应于检测到错误，重发请求被发送到发送侧以重传错误分组。从重放缓冲区中检索先前缓存的错误数据包的副本并重发。通过使用链路往返检测机制，在重播缓冲器已经返回到可靠分组的时隙（加上预定数量的附加传输周期（如果适用）的时候）没有重试请求提供了分组是收到没有错误。

12. 发明申请

US20150163014A1 LANE ERROR DETECTION AND LANE REMOVAL MECHANISM TO REDUCE THE PROBABILITY OF DATA CORRUPTION 有权
标题翻译： LANE错误检测和LANE移除机制，以降低数据损坏的可行性
公开(公告)号：US20150163014A1
公开(公告)日：2015-06-11
申请号：US14099345
申请日：2013-12-06
申请人： Mark S. Birrittella
发明人： Mark S. Birrittella
IPC分类号： H04L1/00 , H03M13/09
CPC分类号： H04L1/0045 , H03M13/09 , H04L1/0058 , H04L1/0061 , H04L1/0071 , H04L1/08 , H04L1/1607 , H04L1/1657 , H04L1/1874
摘要： Method, apparatus, and systems for detecting lane errors and removing errant lanes in multi-lane links. Data comprising link packets is split into a plurality of bitstreams and transmitted over respective lanes of a multi-lane link in parallel. The bitstream data is received at multiple receive lanes of a receiver port and processed to reassemble link packets and to calculate a CRC over the data received on each lane. The link packets include a transmitted CRC that is compared to a received CRC to detect link packet errors. Upon detection of a link packet error, per-lane or per transfer group CRC values are stored, and a retry request is issued to retransmit the bad packet. In conjunction with receipt of the retransmitted packet, per-lane or per transfer group CRC values are recalculated over the received data and compared with the stored per-lane or per transfer group CRC values to detect the lane causing the link packet error.
摘要翻译：用于检测车道错误和消除多车道链路中的错误车道的方法，装置和系统。包括链路分组的数据被分割成多个比特流并且并行地在多通道链路的各个通道上传输。比特流数据在接收器端口的多个接收通道处被接收并被处理以重新组合链路分组并且计算在每个通道上接收的数据上的CRC。链路分组包括与接收到的CRC进行比较的发送CRC，以检测链路分组错误。在检测到链路分组错误时，存储每通道或每个传输组CRC值，并且发出重试请求以重新发送坏数据包。结合接收重传的分组，每通道或每个传输组CRC值在接收的数据上重新计算，并与存储的每通道或每个传输组CRC值进行比较，以检测引起链路分组错误的通道。

13. 发明授权

US06266759B1 Register scoreboarding to support overlapped execution of vector memory reference instructions in a vector processor 失效
标题翻译：注册记分牌以支持向量处理器中向量存储器参考指令的重叠执行
公开(公告)号：US06266759B1
公开(公告)日：2001-07-24
申请号：US09211118
申请日：1998-12-14
申请人： Mark S. Birrittella
发明人： Mark S. Birrittella
IPC分类号： G06F1500
CPC分类号： G06F9/3836 , G06F9/3824 , G06F9/3838 , G06F9/3857
摘要： A vector-processor SIMD RISC computer system uses virtual addressing and overlapped instruction execution. Indicators for each of the architected registers assume different states when an instruction, overlapped with a vector memory-reference instruction, has or has not read from or written to a particular register. Multiple overlapped vector memory-reference instructions are assigned separate sets of indicators. Indicators in a certain state prevents a subsequent overlapped instruction from writing to its associated register.
摘要翻译：矢量处理器SIMD RISC计算机系统使用虚拟寻址和重叠指令执行。当与矢量存储器参考指令重叠的指令已经或没有从特定寄存器读取或写入特定寄存器时，每个架构寄存器的指示器都采用不同的状态。多个重叠向量存储器参考指令被分配指定的组。处于某种状态的指示器阻止后续的重叠指令写入其关联的寄存器。

14. 发明授权

US4663831A Method of forming transistors with poly-sidewall contacts utilizing deposition of polycrystalline and insulating layers combined with selective etching and oxidation of said layers 失效
标题翻译：利用多晶层和绝缘层的沉积与所述层的选择性蚀刻和氧化结合形成具有多侧壁接触的晶体管的方法
公开(公告)号：US4663831A
公开(公告)日：1987-05-12
申请号：US785640
申请日：1985-10-08
申请人： Mark S. Birrittella , Hang M. Liaw , Robert H. Reuss
发明人： Mark S. Birrittella , Hang M. Liaw , Robert H. Reuss
IPC分类号： H01L21/8222 , H01L21/285 , H01L21/331 , H01L27/082 , H01L29/73 , H01L21/20 , H01L21/76
CPC分类号： H01L21/28531 , H01L29/66287 , H01L29/732 , Y10S148/011 , Y10S148/02 , Y10S148/026 , Y10S148/05 , Y10S148/117 , Y10S148/164
摘要： Improved bipolar transistors having minimum base-collector and collector-substrate junction area are formed by using multiple polycrystalline (e.g. doped poly silicon) layers to make lateral contact to a pillar shaped single crystal device region. The lateral poly silicon contacts are isolated from each other and the substrate and extend to the upper surface of the device for external connections. The structure is made by depositing two dielectric-poly layer sandwiches, etching and oxidizing part of the poly silicon layers to provide isolated overlapping poly silicon regions, etching a first hole through both poly silicon regions to the substrate, etching a second hole to the lower poly silicon layer, and filling the first and second holes with single and poly-crystalline silicon, respectfully. A sidewall oxide is formed at the periphery of the top of the single crystal pillar for defining the emitter location without additional masking.
摘要翻译：通过使用多个多晶（例如掺杂多晶硅）层来形成与柱状单晶器件区域的横向接触，形成具有最小基极集电极和集电极 - 衬底结面积的改进的双极晶体管。侧面多晶硅接触件彼此隔离并且衬底并延伸到设备的上表面用于外部连接。该结构通过沉积两个电介质多层三明治，蚀刻和氧化多个硅层的一部分而制成，以提供隔离的重叠多晶硅区域，将通过两个多晶硅区域的第一孔蚀刻到衬底，将第二个孔蚀刻到较低层多晶硅层，并且用单晶和多晶硅填充第一和第二孔。在单晶柱顶部的周围形成侧壁氧化物，用于限定发射器位置而不需要附加掩模。

15. 发明授权

US4656495A Bipolar ram cell and process 失效
标题翻译：双极柱塞电池和工艺
公开(公告)号：US4656495A
公开(公告)日：1987-04-07
申请号：US750121
申请日：1985-07-01
申请人： Mark S. Birrittella
发明人： Mark S. Birrittella
IPC分类号： H01L21/8229 , H01L27/10 , H01L27/102 , H01L29/72 , G11C11/00
CPC分类号： H01L21/8229 , H01L27/1025
摘要： An integrated bipolar RAM cell and process for its manufacture is disclosed. The RAM cell includes first and second cross-coupled bipolar transistors with first and second load elements coupled to the collectors of the first and second transistors, respectively. The load elements can be, for example, diode clamped resistors or lateral PNP transistors. The load elements include regions which are capable of injecting minority carriers into the collectors of the first and second transistors. To avoid charge storage problems and associated reduced switching speed while maintaining high voltage noise immunity, the charge injecting regions are fabricated having an integrated impurity doping less than or equal to about 1.times.10.sup.13 cm.sup.-2.
摘要翻译：公开了一种用于其制造的集成双极型RAM单元及其工艺。 RAM单元包括分别耦合到第一和第二晶体管的集电极的第一和第二负载元件的第一和第二交叉耦合双极晶体管。负载元件可以是例如二极管钳位电阻器或横向PNP晶体管。负载元件包括能够将少数载流子注入第一和第二晶体管的集电极的区域。为了避免电荷存储问题和相关联的降低的开关速度同时保持高电压抗扰性，电荷注入区被制造为具有小于或等于约1×10 13 cm -2的积分杂质掺杂。

16. 发明授权

US4644194A ECL to TTL voltage level translator 失效
标题翻译： ECL到TTL电平转换器
公开(公告)号：US4644194A
公开(公告)日：1987-02-17
申请号：US748362
申请日：1985-06-24
申请人： Mark S. Birrittella , Robert R. Marley , Walter C. Seelbach
发明人： Mark S. Birrittella , Robert R. Marley , Walter C. Seelbach
IPC分类号： H03K19/003 , H03K19/018 , H03K17/10 , H03K17/14 , H03K19/092
CPC分类号： H03K19/00376 , H03K19/01812
摘要： A voltage level translator circuit is provided that translates an input voltage referenced to an ECL supply voltage V.sub.CC to a voltage referenced to a TTL supply voltage V.sub.EE independent of power supply voltage variations. A first and a second embodiment have reference circuits coupled to receive a data input signal for providing a single signal referenced to a first supply voltage terminal to a current mirror. An output circuit is coupled to the current mirror for providing an output signal referenced to the second supply voltage terminal. A third embodiment has a reference circuit coupled to receive a data input signal for referencing a voltage on a first supply voltage terminal to a voltage on a second supply voltage terminal. A voltage setting circuit is coupled to the reference circuit for setting a voltage within the reference circuit. An output circuit is coupled to the voltage setting circuit for providing an output voltage referenced to a voltage on the second voltage terminal and independent of variations in supply voltages.
摘要翻译：提供电压电平转换器电路，其将参考ECL电源电压VCC的输入电压转换为与电源电压变化无关的TTL电源电压VEE。第一和第二实施例具有耦合以接收数据输入信号的参考电路，用于将参考第一电源电压端子的单个信号提供给电流镜。输出电路耦合到电流镜，用于提供参考第二电源电压端子的输出信号。第三实施例具有耦合以接收数据输入信号的参考电路，用于将第一电源电压端子上的电压参考为第二电源电压端子上的电压。电压设定电路与参考电路耦合，用于设定参考电路内的电压。输出电路耦合到电压设置电路，用于提供参考第二电压端子上的电压的输出电压，并且与电源电压的变化无关。

17. 发明授权

US4641047A Complex direct coupled transistor logic 失效
标题翻译：复合直接耦合晶体管逻辑
公开(公告)号：US4641047A
公开(公告)日：1987-02-03
申请号：US627312
申请日：1984-07-02
申请人： Mark S. Birrittella
发明人： Mark S. Birrittella
IPC分类号： H03K19/082 , H03K19/091 , H01L27/04
CPC分类号： H03K19/082 , H03K19/091
摘要： A logic circuit is provided having increased flexibility, increased package density over I2L circuits and improved noise immunity over ISL circuits. A first NPN multi-collector transistor has its collectors coupled wherein each provide an output signal, and a base connected to an input terminal and to the base of a second NPN transistor. The emitter of the second transistor is coupled to receive a first supply voltage, typically ground. The input terminal is coupled to a second supply voltage by a resistor. When monolithically integrated, the emitter and collector of the first and second transistor, respectively, share a common buried epitaxial layer that does not require contact with a metallization layer.
摘要翻译：提供了一种逻辑电路，其具有增加的灵活性，增加了I2L电路上的封装密度，并且提高了超过ISL电路的抗噪声能力。第一NPN多集电极晶体管具有耦合其集电极，其中每个提供输出信号，以及连接到第二NPN晶体管的输入端和基极的基极。第二晶体管的发射极被耦合以接收通常接地的第一电源电压。输入端通过电阻耦合到第二电源电压。当单片集成时，第一和第二晶体管的发射极和集电极分别共享不需要与金属化层接触的公共掩埋外延层。

18. 发明授权

US4631570A Integrated circuit having buried oxide isolation and low resistivity substrate for power supply interconnection 失效
标题翻译：具有埋置氧化物隔离的集成电路和用于电源互连的低电阻衬底
公开(公告)号：US4631570A
公开(公告)日：1986-12-23
申请号：US628019
申请日：1984-07-03
申请人： Mark S. Birrittella , Robert H. Reuss , Walter C. Seelbach
发明人： Mark S. Birrittella , Robert H. Reuss , Walter C. Seelbach
IPC分类号： H01L27/04 , H01L21/762 , H01L21/822 , H01L21/8222 , H01L23/528 , H01L27/06 , H01L27/082 , H01L27/12 , H01L27/02
CPC分类号： H01L21/76243 , H01L23/5286 , H01L27/0825 , H01L2924/0002 , Y10S148/083 , Y10S148/085 , Y10S257/906
摘要： An integrated circuit power supply interconnection technique is disclosed having a highly doped, low resistivity substrate for distribution of the integrated circuit's most positive supply voltage. The substrate functions as the most positive voltage point and accomodates devices that are normally connected directly to this most positive supply voltage. A dielectric buried layer overlies a portion of the substrate and isolates the substrate supply voltage from devices that are not connected directly to the most positive supply voltage.
摘要翻译：公开了一种集成电路电源互连技术，其具有用于分配集成电路最正电源电压的高掺杂的低电阻率衬底。衬底作为最正的电压点，并且适应通常直接连接到最正电源电压的器件。电介质掩埋层覆盖在衬底的一部分上，并将衬底电源电压与不直接连接到最正电源电压的器件隔离。

19. 发明申请

US20150180799A1 HIERARCHICAL/LOSSLESS PACKET PREEMPTION TO REDUCE LATENCY JITTER IN FLOW-CONTROLLED PACKET-BASED NETWORKS 审中-公开
标题翻译：基于分组的网络中的分层/不可信分组预防措施来减少延迟抖动
公开(公告)号：US20150180799A1
公开(公告)日：2015-06-25
申请号：US14136293
申请日：2013-12-20
申请人： Thomas D. Lovett , Albert Cheng , Mark S. Birrittella , James Kunz , Todd Rimmer
发明人： Thomas D. Lovett , Albert Cheng , Mark S. Birrittella , James Kunz , Todd Rimmer
IPC分类号： H04L12/911 , H04L12/851 , H04L1/00
CPC分类号： H04L47/821 , H04L1/0041 , H04L1/0061 , H04L1/0071 , H04L1/1835 , H04L25/14 , H04L47/2441 , H04L47/365 , H04L47/621 , H04L47/6275
摘要： Methods, apparatus, and systems for implementing hierarchical and lossless packet preemption and interleaving to reduce latency jitter in flow-controller packet-based networks. Fabric packets are divided into a plurality of data units, with data units for different fabric packets buffered in separate buffers. Data units are pulled from the buffers and added to a transmit stream in which groups of data units are interleaved. Upon receipt by a receiver, the groups of data units are separated out and buffered in separate buffers under which data units for the same fabric packets are grouped together. In one aspect, each buffer is associated with a respective virtual lane (VL), and the fabric packets are effectively transferred over fabric links using virtual lanes. VLs may have different levels of priority under which data units for fabric packets in higher-priority VLs may preempt fabric packets in lower-priority VLs. By transferring data units rather than entire packets, transmission of a packet can be temporarily paused in favor of a higher-priority packet. Multiple levels of preemption and interleaving in a nested manner are supported.
摘要翻译：用于实现分级和无损数据包抢占和交织以减少流控制器基于分组的网络中的延迟抖动的方法，装置和系统。结构数据包被划分为多个数据单元，不同结构数据包的数据单元缓冲在单独的缓冲区中。数据单元被从缓冲器中拉出并且被添加到数据单元组交错的发送流中。在由接收器接收时，数据单元组被分离出并且在单独的缓冲器中缓冲，在这些缓冲器中，用于相同结构数据包的数据单元被分组在一起。在一个方面，每个缓冲器与相应的虚拟通道（VL）相关联，并且使用虚拟通道在结构链路上有效地传送结构数据包。 VL可以具有不同的优先级，在该优先级下，较高优先级VL中的结构数据包的数据单元可以优先考虑低优先级VL中的结构数据包。通过传送数据单元而不是整个分组，可以临时暂停分组的传输，以利于较高优先级的分组。支持多种级别的抢占和嵌套方式的交错。

20. 发明申请

US20150163170A1 LINK TRANSFER, BIT ERROR DETECTION AND LINK RETRY USING FLIT BUNDLES ASYNCHRONOUS TO LINK FABRIC PACKETS 有权
标题翻译：链接传输，位错误检测和链接恢复使用不相关的链接织布
公开(公告)号：US20150163170A1
公开(公告)日：2015-06-11
申请号：US14099291
申请日：2013-12-06
申请人： Mark S. Birrittella
发明人： Mark S. Birrittella
IPC分类号： H04L12/935 , H04L29/06
CPC分类号： H04L47/36 , H04L49/30 , H04L69/22
摘要： Method, apparatus, and systems for Link Transfer, bit error detection and link retry using flit bundles asynchronous to link Fabric Packets. A first type of packet comprising a Fabric Packet is generated and its data content is divided into multiple data units called “flits.” The flits are then bundled into a second type of packet comprising Link Transfer Packets (LTPs). The LTPs are then sent over single link segments in a fabric comprising many point-to-point links. Each LTP includes a CRC that is used to ensure that data transmitted over each link segment is error free, and comprises a unit of retransmission. The size of the fabric packets may vary, and they may be larger or smaller than an LTP. The transfer scheme enabled flits from multiple fabric packets to be bundled into a single LTP. Upon receipt at a fabric endpoint, the flits from the LTPs are extracted and reassembled to regenerate the Fabric Packets.
摘要翻译：链路传输的方法，设备和系统，使用与链路Fabric数据包异步的flit bundle的位错误检测和链接重试。生成包括Fabric Packet的第一类型的分组，并将其数据内容划分成称为“flits”的多个数据单元。然后，将这些数据包捆绑成包括链路传输分组（LTP）的第二类型的分组。然后，LTP通过包括许多点对点链路的结构中的单个链路段发送。每个LTP包括CRC，用于确保通过每个链路段发送的数据是无错误的，并且包括重传单元。织物分组的大小可以变化，并且它们可以大于或小于LTP。传输方案使来自多个Fabric数据包的传输方案捆绑成一个LTP。在结构端点接收时，提取并重新组合来自LTP的闪烁以重新生成Fabric数据包。

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